SAMA5 ADC+TC: Early debug fixes + lots of new debug instrumentation
This commit is contained in:
Gregory Nutt
parent
28d50790f2
commit
1668aa408e
@ -85,7 +85,7 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Count the number of channels in use */
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/* Count the number of channels in use */
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#define SAMA5_CHAN0_INUSE 0
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#define SAMA5_CHAN1_INUSE 0
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@ -218,7 +218,7 @@
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* is a gain setting for each enabled channel.
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*
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* Valid gain settings are {0, 1, 2, 3} which may be interpreted as
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* either {1, 1, 2, 4} if the DIFFx bit in COR register is zero or as
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* either {1, 1, 2, 4} if the DIFFx bit in COR register is zero or as
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* {0.5, 1, 2, 2} if the DIFFx bit is set.
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*/
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@ -573,7 +573,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
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*
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* Input Parameters
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* arg - The ADC private data structure cast to (void *)
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*
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*
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* Returned Value:
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* None
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*
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@ -588,6 +588,7 @@ static void sam_adc_dmadone(void *arg)
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int chan;
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int i;
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avdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
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ASSERT(priv != NULL && !priv->ready);
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/* If the DMA is disabled, just ignore the data */
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@ -642,6 +643,8 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
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struct sam_adc_s *priv = (struct sam_adc_s *)arg;
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int ret;
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allvdbg("ready=%d enabled=%d\n", priv->enabled, priv->ready);
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/* Check of the bottom half is keeping up with us */
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if (priv->ready && priv->enabled)
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@ -698,6 +701,7 @@ static int sam_adc_dmasetup(FAR struct sam_adc_s *priv, FAR uint8_t *buffer,
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uint32_t paddr;
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uint32_t maddr;
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avdbg("buffer=%p buflen=%d\n", buffer, (int)buflen);
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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DEBUGASSERT(((uint32_t)buffer & 3) == 0);
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@ -728,13 +732,13 @@ static int sam_adc_dmasetup(FAR struct sam_adc_s *priv, FAR uint8_t *buffer,
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* Description:
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* This function executes on the worker thread. It is scheduled by
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* sam_adc_interrupt whenever any enabled end-of-conversion event occurs.
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* All EOC interrupts are disabled when this function runs.
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* All EOC interrupts are disabled when this function runs.
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* sam_adc_endconversion will re-enable EOC interrupts when it completes
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* processing all pending EOC events.
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*
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* Input Parameters
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* arg - The ADC private data structure cast to (void *)
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*
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*
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* Returned Value:
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* None
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*
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@ -748,6 +752,7 @@ static void sam_adc_endconversion(void *arg)
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int chan;
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ASSERT(priv != NULL);
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avdbg("pending=%08x\n", priv->pending);
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/* Get the set of unmasked, pending ADC interrupts */
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@ -877,13 +882,20 @@ static void sam_adc_reset(struct adc_dev_s *dev)
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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uint32_t regval;
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avdbg("Resetting..\n");
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/* NOTE: We can't really reset the ADC hardware without losing the
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* touchscreen configuration.
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*/
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/* Stop any DMA */
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/* Stop any ongoing DMA */
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sam_dmastop(priv->dma);
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#ifdef CONFIG_SAMA5_ADC_DMA
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if (priv->dma)
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{
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sam_dmastop(priv->dma);
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}
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#endif
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/* Stop an release any timer */
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@ -940,6 +952,8 @@ static int sam_adc_setup(struct adc_dev_s *dev)
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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uint32_t regval;
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avdbg("Setup\n");
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/* Enable channel number tag. This bit will force the channel number (CHNB)
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* to be included in the LDCR register content.
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*/
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@ -1006,6 +1020,8 @@ static void sam_adc_shutdown(struct adc_dev_s *dev)
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{
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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avdbg("Shutdown\n");
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/* Disable ADC interrupts, both at the level of the ADC device and at the
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* level of the AIC.
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*/
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@ -1030,6 +1046,8 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
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{
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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avdbg("enable=%d\n", enable);
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#ifdef CONFIG_SAMA5_ADC_DMA
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/* We don't stop the DMA when RX is disabled, we just stop the data transfer */
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@ -1063,6 +1081,8 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
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static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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{
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avdbg("cmd=%d arg=%ld\n", cmd, arg);
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/* No ioctl commands supported:
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*
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* REVISIT: Need to implement a ioctl to support software triggering
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@ -1096,6 +1116,8 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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uint32_t mode;
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int ret;
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avdbg("frequency=%ld channel=%d\n", (long)frequency, channel);
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/* Configure TC for a 1Hz frequency and trigger on RC compare. */
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ret = sam_tc_divisor(frequency, &div, &tcclks);
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@ -1123,7 +1145,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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adbg("ERROR: Failed to allocate channel %d mode %08x\n", channel, mode);
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return -EINVAL;
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}
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/* Set up TC_RA and TC_RC */
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sam_tc_setregister(priv->tc, TC_REGA, div / 2);
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@ -1149,6 +1171,8 @@ static void sam_adc_freetimer(struct sam_adc_s *priv)
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{
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/* Is a timer allocated? */
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avdbg("tc=%p\n", priv->tc);
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if (priv->tc)
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{
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/* Yes.. stop it and free it */
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@ -1174,6 +1198,8 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
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int ret = OK;
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#if defined(CONFIG_SAMA5_ADC_SWTRIG)
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avdbg("Setup software trigger\n");
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/* Configure the software trigger */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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@ -1188,6 +1214,8 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
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sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
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#elif defined(CONFIG_SAMA5_ADC_ADTRG)
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avdbg("Setup ADTRG trigger\n");
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/* Configure the trigger via the external ADTRG signal */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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@ -1213,6 +1241,8 @@ static int sam_adc_trigger(struct sam_adc_s *priv)
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sam_adc_putreg(priv, SAM_ADC_TRGR, regval);
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#elif defined(CONFIG_SAMA5_ADC_TIOATRIG)
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avdbg("Setup timer/counter trigger\n");
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/* Start the timer */
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#if defined(CONFIG_SAMA5_ADC_TIOA0TRIG)
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@ -1291,6 +1321,8 @@ static void sam_adc_autocalibrate(struct sam_adc_s *priv)
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#ifdef CONFIG_SAMA5_ADC_AUTOCALIB
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uint32_t regval;
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avdbg("Entry\n");
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/* Launch an automatic calibration of the ADC cell on next sequence */
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regval = sam_adc_getreg(priv, SAM_ADC_CR);
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@ -1316,6 +1348,8 @@ static void sam_adc_offset(struct sam_adc_s *priv)
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{
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uint32_t regval = 0;
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avdbg("Entry\n");
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#ifdef CONFIG_SAMA5_ADC_ANARCH
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/* Set the offset for each enabled channel. This centers the analog signal
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* on Vrefin/2 before the gain scaling. The Offset applied is: (G-1)Vrefin/2
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@ -1431,6 +1465,8 @@ static void sam_adc_gain(struct sam_adc_s *priv)
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#ifdef CONFIG_SAMA5_ADC_ANARCH
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uint32_t regval;
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avdbg("Entry\n");
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/* Set the gain for each enabled channel */
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regval = 0;
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@ -1475,6 +1511,8 @@ static void sam_adc_gain(struct sam_adc_s *priv)
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sam_adc_putreg(priv, SAM_ADC_CGR, regval);
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#else
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avdbg("Gain=%d\n", CONFIG_SAMA5_ADC_GAIN);
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/* Set GAIN0 only. GAIN0 will be used for all channels. */
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sam_adc_putreg(priv, SAM_ADC_CGR, ADC_CGR_GAIN0(CONFIG_SAMA5_ADC_GAIN));
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@ -1494,9 +1532,11 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
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{
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uint32_t regval;
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avdbg("Entry\n");
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/* Enable/disable the analog change feature */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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#ifdef CONFIG_SAMA5_ADC_ANARCH
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/* Disable analog change: No analog change on channel switching: DIFF0,
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@ -1526,6 +1566,8 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
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#ifdef CONFIG_SAMA5_ADC_SEQUENCER
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static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq)
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{
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avdbg("seqr1=%p seqr2=%p seg=%d\n");
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if (seq > 8)
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{
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*seqr2 |= ADC_SEQR2_USCH(seq, chan);
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@ -1545,6 +1587,8 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
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uint32_t seqr2;
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int seq;
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avdbg("Setup sequencer\n");
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/* Set user configured channel sequence */
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seqr1 = 0;
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@ -1632,6 +1676,8 @@ static void sam_adc_sequencer(struct sam_adc_s *priv)
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#else
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uint32_t regval;
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avdbg("Disable sequencer\n");
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/* Disable the sequencer */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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@ -1653,6 +1699,8 @@ static void sam_adc_channels(struct sam_adc_s *priv)
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{
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uint32_t regval;
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avdbg("Entry\n");
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/* Disable the sequencer */
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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@ -1742,6 +1790,8 @@ struct adc_dev_s *sam_adc_initialize(void)
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if (!priv->initialized)
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{
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avdbg("Initializing...\n");
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/* Disable ADC peripheral clock */
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sam_adc_disableclk();
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@ -1792,7 +1842,7 @@ struct adc_dev_s *sam_adc_initialize(void)
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/* Initialize the public ADC device data structure */
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g_adcdev.ad_ops = &g_adcops;
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g_adcdev.ad_priv = &priv;
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g_adcdev.ad_priv = priv;
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/* Initialize the private ADC device data structure */
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@ -1873,6 +1923,7 @@ struct adc_dev_s *sam_adc_initialize(void)
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/* Return a pointer to the device structure */
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avdbg("Returning %p\n", &g_adcdev);
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return &g_adcdev;
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}
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@ -1888,6 +1939,8 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
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{
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int ret;
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avdbg("Locking\n");
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do
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{
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ret = sem_wait(&priv->exclsem);
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@ -1911,6 +1964,7 @@ void sam_adc_lock(FAR struct sam_adc_s *priv)
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void sam_adc_unlock(FAR struct sam_adc_s *priv)
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{
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avdbg("Unlocking\n");
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sem_post(&priv->exclsem);
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}
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@ -657,7 +657,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table,
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}
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}
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fdbg("No channel found for pid %d\n", pid);
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dmadbg("No channel found for pid %d\n", pid);
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DEBUGPANIC();
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return 0x3f;
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}
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@ -56,6 +56,7 @@
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#include <semaphore.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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@ -90,6 +91,21 @@
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# error Cannot realize TC input frequency
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#endif
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/* Timer debug is enabled if any timer client is enabled */
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#undef DEBUG_TC
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#if defined(CONFIG_SAMA5_ADC)
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# define DEBUG_TC 1
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#endif
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#ifdef DEBUG_TC
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# define tcdbg dbg
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# define tcvdbg vdbg
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#else
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# define wddbg(x...)
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# define wdvdbg(x...)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -110,6 +126,7 @@ struct sam_tcconfig_s
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uintptr_t base; /* TC register base address */
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uint8_t pid; /* Peripheral ID */
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uint8_t chfirst; /* First channel number */
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uint8_t tc; /* Timer/counter number */
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/* Channels */
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@ -191,6 +208,7 @@ static const struct sam_tcconfig_s g_tc012config =
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.base = SAM_TC012_VBASE,
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.pid = SAM_PID_TC0,
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.chfirst = 0,
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.tc = 0,
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.channel =
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{
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{
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@ -257,6 +275,7 @@ static const struct sam_tcconfig_s g_tc345config =
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.base = SAM_TC345_VBASE,
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.pid = SAM_PID_TC1,
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.chfirst = 3,
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.tc = 1,
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.channel =
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{
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{
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@ -586,7 +605,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
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/* Select the timer/counter and get the index associated with the
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* channel.
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*/
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#ifdef CONFIG_SAMA5_TC0
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if (channel >= 0 && channel < 3)
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{
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@ -627,6 +646,8 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
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for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++)
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{
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tcdbg("Initializing TC%d\n", tcconfig->tc);
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/* Initialize the channel data structure */
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chan = &tc->channel[i];
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@ -688,11 +709,16 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
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{
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/* No.. return a failure */
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tcdbg("Channel %d is in-used\n", channel);
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sam_givesem(tc);
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return NULL;
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}
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/* OK.. return the channel with the semaphore locked */
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/* Mark the channel "inuse" */
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chan->inuse = true;
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/* And return the channel with the semaphore locked */
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return chan;
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}
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@ -716,7 +742,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
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* On success, a non-NULL handle value is returned. This handle may be
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* used with subsequent timer/counter interfaces to manage the timer. A
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* NULL handle value is returned on a failure.
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*
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*
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****************************************************************************/
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TC_HANDLE sam_tc_allocate(int channel, int mode)
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@ -727,6 +753,8 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
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* access to the requested channel.
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*/
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tcvdbg("channel=%d mode=%08x\n", channel, mode);
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chan = sam_tc_initialize(channel);
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if (chan)
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{
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@ -749,6 +777,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
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/* Return an opaque reference to the channel */
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tcvdbg("Returning %p\n", chan);
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return (TC_HANDLE)chan;
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}
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@ -763,12 +792,14 @@ TC_HANDLE sam_tc_allocate(int channel, int mode)
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*
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* Returned Value:
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* None
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*
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*
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****************************************************************************/
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void sam_tc_free(TC_HANDLE handle)
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{
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struct sam_chan_s *chan = (struct sam_chan_s *)handle;
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tcvdbg("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse);
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DEBUGASSERT(chan && chan->inuse);
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/* Make sure that the channel is stopped */
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@ -776,7 +807,7 @@ void sam_tc_free(TC_HANDLE handle)
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sam_tc_stop(handle);
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/* Mark the channel as available */
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chan->inuse = false;
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}
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||||
@ -791,14 +822,16 @@ void sam_tc_free(TC_HANDLE handle)
|
||||
* handle Channel handle previously allocated by sam_tc_allocate()
|
||||
*
|
||||
* Returned Value:
|
||||
*
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_tc_start(TC_HANDLE handle)
|
||||
{
|
||||
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
|
||||
|
||||
tcvdbg("Starting channel %d inuse=%d\n", chan->chan, chan->inuse);
|
||||
DEBUGASSERT(chan && chan->inuse);
|
||||
|
||||
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKEN | TC_CCR_SWTRG);
|
||||
}
|
||||
|
||||
@ -812,14 +845,16 @@ void sam_tc_start(TC_HANDLE handle)
|
||||
* handle Channel handle previously allocated by sam_tc_allocate()
|
||||
*
|
||||
* Returned Value:
|
||||
*
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_tc_stop(TC_HANDLE handle)
|
||||
{
|
||||
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
|
||||
|
||||
tcvdbg("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse);
|
||||
DEBUGASSERT(chan && chan->inuse);
|
||||
|
||||
sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS);
|
||||
}
|
||||
|
||||
@ -828,10 +863,9 @@ void sam_tc_stop(TC_HANDLE handle)
|
||||
*
|
||||
* Description:
|
||||
* Set TC_RA, TC_RB, or TC_RB using the provided divisor. The actual
|
||||
* setting in the regsiter will be the TC input frequency divided by
|
||||
* setting in the register will be the TC input frequency divided by
|
||||
* the provided divider (which should derive from the divider returned
|
||||
* by sam_tc_divider).
|
||||
*
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle Channel handle previously allocated by sam_tc_allocate()
|
||||
@ -844,9 +878,15 @@ void sam_tc_stop(TC_HANDLE handle)
|
||||
void sam_tc_setregister(TC_HANDLE handle, int reg, unsigned int div)
|
||||
{
|
||||
struct sam_chan_s *chan = (struct sam_chan_s *)handle;
|
||||
uint32_t regval;
|
||||
|
||||
DEBUGASSERT(reg < TC_NREGISTERS);
|
||||
|
||||
sam_chan_putreg(chan, g_regoffset[reg], TC_FREQUENCY / div);
|
||||
regval = TC_FREQUENCY / div;
|
||||
tcvdbg("Channel %d: Set register %d to %d / %d = %d\n",
|
||||
chan->chan, reg, TC_FREQUENCY, div, (unsigned int)regval);
|
||||
|
||||
sam_chan_putreg(chan, g_regoffset[reg], regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -855,7 +895,6 @@ void sam_tc_setregister(TC_HANDLE handle, int reg, unsigned int div)
|
||||
* Description:
|
||||
* Return the timer input frequency, that is, the MCK frequency divided
|
||||
* down so that the timer/counter is driven within its maximum frequency.
|
||||
* This value needed for
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
@ -899,6 +938,8 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
|
||||
{
|
||||
int ndx = 0;
|
||||
|
||||
tcvdbg("frequency=%d\n", frequency);
|
||||
|
||||
/* Satisfy lower bound */
|
||||
|
||||
while (frequency < (g_divfreq[ndx] >> 16))
|
||||
@ -907,6 +948,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
|
||||
{
|
||||
/* If no divisor can be found, return -ERANGE */
|
||||
|
||||
tcdbg("Lower bound search failed\n");
|
||||
return -ERANGE;
|
||||
}
|
||||
}
|
||||
@ -925,6 +967,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
|
||||
|
||||
if (div)
|
||||
{
|
||||
tcvdbg("return div=%d\n", g_divider[ndx]);
|
||||
*div = g_divider[ndx];
|
||||
}
|
||||
|
||||
@ -932,6 +975,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
|
||||
|
||||
if (tcclks)
|
||||
{
|
||||
tcvdbg("return tcclks=%d\n", ndx);
|
||||
*tcclks = ndx;
|
||||
}
|
||||
|
||||
|
||||
@ -164,7 +164,7 @@ void sam_tc_stop(TC_HANDLE handle);
|
||||
*
|
||||
* Description:
|
||||
* Set TC_RA, TC_RB, or TC_RB using the provided divisor. The actual
|
||||
* setting in the regsiter will be the TC input frequency divided by
|
||||
* setting in the register will be the TC input frequency divided by
|
||||
* the provided divider (which should derive from the divider returned
|
||||
* by sam_tc_divider).
|
||||
*
|
||||
|
||||
118
configs/sama5d3x-ek/src/sam_adc.c
Normal file
118
configs/sama5d3x-ek/src/sam_adc.c
Normal file
@ -0,0 +1,118 @@
|
||||
/************************************************************************************
|
||||
* configs/sama5d3x-ek/src/up_adc.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
#include "sam_adc.h"
|
||||
#include "sama5d3x-ek.h"
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: adc_devinit
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following interface to work with
|
||||
* examples/adc.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int adc_devinit(void)
|
||||
{
|
||||
#ifdef CONFIG_SAMA5_ADC
|
||||
static bool initialized = false;
|
||||
struct adc_dev_s *adc;
|
||||
int ret;
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = sam_adc_initialize();
|
||||
if (adc == NULL)
|
||||
{
|
||||
adbg("ERROR: Failed to get ADC interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register("/dev/adc0", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
adbg("adc_register failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Now we are initialized */
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
#else
|
||||
return -ENOSYS;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC */
|
||||
Loading…
Reference in New Issue
Block a user