imxrt: FlexCAN driver
Signed-off-by: Michal Lenc <lencmich@fel.cvut.cz>
This commit is contained in:
Michal Lenc
Alan Carvalho de Assis
parent
67c0af650f
commit
1670709187
@ -155,6 +155,11 @@ config IMXRT_HAVE_LPUART
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bool
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default n
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config IMXRT_FLEXCAN
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bool
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default n
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select ARCH_HAVE_NETDEV_STATISTICS
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config IMXRT_LPI2C
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bool
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default n
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@ -411,6 +416,94 @@ config IMXRT_LPUART_INVERT
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endmenu # LPUART Configuration
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menu "FLEXCAN Peripherals"
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config IMXRT_FLEXCAN1
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bool "FLEXCAN1"
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default n
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select IMXRT_FLEXCAN
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select NET_CAN_HAVE_TX_DEADLINE
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config IMXRT_FLEXCAN2
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bool "FLEXCAN2"
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default n
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select IMXRT_FLEXCAN
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select NET_CAN_HAVE_TX_DEADLINE
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config IMXRT_FLEXCAN3
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bool "FLEXCAN3"
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default n
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select IMXRT_FLEXCAN
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select NET_CAN_HAVE_TX_DEADLINE
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select NET_CAN_HAVE_CANFD
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endmenu # FLEXCAN Peripherals
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menu "FLEXCAN1 Configuration"
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depends on IMXRT_FLEXCAN1
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config FLEXCAN1_BITRATE
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int "CAN bitrate"
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depends on !NET_CAN_CANFD
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default 1000000
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config FLEXCAN1_SAMPLEP
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int "CAN sample point"
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depends on !NET_CAN_CANFD
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default 80
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endmenu # IMXRT_FLEXCAN1
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menu "FLEXCAN2 Configuration"
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depends on IMXRT_FLEXCAN2
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config FLEXCAN2_BITRATE
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int "CAN bitrate"
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depends on !NET_CAN_CANFD
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default 1000000
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config FLEXCAN2_SAMPLEP
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int "CAN sample point"
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depends on !NET_CAN_CANFD
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default 80
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endmenu # IMXRT_FLEXCAN2
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menu "FLEXCAN3 Configuration"
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depends on IMXRT_FLEXCAN3
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config FLEXCAN3_BITRATE
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int "CAN bitrate"
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depends on !NET_CAN_CANFD
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default 1000000
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config FLEXCAN3_SAMPLEP
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int "CAN sample point"
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depends on !NET_CAN_CANFD
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default 80
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config FLEXCAN3_ARBI_BITRATE
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int "CAN FD Arbitration phase bitrate"
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depends on NET_CAN_CANFD
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default 1000000
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config FLEXCAN3_ARBI_SAMPLEP
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int "CAN FD Arbitration phase sample point"
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depends on NET_CAN_CANFD
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default 80
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config FLEXCAN3_DATA_BITRATE
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int "CAN FD Data phase bitrate"
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depends on NET_CAN_CANFD
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default 4000000
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config FLEXCAN3_DATA_SAMPLEP
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int "CAN FD Data phase sample point"
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depends on NET_CAN_CANFD
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default 90
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endmenu # IMXRT_FLEXCAN3
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menu "LPI2C Peripherals"
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menuconfig IMXRT_LPI2C1
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@ -133,6 +133,10 @@ ifeq ($(CONFIG_IMXRT_LCD),y)
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CHIP_CSRCS += imxrt_lcd.c
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endif
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ifeq ($(CONFIG_IMXRT_FLEXCAN),y)
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CHIP_CSRCS += imxrt_flexcan.c
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endif
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ifeq ($(CONFIG_IMXRT_SNVS_LPSRTC),y)
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CHIP_CSRCS += imxrt_lpsrtc.c
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CHIP_CSRCS += imxrt_hprtc.c
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482
arch/arm/src/imxrt/hardware/imxrt_flexcan.h
Normal file
482
arch/arm/src/imxrt/hardware/imxrt_flexcan.h
Normal file
@ -0,0 +1,482 @@
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/****************************************************************************************************
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* arch/arm/src/imxrt/hardware/imxrt_flexcan.h
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*
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* Copyright (C) 2020 Gregory Nutt. All rights reserved.
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* Author: Michal Lenc <lencmich@fel.cvut.cz>
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*
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* Based on: arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXCAN_H
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#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXCAN_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define IMXRT_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */
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#define IMXRT_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */
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#define IMXRT_CAN_TIMER_OFFSET 0x0008 /* Free Running Timer */
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#define IMXRT_CAN_RXMGMASK_OFFSET 0x0010 /* Rx Mailboxes Global Mask Register */
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#define IMXRT_CAN_RX14MASK_OFFSET 0x0014 /* Rx 14 Mask Register */
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#define IMXRT_CAN_RX15MASK_OFFSET 0x0018 /* Rx 15 Mask Register */
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#define IMXRT_CAN_ECR_OFFSET 0x001c /* Error Counter */
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#define IMXRT_CAN_ESR1_OFFSET 0x0020 /* Error and Status 1 Register */
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#define IMXRT_CAN_IMASK2_OFFSET 0x0024 /* Interrupt Masks 2 Register */
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#define IMXRT_CAN_IMASK1_OFFSET 0x0028 /* Interrupt Masks 1 Register */
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#define IMXRT_CAN_IFLAG2_OFFSET 0x002c /* Interrupt Flags 2 Register */
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#define IMXRT_CAN_IFLAG1_OFFSET 0x0030 /* Interrupt Flags 1 Register */
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#define IMXRT_CAN_CTRL2_OFFSET 0x0034 /* Control 2 Register */
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#define IMXRT_CAN_ESR2_OFFSET 0x0038 /* Error and Status 2 Register */
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#define IMXRT_CAN_CRCR_OFFSET 0x0044 /* CRC Register */
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#define IMXRT_CAN_RXFGMASK_OFFSET 0x0048 /* Rx FIFO Global Mask Register */
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#define IMXRT_CAN_RXFIR_OFFSET 0x004c /* Rx FIFO Information Register */
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#define IMXRT_CAN_CBT_OFFSET 0x0050 /* CAN Bit Timing Register */
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#define IMXRT_CAN_MB_OFFSET 0x0080 /* CAN MB register */
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#define IMXRT_CAN_RXIMR_OFFSET(n) (0x0880+((n)<<2)) /* Rn Individual Mask Registers */
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#define IMXRT_CAN_RXIMR0_OFFSET 0x0880 /* R0 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR1_OFFSET 0x0884 /* R1 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR2_OFFSET 0x0888 /* R2 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR3_OFFSET 0x088c /* R3 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR4_OFFSET 0x0890 /* R4 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR5_OFFSET 0x0894 /* R5 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR6_OFFSET 0x0898 /* R6 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR7_OFFSET 0x089c /* R7 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR8_OFFSET 0x08a0 /* R8 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR9_OFFSET 0x08a4 /* R9 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR10_OFFSET 0x08a8 /* R10 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR11_OFFSET 0x08ac /* R11 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR12_OFFSET 0x08b0 /* R12 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR13_OFFSET 0x08b4 /* R13 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR14_OFFSET 0x08b8 /* R14 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR15_OFFSET 0x08bc /* R15 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR16_OFFSET 0x08c0 /* R16 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR17_OFFSET 0x08c4 /* R17 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR18_OFFSET 0x08c8 /* R18 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR19_OFFSET 0x08cc /* R19 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR20_OFFSET 0x08d0 /* R20 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR21_OFFSET 0x08d4 /* R21 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR22_OFFSET 0x08d8 /* R22 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR23_OFFSET 0x08dc /* R23 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR24_OFFSET 0x08e0 /* R24 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR25_OFFSET 0x08e4 /* R25 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR26_OFFSET 0x08e8 /* R26 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR27_OFFSET 0x08ec /* R27 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR28_OFFSET 0x08f0 /* R28 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR29_OFFSET 0x08f4 /* R29 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR30_OFFSET 0x08f8 /* R30 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR31_OFFSET 0x08fc /* R31 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR32_OFFSET 0x0900 /* R32 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR33_OFFSET 0x0904 /* R33 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR34_OFFSET 0x0908 /* R34 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR35_OFFSET 0x090c /* R35 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR36_OFFSET 0x0910 /* R36 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR37_OFFSET 0x0914 /* R37 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR38_OFFSET 0x0918 /* R38 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR39_OFFSET 0x091c /* R39 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR40_OFFSET 0x0920 /* R40 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR41_OFFSET 0x0924 /* R41 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR42_OFFSET 0x0928 /* R42 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR43_OFFSET 0x092c /* R43 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR44_OFFSET 0x0930 /* R44 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR45_OFFSET 0x0934 /* R45 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR46_OFFSET 0x0938 /* R46 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR47_OFFSET 0x093c /* R47 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR48_OFFSET 0x0940 /* R48 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR49_OFFSET 0x0944 /* R49 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR50_OFFSET 0x0948 /* R50 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR51_OFFSET 0x094c /* R51 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR52_OFFSET 0x0950 /* R52 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR53_OFFSET 0x0954 /* R53 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR54_OFFSET 0x0958 /* R54 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR55_OFFSET 0x095c /* R55 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR56_OFFSET 0x0960 /* R56 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR57_OFFSET 0x0964 /* R57 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR58_OFFSET 0x0968 /* R58 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR59_OFFSET 0x096c /* R59 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR60_OFFSET 0x0970 /* R60 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR61_OFFSET 0x0974 /* R61 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR62_OFFSET 0x0978 /* R62 Individual Mask Registers */
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#define IMXRT_CAN_RXIMR63_OFFSET 0x097c /* R63 Individual Mask Registers */
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#ifdef CONFIG_IMXRT_FLEXCAN3
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#define IMXRT_CAN_FDCTRL_OFFSET 0x0c00 /* CAN FD Control Register */
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#define IMXRT_CAN_FDCBT_OFFSET 0x0c04 /* CAN FD Bit Timing Register */
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#define IMXRT_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */
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#endif /* CONFIG_IMXRT_FLEXCAN3 */
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/* Register Bit Definitions *************************************************************************/
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/* Module Configuration Register */
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#define CAN_MCR_MAXMB_SHIFT (0) /* Bits 0-6: Number of the Last Message Buffer */
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#define CAN_MCR_MAXMB_MASK (0x7f << CAN_MCR_MAXMB_SHIFT)
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/* Bit 7: Reserved */
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#define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-9: ID Acceptance Mode */
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#define CAN_MCR_IDAM_MASK (3 << CAN_MCR_IDAM_SHIFT)
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# define CAN_MCR_IDAM_FMTA (0 << CAN_MCR_IDAM_SHIFT) /* Format A: One full ID */
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# define CAN_MCR_IDAM_FMTB (1 << CAN_MCR_IDAM_SHIFT) /* Format B: Two full (or partial) IDs */
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# define CAN_MCR_IDAM_FMTC (2 << CAN_MCR_IDAM_SHIFT) /* Format C: Four partial IDs */
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# define CAN_MCR_IDAM_FMTD (3 << CAN_MCR_IDAM_SHIFT) /* Format D: All frames rejected */
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/* Bit 10: Reserved */
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#ifdef CONFIG_IMXRT_FLEXCAN3
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# define CAN_MCR_FDEN (1 << 11) /* Bit 11: CAN FD Operation Enable */
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#endif /* Bit 11: Reserved for FlexCAN1 and FlexCAN2 */
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#define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */
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#define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */
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/* Bit 14: Reserved */
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#ifdef CONFIG_IMXRT_FLEXCAN3
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# define CAN_MCR_DMA (1 << 15) /* Bit 15: DMA Enable */
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#endif /* Bit 15: Reserved for FlexCAN1 and FlexCAN2 */
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#define CAN_MCR_IRMQ (1 << 16) /* Bit 16: Individual Rx Masking and Queue Enable */
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#define CAN_MCR_SRXDIS (1 << 17) /* Bit 17: Self Reception Disable */
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#ifdef CONFIG_IMXRT_FLEXCAN3
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# define CAN_MCR_DOZE (1 << 18) /* Bit 18: Doze Mode Enable */
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#endif /* Bit 18: Reserved for FlexCAN1 and FlexCAN2 */
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#define CAN_MCR_WAKSRC (1 << 19) /* Bit 19: Wake Up Source */
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#define CAN_MCR_LPMACK (1 << 20) /* Bit 20: Low Power Mode Acknowledge */
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#define CAN_MCR_WRNEN (1 << 21) /* Bit 21: Warning Interrupt Enable */
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#define CAN_MCR_SLFWAK (1 << 22) /* Bit 22: Self Wake Up */
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#define CAN_MCR_SUPV (1 << 23) /* Bit 23: Supervisor Mode */
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#define CAN_MCR_FRZACK (1 << 24) /* Bit 24: Freeze Mode Acknowledge */
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#define CAN_MCR_SOFTRST (1 << 25) /* Bit 25: Soft Reset */
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#define CAN_MCR_WAKMSK (1 << 26) /* Bit 26: Wake Up Interrupt Mask */
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#define CAN_MCR_NOTRDY (1 << 27) /* Bit 27: FlexCAN Not Ready */
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#define CAN_MCR_HALT (1 << 28) /* Bit 28: Halt FlexCAN */
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#define CAN_MCR_RFEN (1 << 29) /* Bit 29: Rx FIFO Enable */
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#define CAN_MCR_FRZ (1 << 30) /* Bit 30: Freeze Enable */
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#define CAN_MCR_MDIS (1 << 31) /* Bit 31: Module Disable */
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/* Control 1 Register */
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#define CAN_CTRL1_PROPSEG_SHIFT (0) /* Bits 0-2: Propagation Segment */
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#define CAN_CTRL1_PROPSEG_MASK (7 << CAN_CTRL1_PROPSEG_SHIFT)
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#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
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#define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */
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#define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */
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#define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */
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#define CAN_CTRL1_BOFFREC (1 << 6) /* Bit 6: Bus Off Recovery */
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#define CAN_CTRL1_SMP (1 << 7) /* Bit 7: CAN Bit Sampling */
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/* Bits 8-9: Reserved */
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#define CAN_CTRL1_RWRNMSK (1 << 10) /* Bit 10: Rx Warning Interrupt Mask */
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#define CAN_CTRL1_TWRNMSK (1 << 11) /* Bit 11: Tx Warning Interrupt Mask */
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#define CAN_CTRL1_LPB (1 << 12) /* Bit 12: Loop Back Mode */
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#ifdef CONFIG_IMXRT_FLEXCAN3
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# define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */
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#endif /* Bit 13: Reserved for FlexCAN1 and FlexCAN2 */
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#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */
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#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */
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#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */
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#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT)
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#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
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#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-21: Phase Segment 1 */
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#define CAN_CTRL1_PSEG1_MASK (7 << CAN_CTRL1_PSEG1_SHIFT)
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#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
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#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-23: Resync Jump Width */
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#define CAN_CTRL1_RJW_MASK (3 << CAN_CTRL1_RJW_SHIFT)
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#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
|
||||
#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-31: Prescaler Division Factor */
|
||||
#define CAN_CTRL1_PRESDIV_MASK (0xff << CAN_CTRL1_PRESDIV_SHIFT)
|
||||
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
|
||||
|
||||
/* Free Running Timer */
|
||||
|
||||
#define CAN_TIMER_SHIFT (0) /* Bits 0-15: Timer value */
|
||||
#define CAN_TIMER_MASK (0xffff << CAN_TIMER_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* Rx Mailboxes Global Mask Register (32 Rx Mailboxes Global Mask Bits) */
|
||||
|
||||
#define CAN_RXMGMASK(n) (1 << (n)) /* Bit n: Rx Mailboxe n Global Mask Bit */
|
||||
|
||||
/* Rx 14 Mask Register */
|
||||
|
||||
#define CAN_RX14MASK(n) (1 << (n)) /* Bit n: Rx Buffer 14 Mask Bit n */
|
||||
|
||||
/* Rx 15 Mask Register */
|
||||
|
||||
#define CAN_RX15MASK(n) (1 << (n)) /* Bit n: Rx Buffer 15 Mask Bit n */
|
||||
|
||||
/* Error Counter */
|
||||
|
||||
#define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-7: Transmit Error Counter */
|
||||
#define CAN_ECR_TXERRCNT_MASK (0xff << CAN_ECR_TXERRCNT_SHIFT)
|
||||
#define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-15: Receive Error Counter */
|
||||
#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT)
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN3
|
||||
# define CAN_ECR_TXERRCNTFAST_SHIFT (16) /* Bits 16-23: Transmit Error Counter for fast bits */
|
||||
# define CAN_ECR_TXERRCNTFAST_MASK (0xff << CAN_ECR_TXERRCNTFAST_SHIFT)
|
||||
# define CAN_ECR_RXERRCNTFAST_SHIFT (24) /* Bits 24-31: Receive Error Counter for fast bits */
|
||||
# define CAN_ECR_RXERRCNTFAST_MASK (0xff << CAN_ECR_RXERRCNTFAST_SHIFT)
|
||||
#endif /* Bits 16-31: Reserved for FlexCAN1 and FlexCAN2 */
|
||||
|
||||
/* Error and Status 1 Register */
|
||||
|
||||
#define CAN_ESR1_WAKINT (1 << 0) /* Bit 0: Wake-Up Interrupt */
|
||||
#define CAN_ESR1_ERRINT (1 << 1) /* Bit 1: Error Interrupt */
|
||||
#define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: 'Bus Off' Interrupt */
|
||||
#define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception */
|
||||
#define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-5: Fault Confinement State */
|
||||
#define CAN_ESR1_FLTCONF_MASK (3 << CAN_ESR1_FLTCONF_SHIFT)
|
||||
# define CAN_ESR1_FLTCONF_ACTV (0 << CAN_ESR1_FLTCONF_SHIFT)
|
||||
/* Error Active */
|
||||
# define CAN_ESR1_FLTCONF_PASV (1 << CAN_ESR1_FLTCONF_SHIFT)
|
||||
/* Error Passive */
|
||||
# define CAN_ESR1_FLTCONF_OFF (2 << CAN_ESR1_FLTCONF_SHIFT)
|
||||
/* Bus Off */
|
||||
#define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN in Transmission */
|
||||
#define CAN_ESR1_IDLE (1 << 7) /* Bit 7: CAN bus is in IDLE state */
|
||||
#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */
|
||||
#define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning */
|
||||
#define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error */
|
||||
#define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error */
|
||||
#define CAN_ESR1_CRCERR (1 << 12) /* Bit 12: Cyclic Redundancy Check Error */
|
||||
#define CAN_ESR1_ACKERR (1 << 13) /* Bit 13: Acknowledge Error */
|
||||
#define CAN_ESR1_BIT0ERR (1 << 14) /* Bit 14: Bit0 Error */
|
||||
#define CAN_ESR1_BIT1ERR (1 << 15) /* Bit 15: Bit1 Error */
|
||||
#define CAN_ESR1_RWRNINT (1 << 16) /* Bit 16: Rx Warning Interrupt Flag */
|
||||
#define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */
|
||||
#define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN3
|
||||
#define CAN_ESR1_BOFFDONEINT (1 << 19) /* Bit 19: Bus Off Done Interrupt */
|
||||
#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Iterrupt for Errors Detected in Data Phase of CAN FD frames */
|
||||
#define CAN_ESR1_ERROVR (1 << 21) /* Bit 21: Error Overrun */
|
||||
/* Bits 21-25: Reserved */
|
||||
#define CAN_ESR1_STFERRFAST (1 << 26) /* Bit 26: Stuffing Error in the Data Phase of CAN FD frames */
|
||||
#define CAN_ESR1_FRMERRFAST (1 << 27) /* Bit 27: Form Error in the Data Phase of CAN FD frames */
|
||||
#define CAN_ESR1_CRCERRFAST (1 << 28) /* Bit 28: Cyclic Redundancy Check Error in the CRC field of CAN FD frames */
|
||||
/* Bit 29: Reserved */
|
||||
#define CAN_ESR1_BIT0ERRFAST (1 << 30) /* Bit 30: Bit0 Error in the Data Phase of CAN FD frames */
|
||||
#define CAN_ESR1_BIT1ERRFAST (1 << 31) /* Bit 31: Bit1 Error in the Data Phase of CAN FD frames */
|
||||
#endif /* Bits 19-31: Reserved for FlexCAN1 and FlexCAN2 */
|
||||
|
||||
/* Interrupt Masks 2 Register */
|
||||
|
||||
#define CAN_IMASK2(n) (1 << (n)) /* Bit n: Buffer MBn Mask */
|
||||
|
||||
/* Interrupt Masks 1 Register */
|
||||
|
||||
#define CAN_IMASK1(n) (1 << (n)) /* Bit n: Buffer MBn Mask */
|
||||
|
||||
/* Interrupt Flags 2 Register */
|
||||
|
||||
#define CAN_IFLAG2(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt */
|
||||
|
||||
/* Interrupt Flags 1 Register */
|
||||
|
||||
#define CAN_IFLAG1(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt, n=0..4,8..31 */
|
||||
|
||||
/* Control 2 Register */
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN3
|
||||
/* Bits 0-10: Reserved */
|
||||
# define CAN_CTRL2_EDFLTDIS (1 << 11) /* Bit 11: Edge Filter Disable */
|
||||
# define CAN_CTRL2_ISOCANFDEN (1 << 12) /* Bit 12: ISO CAN FD Enable */
|
||||
/* Bit 13: Reserved */
|
||||
# define CAN_CTRL2_PREXCEN (1 << 14) /* Bit 14: Protocol Exception Enable */
|
||||
# define CAN_CTRL2_TIMERSRC (1 << 15) /* Bit 15: Timer Source */
|
||||
#endif /* Bits 0-15: Reserved for FlexCAN1 and FlexCAN2 */
|
||||
#define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable (Rx) */
|
||||
#define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */
|
||||
#define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Mailboxes Reception Priority */
|
||||
#define CAN_CTRL2_TASD_SHIFT (19) /* Bits 19-23: Tx Arbitration Start Delay */
|
||||
#define CAN_CTRL2_TASD_MASK (31 << CAN_CTRL2_TASD_SHIFT)
|
||||
#define CAN_CTRL2_RFFN_SHIFT (24) /* Bits 24-27: Number of Rx FIFO Filters */
|
||||
#define CAN_CTRL2_RFFN_MASK (15 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_8MB (0 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_16MB (1 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_24MB (2 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_32MB (3 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_40MB (4 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_48MB (5 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_56MB (6 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_64MB (7 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_72MB (8 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_80MB (9 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_88MB (10 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_96MB (11 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_104MB (12 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_112MB (13 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_120MB (14 << CAN_CTRL2_RFFN_SHIFT)
|
||||
# define CAN_CTRL2_RFFN_128MB (15 << CAN_CTRL2_RFFN_SHIFT)
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN3
|
||||
/* Bits 28-29: Reserved */
|
||||
# define CAN_CTRL2_BOFFDONEMSK (1 << 30) /* Bit 30: Bus Off Done Interrupt Mask */
|
||||
# define CAN_CTRL2_ERRMSKFAST (1 << 31) /* Bit 31: Error Interrupt for Errors Detected in the Data Phase of CAN FD frames */
|
||||
#else
|
||||
# define CAN_CTRL2_WRMFRZ (1 << 28) /* Bit 28: Enable unrestricted write access to FlexCAN memory in Freeze mode */
|
||||
/* Bits 29-31: Reserved */
|
||||
#endif
|
||||
|
||||
/* Error and Status 2 Register */
|
||||
|
||||
/* Bits 0-12: Reserved */
|
||||
#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */
|
||||
#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */
|
||||
/* Bit 15: Reserved */
|
||||
#define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */
|
||||
#define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT)
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
/* CRC Register */
|
||||
|
||||
#define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */
|
||||
#define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT)
|
||||
/* Bit 15: Reserved */
|
||||
#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */
|
||||
#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT)
|
||||
/* Bits 23-31: Reserved */
|
||||
|
||||
/* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */
|
||||
|
||||
#define CAN_RXFGMASK(n) (1 << (n)) /* Bit n: Rx FIFO n Global Mask Bit */
|
||||
|
||||
/* Rx FIFO Information Register */
|
||||
|
||||
/* Bits 9-31: Reserved */
|
||||
#define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-8: Identifier Acceptance Filter Hit Indicator */
|
||||
#define CAN_RXFIR_IDHIT_MASK (0x1ff << CAN_RXFIR_IDHIT_SHIFT)
|
||||
|
||||
/* Rx Individual Mask Registers */
|
||||
|
||||
#define CAN_RXIMR(n) (1 << (n)) /* Bit n: Individual Mask Bits */
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN3
|
||||
|
||||
/* CAN Bit Timing register */
|
||||
|
||||
#define CAN_CBT_EPSEG2_SHIFT (0) /* Bits 0-4: Extended Phase Segment 2 */
|
||||
#define CAN_CBT_EPSEG2_MASK (0x1f << CAN_CBT_EPSEG2_SHIFT)
|
||||
#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
|
||||
#define CAN_CBT_EPSEG1_SHIFT (5) /* Bits 5-9: Extended Phase Segment 1 */
|
||||
#define CAN_CBT_EPSEG1_MASK (0x1f << CAN_CBT_EPSEG1_SHIFT)
|
||||
#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
|
||||
#define CAN_CBT_EPROPSEG_SHIFT (10) /* Bits 10-15: Extended Propagation Segment */
|
||||
#define CAN_CBT_EPROPSEG_MASK (0x1f << CAN_CBT_EPROPSEG_SHIFT)
|
||||
#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
|
||||
#define CAN_CBT_ERJW_SHIFT (16) /* Bits 16-20: Extended Resync Jump Width */
|
||||
#define CAN_CBT_ERJW_MASK (0x1f << CAN_CBT_ERJW_SHIFT)
|
||||
#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
|
||||
#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extendet Prescaler Division Factor */
|
||||
#define CAN_CBT_EPRESDIV_MASK (0x3ff << CAN_CBT_EPRESDIV_SHIFT)
|
||||
#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
|
||||
#define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */
|
||||
|
||||
/* CAN FD Control register */
|
||||
|
||||
#define CAN_FDCTRL_TDCVAL_SHIFT (0) /* Bits 0-5: Transceiver Delay Compensation Value */
|
||||
#define CAN_FDCTRL_TDCVAL_MASK (0x3f << CAN_FDCTRL_TDCVAL_SHIFT)
|
||||
/* Bits 6-7: Reserved */
|
||||
#define CAN_FDCTRL_TDCOFF_SHIFT (8) /* Bits 8-12: Transceiver Delay Compensation Offset */
|
||||
#define CAN_FDCTRL_TDCOFF_MASK (0x3f << CAN_FDCTRL_TDCOFF_SHIFT)
|
||||
#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
|
||||
/* Bit 13: Reserved */
|
||||
#define CAN_FDCTRL_TDCFAIL (1 << 14) /* Bit 14: Transceiver Delay Compensation Fail */
|
||||
#define CAN_FDCTRL_TDCEN (1 << 15) /* Bit 15: Transceiver Delay Compensation Enable */
|
||||
#define CAN_FDCTRL_MBDSR0_SHIFT (16) /* Bits 16-17: Message Buffer Data Size for Region 0 */
|
||||
#define CAN_FDCTRL_MBDSR0_MASK (0x3 << CAN_FDCTRL_MBDSR0_SHIFT)
|
||||
#define CAN_FDCTRL_MSBSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
|
||||
/* Bit 18: Reserved */
|
||||
#define CAN_FDCTRL_MBDSR1_SHIFT (19) /* Bits 19-20: Message Buffer Data Size for Region 2 */
|
||||
#define CAN_FDCTRL_MBDSR1_MASK (0x3 << CAN_FDCTRL_MBDSR1_SHIFT)
|
||||
#define CAN_FDCTRL_MSBSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
|
||||
/* Bits 21-30: Reserved */
|
||||
#define CAN_FDCTRL_FDRATE (1 << 31) /* Bit 31: Bit Rate Switch Enable */
|
||||
|
||||
/* CAN FD Bit Timing register */
|
||||
|
||||
#define CAN_FDCBT_FPSEG2_SHIFT (0) /* Bits 0-2: Fast Phase Segment 2 */
|
||||
#define CAN_FDCBT_FPSEG2_MASK (0x7 << CAN_FDCBT_FPSEG2_SHIFT)
|
||||
#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
|
||||
/* Bits 3-4: Reserved */
|
||||
#define CAN_FDCBT_FPSEG1_SHIFT (5) /* Bits 5-7: Fast Phase Segment 1 */
|
||||
#define CAN_FDCBT_FPSEG1_MASK (0x7 << CAN_FDCBT_FPSEG1_SHIFT)
|
||||
#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
|
||||
/* Bits 8-9: Reserved */
|
||||
#define CAN_FDCBT_FPROPSEG_SHIFT (10) /* Bits 10-14: Fast Propagation Segment */
|
||||
#define CAN_FDCBT_FPROPSEG_MASK (0x1f << CAN_FDCBT_FPROPSEG_SHIFT)
|
||||
#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
|
||||
/* Bit 15: Reserved */
|
||||
#define CAN_FDCBT_FRJW_SHIFT (16) /* Bits 16-18: Fast Propagation Segment */
|
||||
#define CAN_FDCBT_FRJW_MASK (0x7 << CAN_FDCBT_FRJW_SHIFT)
|
||||
#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
|
||||
/* Bit 19: Reserved */
|
||||
#define CAN_FDCBT_FPRESDIV_SHIFT (20) /* Bits 20-29: Fast Propagation Segment */
|
||||
#define CAN_FDCBT_FPRESDIV_MASK (0x3ff << CAN_FDCBT_FPRESDIV_SHIFT)
|
||||
#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
|
||||
/* Bits 30-31: Reserved */
|
||||
|
||||
/* CAN FD CRC register */
|
||||
|
||||
#define CAN_FDCRC_FD_TXCRC_SHIFT (0) /* Bits 0-20: Extended Tranmitted CRC value */
|
||||
#define CAN_FDCRC_FD_TXCRC_MASK (0x1fffff << CAN_FDCRC_FD_TXCRC_SHIFT)
|
||||
#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
|
||||
/* Bits 21-23: Reserved */
|
||||
#define CAN_FDCRC_FD_MBCRC_SHIFT (24) /* Bits 24-30: Extended Tranmitted CRC value */
|
||||
#define CAN_FDCRC_FD_MBCRC_MASK (0x7f << CAN_FDCRC_FD_MBCRC_SHIFT)
|
||||
#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
|
||||
/* Bit 31: Reserved */
|
||||
|
||||
#endif /* CONFIG_IMXRT_FLEXCAN3 */
|
||||
|
||||
/* CAN MB TX codes */
|
||||
#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */
|
||||
#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */
|
||||
#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */
|
||||
/* MB is a TX Remote Request Frame (when MB RTR = 1). */
|
||||
#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */
|
||||
/* an incoming Remote Request Frame. */
|
||||
#define CAN_TXMB_NOTUSED 0xF /* Not used.*/
|
||||
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXCAN_H */
|
||||
@ -165,6 +165,9 @@
|
||||
#define IOMUX_ENET_TX_CLK_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
|
||||
IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE )
|
||||
|
||||
#define IOMUX_CAN_DEFAULT (IOMUX_SLEW_SLOW | \
|
||||
IOMUX_DRIVE_50OHM | IOMUX_SPEED_LOW )
|
||||
|
||||
#define IOMUX_USDHC1_DATAX_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \
|
||||
IOMUX_PULL_UP_47K | IOMUX_SCHMITT_TRIGGER)
|
||||
#define IOMUX_USDHC1_CMD_DEFAULT (IOMUX_SLEW_FAST | IOMUX_DRIVE_130OHM | \
|
||||
|
||||
@ -84,6 +84,7 @@
|
||||
#define IMXRT_CCM_CCGR4_OFFSET 0x0078 /* CCM Clock Gating Register 4 */
|
||||
#define IMXRT_CCM_CCGR5_OFFSET 0x007c /* CCM Clock Gating Register 5 */
|
||||
#define IMXRT_CCM_CCGR6_OFFSET 0x0080 /* CCM Clock Gating Register 6 */
|
||||
#define IMXRT_CCM_CCGR7_OFFSET 0x0084 /* CCM Clock Gating Register 7 */
|
||||
/* 0x0084 Reserved */
|
||||
#define IMXRT_CCM_CMEOR_OFFSET 0x0088 /* CCM Module Enable Override Register */
|
||||
|
||||
@ -138,6 +139,7 @@
|
||||
#define IMXRT_CCM_CCGR4 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET)
|
||||
#define IMXRT_CCM_CCGR5 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET)
|
||||
#define IMXRT_CCM_CCGR6 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET)
|
||||
#define IMXRT_CCM_CCGR7 (IMXRT_CCM_BASE + IMXRT_CCM_CCGR7_OFFSET)
|
||||
#define IMXRT_CCM_CMEOR (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET)
|
||||
|
||||
#define IMXRT_CCM_ANALOG_PLL_ARM (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET)
|
||||
@ -764,6 +766,14 @@
|
||||
#define CCM_CCGR_USDHC1 IMXRT_CCM_CCGR6, 1
|
||||
#define CCM_CCGR_USBOH3 IMXRT_CCM_CCGR6, 0
|
||||
|
||||
#define CCM_CCGR_FLEXIO IMXRT_CCM_CCGR7, 6
|
||||
#define CCM_CCGR_AIPS IMXRT_CCM_CCGR7, 5
|
||||
#define CCM_CCGR_CAN3_SERIAL IMXRT_CCM_CCGR7, 4
|
||||
#define CCM_CCGR_CAN3 IMXRT_CCM_CCGR7, 3
|
||||
#define CCM_CCGR_AXBS IMXRT_CCM_CCGR7, 2
|
||||
#define CCM_CCGR_FLEXSPI2 IMXRT_CCM_CCGR7, 1
|
||||
#define CCM_CCGR_ENET2 IMXRT_CCM_CCGR7, 0
|
||||
|
||||
/* Module Enable Override Register */
|
||||
|
||||
/* Bits 0-4: Reserved */
|
||||
@ -771,7 +781,8 @@
|
||||
#define CCM_CMEOR_MOD_EN_OV_PIT (1 << 6) /* Bit 6: Override clock enable signal from PIT */
|
||||
#define CCM_CMEOR_MOD_EN_OV_USDHC (1 << 7) /* Bit 7: Override clock enable signal from USDHC */
|
||||
#define CCM_CMEOR_MOD_EN_OV_TRNG (1 << 9) /* Bit 9: Override clock enable signal from TRNG */
|
||||
/* Bits 10-27: Reserved */
|
||||
#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI (1 << 10) /* Bit 10: Override clock enable signal from CAN3 */
|
||||
/* Bits 11-27: Reserved */
|
||||
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI (1 << 28) /* Bit 28: Override clock enable signal from CAN2 */
|
||||
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI (1 << 30) /* Bit 30: Override clock enable signal from CAN1 */
|
||||
/* Bit 31: Reserved */
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "imxrt_iomuxc.h"
|
||||
#include "imxrt_gpio.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -619,6 +619,22 @@ void imxrt_clockconfig(void)
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN
|
||||
/* Set FlexCAN clock source to PLL3 80M */
|
||||
reg = getreg32(IMXRT_CCM_CSCMR2);
|
||||
reg &= ~CCM_CSCMR2_CAN_CLK_SEL_MASK;
|
||||
reg |= IMXRT_CAN_CLK_SELECT;
|
||||
putreg32(reg, IMXRT_CCM_CSCMR2);
|
||||
|
||||
/* Set FlexCAN dividet to 1 for 80 MHz */
|
||||
reg = getreg32(IMXRT_CCM_CSCMR2);
|
||||
reg &= ~CCM_CSCMR2_CAN_CLK_PODF_MASK;
|
||||
reg |= CCM_CSCMR2_CAN_CLK_PODF(
|
||||
CCM_PODF_FROM_DIVISOR(IMXRT_CAN_PODF_DIVIDER)
|
||||
);
|
||||
putreg32(reg, IMXRT_CCM_CSCMR2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI
|
||||
/* Set LPSPI clock source to PLL3 PFD0 */
|
||||
|
||||
|
||||
1864
arch/arm/src/imxrt/imxrt_flexcan.c
Normal file
1864
arch/arm/src/imxrt/imxrt_flexcan.c
Normal file
File diff suppressed because it is too large
Load Diff
127
arch/arm/src/imxrt/imxrt_flexcan.h
Normal file
127
arch/arm/src/imxrt/imxrt_flexcan.h
Normal file
@ -0,0 +1,127 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/imxrt/imxrt_flexcan.h
|
||||
*
|
||||
* Copyright (C) 2020 Gregory Nutt. All rights reserved.
|
||||
* Author: Michal Lenc <lencmich@fel.cvut.cz>
|
||||
*
|
||||
* Based on: arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXCAN_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXCAN_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hardware/imxrt_flexcan.h"
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXCAN
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Function: arm_caninitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the enabled CAN device interfaces. If there are more
|
||||
* different network devices in the chip, then board-specific logic will
|
||||
* have to provide this function to determine which, if any, network
|
||||
* devices should be initialized.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Called very early in the initialization sequence.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_NETDEV_LATEINIT)
|
||||
|
||||
void arm_netinitialize(void);
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Function: imxrt_caninitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the CAN controller and driver
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - In the case where there are multiple CAN devices, this value
|
||||
* identifies which CAN device is to be initialized.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#else
|
||||
|
||||
int imxrt_caninitialize(int intf);
|
||||
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_IMXRT_FLEXCAN */
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_FLEXCAN_H */
|
||||
@ -68,6 +68,8 @@
|
||||
#define imxrt_clockoff_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_can3() imxrt_periphclk_configure(CCM_CCGR_CAN3, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_can3_serial() imxrt_periphclk_configure(CCM_CCGR_CAN3_SERIAL, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_OFF)
|
||||
#define imxrt_clockoff_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_OFF)
|
||||
@ -177,6 +179,8 @@
|
||||
#define imxrt_clockrun_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_can3() imxrt_periphclk_configure(CCM_CCGR_CAN3, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_can3_serial() imxrt_periphclk_configure(CCM_CCGR_CAN3_SERIAL, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_RUN)
|
||||
#define imxrt_clockrun_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_RUN)
|
||||
@ -286,6 +290,8 @@
|
||||
#define imxrt_clockall_can1_serial() imxrt_periphclk_configure(CCM_CCGR_CAN1_SERIAL, CCM_CG_ALL)
|
||||
#define imxrt_clockall_can2() imxrt_periphclk_configure(CCM_CCGR_CAN2, CCM_CG_ALL)
|
||||
#define imxrt_clockall_can2_serial() imxrt_periphclk_configure(CCM_CCGR_CAN2_SERIAL, CCM_CG_ALL)
|
||||
#define imxrt_clockall_can3() imxrt_periphclk_configure(CCM_CCGR_CAN3, CCM_CG_ALL)
|
||||
#define imxrt_clockall_can3_serial() imxrt_periphclk_configure(CCM_CCGR_CAN3_SERIAL, CCM_CG_ALL)
|
||||
#define imxrt_clockall_csi() imxrt_periphclk_configure(CCM_CCGR_CSI, CCM_CG_ALL)
|
||||
#define imxrt_clockall_csu() imxrt_periphclk_configure(CCM_CCGR_CSU, CCM_CG_ALL)
|
||||
#define imxrt_clockall_dcdc() imxrt_periphclk_configure(CCM_CCGR_DCDC, CCM_CG_ALL)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user