nucleo-f446re: move clock configuration to board.h for consistency with other boards
This commit is contained in:
raiden00pl
Xiang Xiao
parent
dab6140082
commit
16a0b8ab94
@ -46,12 +46,175 @@
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#endif
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#include <stm32.h>
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#include <arch/board/nucleo-f446re.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3).
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* However, as shipped, the X2 and X3 crystals are not populated.
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* Therefore the Nucleo-FF446RE will need to run off the 16MHz HSI clock.
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 180000000 Determined by PLL config
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* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 216 (STM32_PLLCFG_PLLN)
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* PLLP : 4 (STM32_PLLCFG_PLLP)
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* PLLQ : 9 (STM32_PLLCFG_PPQ)
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* Flash Latency(WS) : 4
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - not installed
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* LSE - not installed
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*/
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_BOARD_USEHSI 1
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4
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* so we can select a divider of 4 and a multiplier of 45
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* However multiplier must be between 50 and 432
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* so we double again to choose a multiplier of 90, and a divider of 8
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* VCO output frequency must be in range 100...432 MHz
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*
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* VCO input frequency = PLL input clock frequency / PLLM,
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* 2 <= PLLM <= 63
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* VCO output frequency = VCO input frequency × PLLN,
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* 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz)
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* PLL output clock frequency = VCO frequency / PLLP,
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* PLLP = 2, 4, 6, or 8
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* USB OTG FS clock frequency = VCO frequency / PLLQ,
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* 2 <= PLLQ <= 15
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*
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* PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4
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*
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* We will configure like this
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*
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* PLL source is HSI
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* PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN
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* = (16,000,000 / 4) * 90
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* = 360 MHz
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* SYSCLK = PLL_VCO / PLLP
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* = 360,000,000 / 2 = 180,000,000
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* USB OTG FS and SDIO Clock
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* = TODO 7.5 is not possible
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*
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* REVISIT: Trimming of the HSI is not yet supported.
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15)
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#define STM32_SYSCLK_FREQUENCY 180000000ul
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/* AHB clock (HCLK) is SYSCLK (104MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (104MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY)
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#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY)
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
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*
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* REVISIT
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*/
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*
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* REVISIT
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*
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* REVISIT
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channel/Stream Selections ********************************************/
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/* Stream selections are arbitrary for now but might become important in the
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@ -1,239 +0,0 @@
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/****************************************************************************
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* boards/arm/stm32/nucleo-f446re/include/nucleo-f446re.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_NUCLEO_F446RE_H
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#define __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_NUCLEO_F446RE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *******************************************************************/
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/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3). However, as
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* shipped, the X2 and X3 crystals are not populated. Therefore the
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* Nucleo-FF446RE will need to run off the 16MHz HSI clock.
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 180000000 Determined by PLL config
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* HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 216 (STM32_PLLCFG_PLLN)
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* PLLP : 4 (STM32_PLLCFG_PLLP)
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* PLLQ : 9 (STM32_PLLCFG_PPQ)
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* Flash Latency(WS) : 4
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - not installed
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* LSE - not installed
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*/
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_BOARD_USEHSI 1
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4
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* so we can select a divider of 4 and a multiplier of 45
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* However multiplier must be between 50 and 432
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* so we double again to choose a multiplier of 90, and a divider of 8
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* VCO output frequency must be in range 100...432 MHz
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*
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* VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63
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* VCO output frequency = VCO input frequency × PLLN, 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz)
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* PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8
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* USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15
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*
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* PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4
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*
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* We will configure like this
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*
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* PLL source is HSI
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* PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN
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* = (16,000,000 / 4) * 90
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* = 360 MHz
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* SYSCLK = PLL_VCO / PLLP
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* = 360,000,000 / 2 = 180,000,000
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* USB OTG FS and SDIO Clock
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* = TODO 7.5 is not possible
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*
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* REVISIT: Trimming of the HSI is not yet supported.
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15)
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#define STM32_SYSCLK_FREQUENCY 180000000ul
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/* AHB clock (HCLK) is SYSCLK (104MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (104MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 (REVISIT) */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*
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* REVISIT
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*/
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#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
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#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
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*
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* REVISIT
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*/
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*
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* REVISIT
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
|
||||
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
|
||||
*
|
||||
* REVISIT
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_NUCLEO_F446RE_H */
|
||||
Loading…
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Reference in New Issue
Block a user