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Merged in david_s5/arch/upstream_446 (pull request #7)

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Upstream_446
This commit is contained in:
Gregory Nutt 2015-08-21 18:11:05 -06:00
commit 16c5be9767
6 changed files with 2108 additions and 6 deletions
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1022
arch/arm/src/stm32/chip/stm32f44xxx_otgfs.h Normal file
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File diff suppressed because it is too large Load Diff

10
arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
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@ -536,10 +536,13 @@
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S N multiplication factor for VCO */
#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SN(n) ((n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
#define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIF-Rx clock */
#define RCC_PLLI2SCFGR_PLLI2SP_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP(n) ((n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
# define RCC_PLLI2SCFGR_PLLI2SP_2 RCC_PLLI2SCFGR_PLLI2SP(0) /* 00: PLLI2S = 2 */
# define RCC_PLLI2SCFGR_PLLI2SP_4 RCC_PLLI2SCFGR_PLLI2SP(1) /* 01: PLLI2S = 4 */
# define RCC_PLLI2SCFGR_PLLI2SP_6 RCC_PLLI2SCFGR_PLLI2SP(2) /* 10: PLLI2S = 6 */
# define RCC_PLLI2SCFGR_PLLI2SP_8 RCC_PLLI2SCFGR_PLLI2SP(3) /* 11: PLLI2S = 8 */
#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAI1 clock*/
#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
@ -563,7 +566,10 @@
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48 MHz clock */
#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
# define RCC_PLLSAICFGR_PLLSAI_2 RCC_PLLSAICFGR_PLLSAIP(0) /* 00: PLLSAI = 2 */
# define RCC_PLLSAICFGR_PLLSAI_4 RCC_PLLSAICFGR_PLLSAIP(1) /* 01: PLLSAI = 4 */
# define RCC_PLLSAICFGR_PLLSAI_6 RCC_PLLSAICFGR_PLLSAIP(2) /* 10: PLLSAI = 6 */
# define RCC_PLLSAICFGR_PLLSAI_8 RCC_PLLSAICFGR_PLLSAIP(3) /* 11: PLLSAI = 8 */
#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */
#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)

1014
arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h Normal file
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File diff suppressed because it is too large Load Diff

7
arch/arm/src/stm32/stm32_otgfs.h
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@ -45,7 +45,12 @@
#include <stdint.h>
#include "stm32.h"
#include "chip/stm32_otgfs.h"
#if defined(CONFIG_STM32_STM32F446)
# include "chip/stm32f44xxx_otgfs.h"
#else
# include "chip/stm32fxxxxx_otgfs.h"
#endif
#if defined(CONFIG_STM32_OTGFS)

41
arch/arm/src/stm32/stm32_otgfsdev.c
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@ -5169,16 +5169,51 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
/* Deactivate the power down */
#if defined(NOT_CONFIG_STM32_STM32F446)
/* In the case of the STM32F446 the meaning
* of the bit has changed to VBUS Detection Enable
* when set
*/
regval = OTGFS_GCCFG_PWRDWN;
# ifdef CONFIG_USBDEV_VBUSSENSING
regval |= OTGFS_GCCFG_VBDEN;
# endif
#else
/* In the case of the the all others the meaning
* of the bit is No VBUS Sense when Set
*/
regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | OTGFS_GCCFG_VBUSBSEN);
#ifndef CONFIG_USBDEV_VBUSSENSING
# ifndef CONFIG_USBDEV_VBUSSENSING
regval |= OTGFS_GCCFG_NOVBUSSENS;
#endif
#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT
# endif
# ifdef CONFIG_STM32_OTGFS_SOFOUTPUT
regval |= OTGFS_GCCFG_SOFOUTEN;
# endif
#endif
stm32_putreg(regval, STM32_OTGFS_GCCFG);
up_mdelay(20);
/*
* For the new otg controller in the F446 when
* VBUS sensing is not used we need to force the
* B session valid
*
*/
#if defined(NOT_CONFIG_STM32_STM32F446)
# ifndef CONFIG_USBDEV_VBUSSENSING
regval = stm32_getreg(STM32_OTGFS_GOTGCTL);
regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL);
stm32_putreg(regval, STM32_OTGFS_GOTGCTL);
# endif
#endif
/* Force Device Mode */
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);

20
arch/arm/src/stm32/stm32f44xxx_rcc.c
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@ -698,6 +698,10 @@ static void stm32_stdclockconfig(void)
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK |
RCC_PLLSAICFGR_PLLSAIN_MASK |
RCC_PLLSAICFGR_PLLSAIP_MASK |
RCC_PLLSAICFGR_PLLSAIQ_MASK);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIM
| STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIP
@ -705,6 +709,13 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_PLLSAICFGR);
regval = getreg32(STM32_RCC_DCKCFGR);
regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK |
RCC_DCKCFGR_PLLSAIDIVQ_MASK |
RCC_DCKCFGR_SAI1SRC_MASK |
RCC_DCKCFGR_SAI2SRC_MASK |
RCC_DCKCFGR_I2S1SRC_MASK |
RCC_DCKCFGR_I2S2SRC_MASK);
regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ
| STM32_RCC_DCKCFGR_PLLSAIDIVQ
| STM32_RCC_DCKCFGR_SAI1SRC
@ -733,6 +744,10 @@ static void stm32_stdclockconfig(void)
/* Configure PLLI2S */
regval = getreg32(STM32_RCC_PLLI2SCFGR);
regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK |
RCC_PLLI2SCFGR_PLLI2SN_MASK |
RCC_PLLI2SCFGR_PLLI2SP_MASK |
RCC_PLLI2SCFGR_PLLI2SQ_MASK);
regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM
| STM32_RCC_PLLI2SCFGR_PLLI2SN
| STM32_RCC_PLLI2SCFGR_PLLI2SP
@ -741,6 +756,11 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_PLLI2SCFGR);
regval = getreg32(STM32_RCC_DCKCFGR2);
regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK |
RCC_DCKCFGR2_CECSEL_MASK |
RCC_DCKCFGR2_CK48MSEL_MASK |
RCC_DCKCFGR2_SDIOCSEL_MASK |
RCC_DCKCFGR2_SPDIFRXEL_MASK);
regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL
| STM32_RCC_DCKCFGR2_CECSEL
| STM32_RCC_DCKCFGR2_CK48MSEL