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esp32s2: add simple boot support

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The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato 2024-05-23 10:36:29 +02:00 committed by Alan Carvalho de Assis
parent b5f8498142
commit 16f8966fa9
42 changed files with 1064 additions and 6489 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/platforms/risc-v/esp32c3-legacy/index.rst
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@ -90,7 +90,7 @@ Building and flashing
First make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32 image and to flash the image into the board.
It can be installed with: ``pip install esptool``.
It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c3-devkit:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is

2
Documentation/platforms/risc-v/esp32c3/index.rst
View File

@ -94,7 +94,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-C3 image and to flash the image into the board.
It can be installed with: ``pip install esptool``.
It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c3-generic:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is

2
Documentation/platforms/risc-v/esp32c6/index.rst
View File

@ -84,7 +84,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-C6 image and to flash the image into the board.
It can be installed with: ``pip install esptool``.
It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32c6-devkitc:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is

2
Documentation/platforms/risc-v/esp32h2/index.rst
View File

@ -84,7 +84,7 @@ Building and flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert
the ELF to a compatible ESP32-H2 image and to flash the image into the board.
It can be installed with: ``pip install esptool``.
It can be installed with: ``pip install esptool==4.8.dev4``.
Configure the NuttX project: ``./tools/configure.sh esp32h2-devkit:nsh``
Run ``make`` to build the project. Note that the conversion mentioned above is

2
Documentation/platforms/xtensa/esp32/index.rst
View File

@ -505,7 +505,7 @@ Prerequisites
First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary
images) and ``esptool`` (the ESP32 toolkit)::
$ pip install imgtool esptool
$ pip install imgtool esptool==4.8.dev4
We also need to make sure that the python modules are added to ``PATH``::

2
Documentation/platforms/xtensa/esp32s2/index.rst
View File

@ -359,7 +359,7 @@ Prerequisites
First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary
images) and ``esptool`` (the ESP32-S2 toolkit)::
$ pip install imgtool esptool
$ pip install imgtool esptool==4.8.dev4
We also need to make sure that the python modules are added to ``PATH``::

2
Documentation/platforms/xtensa/esp32s3/index.rst
View File

@ -129,7 +129,7 @@ Building and Flashing
First, make sure that ``esptool.py`` is installed. This tool is used to convert the ELF to a
compatible ESP32-S3 image and to flash the image into the board.
It can be installed with: ``pip install esptool``.
It can be installed with: ``pip install esptool==4.8.dev4``.
It's a two-step process where the first converts the ELF file into an ESP32-S3 compatible binary
and the second flashes it to the board. These steps are included in the build system and it is

28
arch/xtensa/src/esp32s2/Bootloader.mk
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@ -20,7 +20,7 @@
.PHONY: bootloader clean_bootloader
ifeq ($(CONFIG_ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE),y)
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),)
TOOLSDIR = $(TOPDIR)/tools/espressif
CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip
@ -114,8 +114,13 @@ else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y)
$(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S2_PARTITION_TABLE_OFFSET)) \
} >> $(BOOTLOADER_CONFIG)
endif
endif
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
bootloader:
$(Q) echo "Using direct bootloader to boot NuttX."
else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32s2.bin
BOOTLOADER_SIGNED_BIN = $(TOPDIR)/mcuboot-esp32s2.signed.bin
@ -181,22 +186,3 @@ clean_bootloader:
$(call DELFILE,$(TOPDIR)/partition-table-esp32s2.bin)
endif
else ifeq ($(CONFIG_ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT),y)
BOOTLOADER_VERSION = latest
BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y)
bootloader:
$(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s2.bin,$(TOPDIR)/bootloader-esp32s2.bin)
$(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32s2.bin,$(TOPDIR)/partition-table-esp32s2.bin)
clean_bootloader:
$(call DELFILE,$(TOPDIR)/bootloader-esp32s2.bin)
$(call DELFILE,$(TOPDIR)/partition-table-esp32s2.bin)
endif
endif

29
arch/xtensa/src/esp32s2/Kconfig
View File

@ -1222,9 +1222,14 @@ config ESP32S2_HAVE_OTA_PARTITION
menu "Bootloader and Image Configuration"
config ESP32S2_APP_FORMAT_LEGACY
config ESPRESSIF_SIMPLE_BOOT
bool
default y if !ESP32S2_APP_FORMAT_MCUBOOT
depends on !ESP32S2_APP_FORMAT_MCUBOOT
depends on !ESP32S2_APP_FORMAT_LEGACY
default y
config ESP32S2_APP_FORMAT_LEGACY
bool "Enable Legacy boot format"
depends on !ESP32S2_APP_FORMAT_MCUBOOT
---help---
This is the legacy application image format, as supported by the ESP-IDF
@ -1233,28 +1238,11 @@ config ESP32S2_APP_FORMAT_LEGACY
config ESP32S2_APP_FORMAT_MCUBOOT
bool "Enable MCUboot-bootable format"
depends on !MCUBOOT_BOOTLOADER
default n
select ESP32S2_HAVE_OTA_PARTITION
select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
config ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT
bool
default y if !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
depends on !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
---help---
The build system will download the prebuilt binaries from
https://github.com/espressif/esp-nuttx-bootloader according to the chosen
Application Image Format (ESP32S2_APP_FORMAT_LEGACY or ESP32S2_APP_FORMAT_MCUBOOT)
config ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
bool "Build binaries from source"
---help---
The build system will build all the required binaries from source. It will clone
the https://github.com/espressif/esp-nuttx-bootloader repository and build a
custom bootloader according to the chosen Application Image Format
(ESP32S2_APP_FORMAT_LEGACY or ESP32S2_APP_FORMAT_MCUBOOT) and partition information.
choice
prompt "Target slot for image flashing"
default ESP32S2_ESPTOOL_TARGET_PRIMARY
@ -1299,7 +1287,6 @@ config ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET
bool "Customize partition table offset"
default n
depends on ESP32S2_APP_FORMAT_LEGACY
select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE
---help---
Enable to select the offset of the partition table in the flash.

6
arch/xtensa/src/esp32s2/Make.defs
View File

@ -143,6 +143,10 @@ ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32s2_rtc_lowerhalf.c
endif
ifeq ($(ESP32S2_APP_FORMAT_LEGACY), )
CHIP_CSRCS += loader.c
endif
#############################################################################
# Espressif HAL for 3rd Party Platforms
#############################################################################
@ -151,7 +155,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd
ESP_HAL_3RDPARTY_VERSION = 7247aeb8749d8c6e29f951fa499100f593042408
endif
ifndef ESP_HAL_3RDPARTY_URL

2
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
View File

@ -28,7 +28,7 @@
#include <sys/param.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_rtccntl.h"

2
arch/xtensa/src/esp32s2/esp32s2_rng.c
View File

@ -41,7 +41,7 @@
#include <arch/xtensa/core_macros.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/wdev_reg.h"
#include "esp32s2_clockconfig.h"

2
arch/xtensa/src/esp32s2/esp32s2_rt_timer.c
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@ -40,7 +40,7 @@
#include <nuttx/semaphore.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_system.h"

4
arch/xtensa/src/esp32s2/esp32s2_rtc.c
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@ -45,13 +45,13 @@
#include "hardware/esp32s2_tim.h"
#include "hardware/regi2c_ctrl.h"
#include "hardware/esp32s2_spi_mem_reg.h"
#include "hardware/esp32s2_extmem.h"
#include "hardware/esp32s2_syscon.h"
#include "hardware/regi2c_bbpll.h"
#include "hardware/regi2c_lp_bias.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "soc/extmem_reg.h"
#include "esp32s2_rtc.h"

2
arch/xtensa/src/esp32s2/esp32s2_spiflash.c
View File

@ -41,7 +41,7 @@
#include <nuttx/mtd/mtd.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s2_spi_mem_reg.h"
#include "rom/esp32s2_spiflash.h"
#include "rom/esp32s2_opi_flash.h"

2
arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c
View File

@ -40,7 +40,7 @@
#include "hardware/esp32s2_soc.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s2_spiflash.h"
#include "rom/esp32s2_spiflash.h"

6
arch/xtensa/src/esp32s2/esp32s2_spiram.c
View File

@ -35,14 +35,16 @@
#include <nuttx/spinlock.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "esp32s2_psram.h"
#include "esp32s2_spiram.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_cache_memory.h"
#include "hardware/esp32s2_extmem.h"
#include "hardware/esp32s2_iomux.h"
#include "soc/extmem_reg.h"
#include "soc/ext_mem_defs.h"
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/

189
arch/xtensa/src/esp32s2/esp32s2_start.c
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@ -31,10 +31,9 @@
#include <nuttx/irq.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_attr.h"
#include "hardware/esp32s2_cache_memory.h"
#include "hardware/esp32s2_extmem.h"
#include "rom/esp32s2_libc_stubs.h"
#include "esp32s2_clockconfig.h"
#include "esp32s2_region.h"
@ -43,6 +42,25 @@
#include "esp32s2_lowputc.h"
#include "esp32s2_wdt.h"
#include "esp32s2_rtc.h"
#include "loader.h"
#include "soc/extmem_reg.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_types.h"
#include "hal/cache_types.h"
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
#include "rom/spi_flash.h"
# include "bootloader_flash_priv.h"
# include "esp_rom_efuse.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "bootloader_random.h"
# include "esp_rom_uart.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
/****************************************************************************
* Pre-processor Definitions
@ -54,28 +72,26 @@
# define showprogress(c)
#endif
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
# ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S2_OTA_PRIMARY_SLOT_OFFSET
# else
/* Force offset to the beginning of the whole image */
# define PRIMARY_SLOT_OFFSET 0x0000
# endif
# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
/* Cache MMU block size */
#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
/* Cache MMU address mask (MMU tables ignore bits which are zero) */
#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1))
#endif
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern uint8_t _image_irom_vma[];
extern uint8_t _image_irom_lma[];
extern uint8_t _image_irom_size[];
@ -120,11 +136,9 @@ typedef enum
* ROM Function Prototypes
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr,
uint32_t paddr, uint32_t psize, uint32_t num,
uint32_t fixed);
#endif
extern uint32_t cache_suspend_icache(void);
@ -146,7 +160,8 @@ extern void cache_enable_dcache(uint32_t autoload);
* Private Function Prototypes
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
noreturn_function void __start(void);
#endif
@ -154,7 +169,8 @@ noreturn_function void __start(void);
* Private Data
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
HDR_ATTR static void (*_entry_point)(void) = __start;
#endif
@ -296,6 +312,7 @@ static void IRAM_ATTR configure_cpu_caches(void)
static void noreturn_function IRAM_ATTR __esp32s2_start(void)
{
#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT
uint32_t sp;
/* Make sure that normal interrupts are disabled. This is really only an
@ -315,9 +332,11 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
#ifndef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
/* Make page 0 access raise an exception */
esp32s2_region_protection();
#endif
/* Move CPU0 exception vectors to IRAM */
@ -331,6 +350,7 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
{
*dest++ = 0;
}
#endif
/* The 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to
@ -394,111 +414,6 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void)
for (; ; ); /* Should not return */
}
/****************************************************************************
* Name: calc_mmu_pages
*
* Description:
* Calculate the number of cache pages to map.
*
* Input Parameters:
* size - Size of data to map
* vaddr - Virtual address where data will be mapped
*
* Returned Value:
* Number of cache MMU pages required to do the mapping.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr)
{
return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) /
MMU_BLOCK_SIZE;
}
#endif
/****************************************************************************
* Name: map_rom_segments
*
* Description:
* Configure the MMU and Cache peripherals for accessing ROM code and data.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
static int map_rom_segments(void)
{
uint32_t rc = 0;
uint32_t regval;
uint32_t drom_lma_aligned;
uint32_t drom_vma_aligned;
uint32_t drom_page_count;
uint32_t irom_lma_aligned;
uint32_t irom_vma_aligned;
uint32_t irom_page_count;
size_t partition_offset = PRIMARY_SLOT_OFFSET;
uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma;
uint32_t app_irom_size = (uint32_t)_image_irom_size;
uint32_t app_irom_vma = (uint32_t)_image_irom_vma;
uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma;
uint32_t app_drom_size = (uint32_t)_image_drom_size;
uint32_t app_drom_vma = (uint32_t)_image_drom_vma;
uint32_t autoload = cache_suspend_icache();
cache_invalidate_icache_all();
/* Clear the MMU entries that are already set up, so the new app only has
* the mappings it creates.
*/
for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++)
{
FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL;
}
drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
rc = cache_ibus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned,
drom_lma_aligned, 64, (int)drom_page_count, 0);
irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
if (app_irom_lma + app_irom_size > IRAM1_ADDRESS_LOW)
{
rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64,
64, 1);
rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64,
64, 1);
regval = getreg32(EXTMEM_PRO_ICACHE_CTRL1_REG);
regval &= ~(EXTMEM_PRO_ICACHE_MASK_IRAM1);
putreg32(regval, EXTMEM_PRO_ICACHE_CTRL1_REG);
}
rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned,
irom_lma_aligned, 64, (int)irom_page_count, 0);
regval = getreg32(EXTMEM_PRO_ICACHE_CTRL1_REG);
regval &= ~(EXTMEM_PRO_ICACHE_MASK_IRAM0 |
EXTMEM_PRO_ICACHE_MASK_DROM0);
putreg32(regval, EXTMEM_PRO_ICACHE_CTRL1_REG);
cache_resume_icache(autoload);
return (int)rc;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -512,10 +427,32 @@ static int map_rom_segments(void)
*
****************************************************************************/
void IRAM_ATTR __start(void)
noreturn_function void IRAM_ATTR __start(void)
{
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
if (map_rom_segments() != 0)
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined(CONFIG_ESPRESSIF_SIMPLE_BOOT)
size_t partition_offset = PRIMARY_SLOT_OFFSET;
uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma;
uint32_t app_irom_size = (uint32_t)_image_irom_size;
uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma;
uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma;
uint32_t app_drom_size = (uint32_t)_image_drom_size;
uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma;
# ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
if (bootloader_init() != 0)
{
ets_printf("Hardware init failed, aborting\n");
while (true);
}
# endif
if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size,
app_irom_start, app_irom_vaddr, app_irom_size) != 0)
{
ets_printf("Failed to setup XIP, aborting\n");
while (true);

4
arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h
View File

@ -1244,7 +1244,7 @@ static inline void touch_lh_timeout_disable(void)
static inline void touch_lh_timeout_set_threshold(uint32_t threshold)
{
return REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG,
REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG,
RTC_CNTL_TOUCH_TIMEOUT_NUM,
threshold);
}
@ -2195,7 +2195,7 @@ static inline enum touch_pad_e touch_lh_sleep_get_channel_num(void)
static inline void touch_lh_sleep_set_threshold(uint32_t touch_thres)
{
return REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG,
REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG,
RTC_CNTL_TOUCH_SLP_TH,
touch_thres);
}

51
arch/xtensa/src/esp32s2/hal.mk
View File

@ -21,10 +21,12 @@
# Include header paths
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private
@ -49,6 +51,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
@ -69,6 +74,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
@ -78,6 +84,10 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
@ -94,4 +104,41 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
LDFLAGS += --wrap=bootloader_print_banner
endif
CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1

110
arch/xtensa/src/esp32s2/hardware/esp32s2_cache_memory.h
View File

@ -30,100 +30,6 @@
* Pre-processor Definitions
****************************************************************************/
/* IRAM0 is connected with Cache IBUS0 */
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH 0x40400000
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
/* IRAM1 is connected with Cache IBUS1 */
#define IRAM1_ADDRESS_LOW 0x40400000
#define IRAM1_ADDRESS_HIGH 0x40800000
/* DROM0 is connected with Cache IBUS2 */
#define DROM0_ADDRESS_LOW 0x3f000000
#define DROM0_ADDRESS_HIGH 0x3f400000
/* DRAM0 is connected with Cache DBUS0 */
#define DRAM0_ADDRESS_LOW 0x3fc00000
#define DRAM0_ADDRESS_HIGH 0x40000000
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
/* DRAM1 is connected with Cache DBUS1 */
#define DRAM1_ADDRESS_LOW 0x3f800000
#define DRAM1_ADDRESS_HIGH 0x3fc00000
/* DPORT is connected with Cache DBUS2 */
#define DPORT_ADDRESS_LOW 0x3f400000
#define DPORT_ADDRESS_HIGH 0x3f800000
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
bus_name##_ADDRESS_LOW)
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
&& (vaddr) < \
bus_name##_ADDRESS_HIGH)
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
#define PRO_CACHE_IBUS0 0
#define PRO_CACHE_IBUS0_MMU_START 0
#define PRO_CACHE_IBUS0_MMU_END 0x100
#define PRO_CACHE_IBUS1 1
#define PRO_CACHE_IBUS1_MMU_START 0x100
#define PRO_CACHE_IBUS1_MMU_END 0x200
#define PRO_CACHE_IBUS2 2
#define PRO_CACHE_IBUS2_MMU_START 0x200
#define PRO_CACHE_IBUS2_MMU_END 0x300
#define PRO_CACHE_DBUS0 3
#define PRO_CACHE_DBUS0_MMU_START 0x300
#define PRO_CACHE_DBUS0_MMU_END 0x400
#define PRO_CACHE_DBUS1 4
#define PRO_CACHE_DBUS1_MMU_START 0x400
#define PRO_CACHE_DBUS1_MMU_END 0x500
#define PRO_CACHE_DBUS2 5
#define PRO_CACHE_DBUS2_MMU_START 0x500
#define PRO_CACHE_DBUS2_MMU_END 0x600
#define ICACHE_MMU_SIZE 0x300
#define DCACHE_MMU_SIZE 0x300
#define MMU_BUS_START(i) ((i) * 0x100)
#define MMU_BUS_SIZE 0x100
#define MMU_INVALID BIT(14)
#define MMU_ACCESS_FLASH BIT(15)
#define MMU_ACCESS_SPIRAM BIT(16)
#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
@ -131,23 +37,9 @@
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
#define MMU_ADDRESS_MASK 0x3fff
#define MMU_PAGE_SIZE 0x10000
#define INVALID_PHY_PAGE 0xffff
#define BUS_ADDR_SIZE 0x400000
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
#define BUS_NUM_MASK 0x3
#define CACHE_MEMORY_BANK_SIZE 8192
#define CACHE_MEMORY_BANK_NUM 4
#define CACHE_MEMORY_BANK_NUM_MASK 0x3
#define CACHE_MEMORY_LAYOUT_SHIFT 4
#define CACHE_MEMORY_LAYOUT_SHIFT0 0
#define CACHE_MEMORY_LAYOUT_SHIFT1 4
#define CACHE_MEMORY_LAYOUT_SHIFT2 8
#define CACHE_MEMORY_LAYOUT_SHIFT3 12
#define CACHE_MEMORY_LAYOUT_MASK 0xf
#define CACHE_MEMORY_BANK0_ADDR 0x3ffb0000
#define CACHE_MEMORY_BANK1_ADDR 0x3ffb2000
#define CACHE_MEMORY_BANK2_ADDR 0x3ffb4000
#define CACHE_MEMORY_BANK3_ADDR 0x3ffb6000
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_CACHE_MEMORY_H */

2757
arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h
View File

File diff suppressed because it is too large Load Diff

314
arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
View File

@ -29,161 +29,15 @@
#include <stdbool.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include <nuttx/bits.h>
#include "soc/soc.h"
#include "esp_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Bits */
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
#define PRO_CPU_NUM (0)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) /* Largest span of contiguous memory (DRAM or IRAM) in the address space */
/* Registers Operation */
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
/* Set bits of register controlled by mask */
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S)))
/* Set field value from a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
/* Get field value from a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
/* Set field value to a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
/* Set field value to a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
/* Generate a value from a field value,
* used when _f is not left shifted by _f##_S
*/
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
/* Generate a value from a field value,
* used when _f is left shifted by _f##_S
*/
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
/* Read value from register */
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
/* Write value to register */
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
/* Clear bits of register controlled by mask */
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
/* Set bits of register controlled by mask */
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
/* Get bits of register controlled by mask */
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
/* Get bits of register controlled by highest bit and lowest bit */
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
/* Set bits of register controlled by mask and shift */
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
/* Get field of register */
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S))
@ -192,118 +46,11 @@
#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
/* Periheral Clock */
#define APB_CLK_FREQ_ROM 40 * 1000000
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */
#define REF_CLK_FREQ (1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define MWDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */
#define DR_REG_SYSTEM_BASE 0x3f4c0000
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x61800000
#define DR_REG_MMU_TABLE 0x61801000
#define DR_REG_ITAG_TABLE 0x61802000
#define DR_REG_DTAG_TABLE 0x61803000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000
#define DR_REG_GPIO_BASE 0x3f404000
#define DR_REG_GPIO_SD_BASE 0x3f404f00
#define DR_REG_FE2_BASE 0x3f405000
#define DR_REG_FE_BASE 0x3f406000
#define DR_REG_FRC_TIMER_BASE 0x3f407000
#define DR_REG_RTCCNTL_BASE 0x3f408000
#define DR_REG_RTCIO_BASE 0x3f408400
#define DR_REG_SENS_BASE 0x3f408800
#define DR_REG_RTC_I2C_BASE 0x3f408C00
#define DR_REG_IO_MUX_BASE 0x3f409000
#define DR_REG_HINF_BASE 0x3f40B000
#define DR_REG_I2S_BASE 0x3f40F000
#define DR_REG_UART1_BASE 0x3f410000
#define DR_REG_I2C_EXT_BASE 0x3f413000
#define DR_REG_UHCI0_BASE 0x3f414000
#define DR_REG_SLCHOST_BASE 0x3f415000
#define DR_REG_RMT_BASE 0x3f416000
#define DR_REG_PCNT_BASE 0x3f417000
#define DR_REG_SLC_BASE 0x3f418000
#define DR_REG_LEDC_BASE 0x3f419000
#define DR_REG_CP_BASE 0x3f4c3000
#define DR_REG_EFUSE_BASE 0x3f41A000
#define DR_REG_NRX_BASE 0x3f41CC00
#define DR_REG_BB_BASE 0x3f41D000
#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
#define DR_REG_TIMERGROUP1_BASE 0x3f420000
#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
#define DR_REG_SYSTIMER_BASE 0x3f423000
#define DR_REG_SPI2_BASE 0x3f424000
#define DR_REG_SPI3_BASE 0x3f425000
#define DR_REG_SYSCON_BASE 0x3f426000
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000
#define DR_REG_APB_SARADC_BASE 0x3f440000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_USB_BASE 0x60080000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000)))
/* Registers Operation */
#define DR_REG_TWAI_BASE 0x6002B000
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
/* Overall memory map */
#define SOC_DROM_LOW 0x3f000000 /* drom0 low address for icache */
#define SOC_DROM_HIGH 0x3ff80000 /* dram0 high address for dcache */
#define SOC_IROM_LOW 0x40080000
#define SOC_IROM_HIGH 0x40800000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40020000
#define SOC_IRAM_LOW 0x40020000
#define SOC_IRAM_HIGH 0x40070000
#define SOC_DRAM_LOW 0x3ffb0000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_RTC_IRAM_LOW 0x40070000
#define SOC_RTC_IRAM_HIGH 0x40072000
#define SOC_RTC_DRAM_LOW 0x3ff9e000
#define SOC_RTC_DRAM_HIGH 0x3ffa0000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3f500000
#define SOC_EXTRAM_DATA_HIGH 0x3ff80000
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
/* Virtual address 0 */
#define VADDR0_START_ADDR SOC_DROM_LOW
@ -317,59 +64,6 @@
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
/* Interrupt cpu using table */
/****************************************************************************
*Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host VHCI Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 4 1 extern level WBB
* 5 1 extern level BT Controller
* 6 1 timer RTOS Tick RTOS Tick
* 7 1 software Reserved Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer Internal Timer
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level Reserved Reserved
* 26 5 extern level Reserved Reserved
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level Reserved Reserved
****************************************************************************/
/* CPU0 Interrupt number reserved, not touch this. */
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */
/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
/* Other interrupt numbers should be managed by the user */
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)

3098
arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h
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File diff suppressed because it is too large Load Diff

300
arch/xtensa/src/esp32s2/loader.c Normal file
View File

@ -0,0 +1,300 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/loader.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include "xtensa.h"
#include "esp_attr.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_types.h"
#include "hal/cache_types.h"
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
#include "soc/extmem_reg.h"
#include "rom/cache.h"
#include "spi_flash_mmap.h"
# include "bootloader_flash_priv.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "esp_rom_uart.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
# define HDR_ATTR __attribute__((section(".entry_addr"))) \
__attribute__((used))
# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */
# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG
# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \
EXTMEM_ICACHE_SHUT_DBUS_M)
# define CHECKSUM_ALIGN 16
# define IS_PADD(addr) (addr == 0)
# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
# ifdef SOC_RTC_FAST_MEM_SUPPORTED
# define IS_RTC_FAST_IRAM(addr) \
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH)
# define IS_RTC_FAST_DRAM(addr) \
(addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
# else
# define IS_RTC_FAST_IRAM(addr) 0
# define IS_RTC_FAST_DRAM(addr) 0
# endif
# ifdef SOC_RTC_SLOW_MEM_SUPPORTED
# define IS_RTC_SLOW_DRAM(addr) \
(addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH)
# else
# define IS_RTC_SLOW_DRAM(addr) 0
# endif
# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
&& !IS_IRAM(addr) && !IS_DRAM(addr) \
&& !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \
&& !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr))
# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr)
#endif
/****************************************************************************
* Private Types
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern uint8_t _image_irom_vma[];
extern uint8_t _image_irom_lma[];
extern uint8_t _image_irom_size[];
extern uint8_t _image_drom_vma[];
extern uint8_t _image_drom_lma[];
extern uint8_t _image_drom_size[];
#endif
/****************************************************************************
* ROM Function Prototypes
****************************************************************************/
#if defined(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: map_rom_segments
*
* Description:
* Configure the MMU and Cache peripherals for accessing ROM code and data.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
uint32_t app_drom_size, uint32_t app_irom_start,
uint32_t app_irom_vaddr, uint32_t app_irom_size)
{
uint32_t rc = 0;
uint32_t actual_mapped_len = 0;
uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
esp_image_header_t image_header; /* Header for entire image */
esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
bool padding_checksum = false;
unsigned int segments = 0;
unsigned int ram_segments = 0;
unsigned int rom_segments = 0;
size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH;
/* Read image header */
if (bootloader_flash_read(offset, &image_header,
sizeof(esp_image_header_t),
true) != ESP_OK)
{
ets_printf("Failed to load image header!\n");
abort();
}
offset += sizeof(esp_image_header_t);
/* Iterate for segment information parsing */
while (segments++ < 16 && rom_segments < 2)
{
/* Read segment header */
if (bootloader_flash_read(offset, &segment_hdr,
sizeof(esp_image_segment_header_t),
true) != ESP_OK)
{
ets_printf("failed to read segment header at %x\n", offset);
abort();
}
if (IS_NONE(segment_hdr.load_addr))
{
break;
}
if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr))
{
/* RTC segment is loaded by ROM bootloader */
ram_segments++;
}
ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n",
IS_NONE(segment_hdr.load_addr) ? "???" :
IS_RTC_FAST_IRAM(segment_hdr.load_addr) ||
IS_RTC_FAST_DRAM(segment_hdr.load_addr) ||
IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" :
IS_MMAP(segment_hdr.load_addr) ?
IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" :
IS_PADD(segment_hdr.load_addr) ? "padd" :
IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram",
offset + sizeof(esp_image_segment_header_t),
segment_hdr.load_addr, segment_hdr.data_len,
segment_hdr.data_len);
/* Fix drom and irom produced be the linker, as this
* is later invalidated by the elf2image command.
*/
if (IS_DROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_drom_vma)
{
app_drom_start = offset + sizeof(esp_image_segment_header_t);
app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_IROM(segment_hdr.load_addr) &&
segment_hdr.load_addr == (uint32_t)_image_irom_vma)
{
app_irom_start = offset + sizeof(esp_image_segment_header_t);
app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
rom_segments++;
}
if (IS_SRAM(segment_hdr.load_addr))
{
ram_segments++;
}
offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
if (ram_segments == image_header.segment_count && !padding_checksum)
{
offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1;
padding_checksum = true;
}
}
if (segments == 0 || segments == 16)
{
ets_printf("Error parsing segments\n");
}
ets_printf("total segments stored %d\n", segments - 1);
#endif
#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
ets_printf("IROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
app_irom_start_aligned, app_irom_vaddr_aligned,
app_irom_size, app_irom_size);
ets_printf("DROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
app_drom_start_aligned, app_drom_vaddr_aligned,
app_drom_size, app_drom_size);
#endif
cache_hal_disable(CACHE_TYPE_ALL);
/* Clear the MMU entries that are already set up,
* so the new app only has the mappings it creates.
*/
mmu_hal_unmap_all();
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_drom_vaddr_aligned, app_drom_start_aligned,
app_drom_size, &actual_mapped_len);
mmu_hal_map_region(0, MMU_TARGET_FLASH0,
app_irom_vaddr_aligned, app_irom_start_aligned,
app_irom_size, &actual_mapped_len);
/* ------------------Enable corresponding buses--------------------- */
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned,
app_drom_size);
cache_ll_l1_enable_bus(0, bus_mask);
bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(0, bus_mask);
#if CONFIG_ESPRESSIF_NUM_CPUS > 1
bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
cache_ll_l1_enable_bus(1, bus_mask);
bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
cache_ll_l1_enable_bus(1, bus_mask);
#endif
/* ------------------Enable Cache----------------------------------- */
cache_hal_enable(CACHE_TYPE_ALL);
return (int)rc;
}

80
arch/xtensa/src/esp32s2/loader.h Normal file
View File

@ -0,0 +1,80 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/loader.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
#define __ARCH_XTENSA_SRC_ESP32S2_LOADER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: map_rom_segments
*
* Description:
* Configure the MMU and Cache peripherals for accessing ROM code and data.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
uint32_t app_drom_size, uint32_t app_irom_start,
uint32_t app_irom_vaddr, uint32_t app_irom_size);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_LOADER_H */

10
boards/xtensa/esp32s2/common/scripts/flat_memory.ld
View File

@ -72,6 +72,16 @@ MEMORY
metadata (RX) : org = CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = FLASH_SIZE - ORIGIN(ROM)
#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
ROM (RX) : org = 0x20,
len = FLASH_SIZE - ORIGIN(ROM)
#endif
/* Below values assume the flash cache is on, and have the blocks this

37
boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld
View File

@ -62,8 +62,14 @@ SECTIONS
.flash.rodata :
{
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (esp32s2_start.*) .rodata)
*(EXCLUDE_FILE (esp32s2_start.*) .rodata.*)
*(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
*libarch.a:esp32s2_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata)
*(EXCLUDE_FILE (esp32s2_start.* loader.* esp32s2_region.*
*libarch.a:esp32s2_spiflash.*
*libarch.a:*cache_hal.* *libarch.a:*mmu_hal.*
*libarch.a:*mpu_hal.*) .rodata.*)
*(.srodata.*)
@ -161,6 +167,14 @@ SECTIONS
*(.iram1 .iram1.*)
esp32s2_start.*(.literal .text .literal.* .text.*)
esp32s2_region.*(.text .text.* .literal .literal.*)
loader.*(.text .text.* .literal .literal.*)
*libarch.a:esp32s2_spiflash.*(.literal .text .literal.* .text.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
@ -233,6 +247,15 @@ SECTIONS
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s2_start.*(.rodata .rodata.*)
esp32s2_region.*(.rodata .rodata.*)
loader.*(.rodata .rodata.*)
*libarch.a:esp32s2_spiflash.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
_edata = ABSOLUTE(.);
. = ALIGN(4);
@ -254,7 +277,7 @@ SECTIONS
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
/* The alignment of the ".flash.text" output section is forced to
* 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
@ -264,7 +287,7 @@ SECTIONS
* be equal.
*/
.flash_text_dummy (NOLOAD) : ALIGN(0x0000FFFF)
.flash_text_dummy (NOLOAD) : ALIGN(0x00010000)
{
/* This section is required to skip .flash.rodata area because irom0_0_seg
* and drom0_0_seg reflect the same address space on different buses.
@ -273,7 +296,7 @@ SECTIONS
. = SIZEOF(.flash.rodata);
} >irom0_0_seg
.flash.text : ALIGN(0x0000FFFF)
.flash.text : ALIGN(0x00010000)
{
_stext = .;
@ -307,7 +330,7 @@ SECTIONS
.rtc.bss (NOLOAD) :
{
*(.rtc.bss)
} >rtc_data_seg
} >rtc_slow_seg
.rtc.data :
{
@ -318,5 +341,5 @@ SECTIONS
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
} >rtc_data_seg AT>ROM
} >rtc_slow_seg AT>ROM
}

428
boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld Normal file
View File

@ -0,0 +1,428 @@
/****************************************************************************
* boards/xtensa/esp32s2/common/scripts/simple_boot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Default entry point: */
ENTRY(__start);
SECTIONS
{
/* Send .iram0 code to iram */
.iram0.vectors : ALIGN(4)
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM. */
_init_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
.iram0.text : ALIGN(4)
{
/* Code marked as running out of IRAM */
*(.iram1 .iram1.*)
. = ALIGN (4);
esp32s2_start.*(.literal .text .literal.* .text.*)
esp32s2_region.*(.text .text.* .literal .literal.*)
loader.*(.literal .text .literal.* .text.*)
*libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu.*(.text .text.* .literal .literal.*)
*libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*clk.*(.text .text.* .literal .literal.*)
*libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0)
*libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
*libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*)
*libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
*libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
*libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_flash_config_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
*libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
*libarch.a:*bootloader_random_esp32s2.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
*libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
*libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*)
*libarch.a:*log.*(.text .text.* .literal .literal.*)
*libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
*libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
_iram_text = ABSOLUTE(.);
} >iram0_0_seg AT>ROM
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
. = ALIGN (4);
_iram_end = ABSOLUTE(.);
} >iram0_0_seg
.dram0.dummy (NOLOAD):
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
} >dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
_sbss = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
KEEP (*(.bss))
*(.bss.*)
*(.share.mem)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
_bss_end = ABSOLUTE(.);
} >dram0_0_seg
.noinit (NOLOAD):
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(4);
*(.noinit)
*(.noinit.*)
. = ALIGN(4);
} >dram0_0_seg
.dram0.data : ALIGN(4)
{
/* .data initialized on power-up in ROMed configurations. */
_data_start = ABSOLUTE(.);
_sdata = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
esp32s2_start.*(.rodata .rodata.*)
esp32s2_region.*(.rodata .rodata.*)
loader.*(.rodata .rodata.*)
*libarch.a:*brownout.*(.rodata .rodata.*)
*libarch.a:*cpu.*(.rodata .rodata.*)
*libarch.a:*gpio_hal.*(.rodata .rodata.*)
*libarch.a:*periph_ctrl.*(.rodata .rodata.*)
*libarch.a:*clk.*(.rodata .rodata.*)
*libarch.a:*esp_clk.*(.rodata .rodata.*)
*libarch.a:*esp_clk_tree.*(.rodata .rodata.*)
*libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*)
*libarch.a:*clk_tree_hal.*(.rodata .rodata.*)
*libarch.a:*rtc_init.*(.rodata .rodata.*)
*libarch.a:*rtc_clk.*(.rodata .rodata.*)
*libarch.a:*rtc_clk_init.*(.rodata .rodata.*)
*libarch.a:*rtc_sleep.*(.rodata .rodata.*)
*libarch.a:*rtc_time.*(.rodata .rodata.*)
*libarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
*libarch.a:*uart_hal_iram.*(.rodata .rodata.*)
*libarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
*libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*)
*libarch.a:*bootloader_init.*(.rodata .rodata.*)
*libarch.a:*bootloader_common.*(.rodata .rodata.*)
*libarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_console.*(.rodata .rodata.*)
*libarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_esp32s2.*(.rodata .rodata.*)
*libarch.a:*bootloader_flash.*(.rodata .rodata.*)
*libarch.a:*bootloader_flash_config_esp32s2.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
*libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
*libarch.a:*bootloader_efuse.*(.rodata .rodata.*)
*libarch.a:*bootloader_panic.*(.rodata .rodata.*)
*libarch.a:*bootloader_mem.*(.rodata .rodata.*)
*libarch.a:*bootloader_random.*(.rodata .rodata.*)
*libarch.a:*bootloader_random_esp32s2.*(.rodata .rodata.*)
*libarch.a:*esp_image_format.*(.rodata .rodata.*)
*libarch.a:*bootloader_soc.*(.rodata .rodata.*)
*libarch.a:*bootloader_sha.*(.rodata .rodata.*)
*libarch.a:*flash_encrypt.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
*libarch.a:*uart_periph.*(.rodata .rodata.*)
*libarch.a:*esp_rom_uart.*(.rodata .rodata.*)
*libarch.a:*esp_rom_sys.*(.rodata .rodata.*)
*libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*)
*libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*)
*libarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
*libarch.a:*esp_efuse_fields.*(.rodata .rodata.*)
*libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*)
*libarch.a:*log.*(.rodata .rodata.*)
*libarch.a:*log_noos.*(.rodata .rodata.*)
*libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
_data_end = ABSOLUTE(.);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} >dram0_0_seg AT>ROM
_image_drom_vma = ADDR(.flash.rodata);
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
/* The alignment of the ".flash.rodata" output section is forced to
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
.flash.rodata_dummy (NOLOAD) :
{
. = ALIGN(0x10000);
} > ROM
.flash.rodata :
{
_srodata = ABSOLUTE(.);
*(EXCLUDE_FILE (esp32s2_start.*) .rodata)
*(EXCLUDE_FILE (esp32s2_start.*) .rodata.*)
*(.srodata.*)
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table .gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP(*(.eh_frame))
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
_sinit = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* This table MUST be 4-byte aligned */
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
} >default_rodata_seg AT>ROM
_image_irom_vma = ADDR(.flash.text);
_image_irom_lma = LOADADDR(.flash.text);
_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
/* The alignment of the ".flash.text" output section is forced to
* 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
.flash.text_dummy (NOLOAD) :
{
. += SIZEOF(.flash.rodata);
. = ALIGN(0x10000);
} >default_code_seg AT> ROM
.flash.text :
{
_stext = .;
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
. = ALIGN(4);
. += 16;
_etext = .;
} >default_code_seg AT>ROM
.rtc.text :
{
. = ALIGN(4);
*(.rtc.literal .rtc.text)
} >rtc_iram_seg AT>ROM
.rtc.dummy (NOLOAD) :
{
/* This section is required to skip .rtc.text area because the text and
* data segments reflect the same address space on different buses.
*/
. = SIZEOF(.rtc.text);
} >rtc_data_seg
/* RTC BSS section. */
.rtc.bss (NOLOAD) :
{
*(.rtc.bss)
} >rtc_slow_seg
.rtc.data :
{
*(.rtc.data)
*(.rtc.rodata)
/* Whatever is left from the RTC memory is used as a special heap. */
. = ALIGN (4);
_srtcheap = ABSOLUTE(.);
} >rtc_slow_seg AT>ROM
}

9
boards/xtensa/esp32s2/common/src/Make.defs
View File

@ -72,6 +72,15 @@ ifeq ($(CONFIG_ESP_RMT),y)
CSRCS += esp32s2_board_rmt.c
endif
ifeq ($(CONFIG_ESP32S2_TWAI)$(CONFIG_ARCH_BUTTONS),y)
CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
CHIPHALDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty
CFLAGS += -Wno-undef
CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)components$(DELIM)esp_common$(DELIM)include
CFLAGS += ${INCDIR_PREFIX}$(CHIPHALDIR)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
endif
DEPPATH += --dep-path src
VPATH += :src
CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src

2
boards/xtensa/esp32s2/common/src/esp32s2_board_twai.c
View File

@ -30,8 +30,6 @@
#include <nuttx/can/can.h>
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s2_twai.h"
#ifdef CONFIG_CAN

2
boards/xtensa/esp32s2/esp32s2-kaluga-1/scripts/Make.defs
View File

@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

2
boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs
View File

@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

1
boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_ledc.c
View File

@ -33,7 +33,6 @@
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s2_ledc.h"
/****************************************************************************

2
boards/xtensa/esp32s2/franzininho-wifi/scripts/Make.defs
View File

@ -33,6 +33,8 @@ ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif

2
boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
View File

@ -1,5 +1,5 @@
/****************************************************************************
* boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
* boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
tools/esp32/Config.mk
View File

@ -229,7 +229,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \

2
tools/esp32c3/Config.mk
View File

@ -218,7 +218,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-C3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \

2
tools/esp32c6/Config.mk
View File

@ -47,7 +47,7 @@ define POSTBUILD
$(Q) echo "MKIMAGE: ESP32-C6 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo "Or run: \"make -C $(TOPDIR)/tools/esp32c6\" to install all IDF tools."; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \

28
tools/esp32s2/Config.mk
View File

@ -124,6 +124,13 @@ else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y)
IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \
-H $(CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE) --pad-header \
-S $(CONFIG_ESP32S2_OTA_SLOT_SIZE)
else
# CONFIG_ESPRESSIF_SIMPLE_BOOT
APP_OFFSET := 0x1000
APP_IMAGE := nuttx.bin
FLASH_APP := $(APP_OFFSET) $(APP_IMAGE)
ESPTOOL_BINDIR := .
endif
ESPTOOL_BINS += $(FLASH_APP)
@ -214,7 +221,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S2 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
@ -241,6 +248,25 @@ define MKIMAGE
$(Q) echo nuttx.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.bin (MCUboot compatible)"
endef
else
define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S2 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
fi
$(Q) if [ -z $(FLASH_SIZE) ]; then \
echo "Missing Flash memory size configuration."; \
exit 1; \
fi
$(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ))
esptool.py -c esp32s2 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx
$(Q) echo nuttx.bin >> nuttx.manifest
$(Q) echo "Generated: nuttx.bin"
endef
endif
endif

4
tools/esp32s3/Config.mk
View File

@ -137,7 +137,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \
@ -169,7 +169,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: ESP32-S3 binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \

2
tools/espressif/Config.mk
View File

@ -155,7 +155,7 @@ define MKIMAGE
$(Q) echo "MKIMAGE: NuttX binary"
$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
echo ""; \
echo "esptool.py not found. Please run: \"pip install esptool\""; \
echo "esptool.py not found. Please run: \"pip install esptool==4.8.dev4\""; \
echo ""; \
echo "Run make again to create the nuttx.bin image."; \
exit 1; \