arch/arm/src/imxrt: Minor reparitioning to account for the fact that the GPIO5 base address is not contiguous with the GPIO1-4 base addresses.
This commit is contained in:
Gregory Nutt
parent
10d99cc6e6
commit
17cc0b9bfe
@ -145,7 +145,6 @@
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#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
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#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
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/* 0x401b4000 16KB Reserved */
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#define IMXRT_GPIO_BASE(n) (0x401b8000 + ((n) << 14))
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#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
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#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
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#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
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@ -51,8 +51,9 @@
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#define GPIO2 1 /* Port 2 index */
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#define GPIO3 2 /* Port 3 index */
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#define GPIO4 3 /* Port 4 index */
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#define GPIO5 4 /* Port 5 index */
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#define IMXRT_GPIO_NPORTS 4 /* Four total ports */
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#define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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#define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */
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/* Register offsets *************************************************************************/
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@ -68,15 +69,6 @@
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/* Register addresses ***********************************************************************/
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#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET)
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#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET)
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#define IMXRT_GPIO_PSR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET)
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#define IMXRT_GPIO_ICR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET)
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#define IMXRT_GPIO_ICR2(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET)
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#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET)
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#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET)
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#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET)
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#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
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#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
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#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
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@ -223,9 +223,33 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
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g_gpio2_padmux, /* GPIO2 */
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g_gpio3_padmux, /* GPIO3 */
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g_gpio4_padmux, /* GPIO4 */
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NULL, /* GPIO5 REVISIT */
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NULL /* End of list */
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};
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */
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uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
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{
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IMXRT_GPIO1_BASE
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#if IMXRT_GPIO_NPORTS > 1
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, IMXRT_GPIO2_BASE
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#endif
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#if IMXRT_GPIO_NPORTS > 2
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, IMXRT_GPIO3_BASE
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#endif
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#if IMXRT_GPIO_NPORTS > 3
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, IMXRT_GPIO4_BASE
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#endif
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#if IMXRT_GPIO_NPORTS > 4
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, IMXRT_GPIO5_BASE
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -300,6 +324,8 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset)
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uintptr_t regaddr;
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unsigned int index;
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DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS);
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/* Configure pin as in input */
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imxrt_gpio_dirin(port, pin);
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@ -344,6 +370,8 @@ static inline int imxrt_gpio_configoutput(gpio_pinset_t pinset)
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int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
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DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS);
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/* Set the output value */
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imxrt_gpio_setoutput(port, pin, value);
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@ -483,6 +511,8 @@ void imxrt_gpio_write(gpio_pinset_t pinset, bool value)
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int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS);
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flags = enter_critical_section();
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imxrt_gpio_setoutput(port, pin, value);
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leave_critical_section(flags);
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@ -503,6 +533,8 @@ bool imxrt_gpio_read(gpio_pinset_t pinset)
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int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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bool value;
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DEBUGASSERT((unsigned int)port < IMXRT_GPIO_NPORTS);
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flags = enter_critical_section();
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value = imxrt_gpio_getinput(port, pin);
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leave_critical_section(flags);
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@ -50,6 +50,7 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 32-bit Encoding:
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*
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* ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM
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@ -86,10 +87,11 @@
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#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */
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#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
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# define GPIO_PORT1 (0 << GPIO_PORT_SHIFT) /* GPIO1 */
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# define GPIO_PORT2 (1 << GPIO_PORT_SHIFT) /* GPIO2 */
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# define GPIO_PORT3 (2 << GPIO_PORT_SHIFT) /* GPIO3 */
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# define GPIO_PORT4 (3 << GPIO_PORT_SHIFT) /* GPIO4 */
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# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */
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# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */
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# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */
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# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */
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# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO4 */
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/* GPIO Pin Number:
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*
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@ -179,6 +181,19 @@
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#define GPIO_IOMUX_SHIFT (0) /* Bits 9-15: IOMUX pin configuration */
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#define GPIO_IOMUX_MASK (0xffff << GPIO_IOMUX_SHIFT)
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/* Helper addressing macros */
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#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIO5 macros as indices */
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#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET)
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#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET)
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#define IMXRT_GPIO_PSR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_PSR_OFFSET)
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#define IMXRT_GPIO_ICR1(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR1_OFFSET)
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#define IMXRT_GPIO_ICR2(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ICR2_OFFSET)
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#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET)
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#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET)
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#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -200,6 +215,10 @@ extern "C"
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#define EXTERN extern
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#endif
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/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */
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EXTERN uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS];
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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@ -1367,15 +1367,18 @@ Configuration Sub-directories
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that the part supports auto baudrate detection, but I have found no
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documentation on how to use that.
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Currently only a fixed, configurable BAUD is used and this must
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be set to the BT860 default.
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Currently the "generic" HCI UART upper half is used with the BT860
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and that upper half driver supports only a fixed (but configurable
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BAUD) is used and this must be set to the BT860 default (115200).
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Baud rate can be set with vendor-specific command. Ideally, the
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sequence would be: (1) start at default baud rate, (2) get local
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version info, (3) send the vendor-specific baud rate change command,
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(4) wait for response, and (5) set local UART to higher baud rate.
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A custom BT860 upper half driver is needed that can use vendor
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specific command: Baud rate can be set with such a vendor-specific
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command. Ideally, the sequence would be: (1) start at default baud
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rate, (2) get local version info, (3) send the vendor-specific baud
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rate change command, (4) wait for response, and (5) set the local
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UART to the matching, higher baud rate.
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The custom, vendor-specific command is
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The custom, vendor-specific BT860 command is:
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{0x18, 0xfc, 0x06, 0x00, 0x00, NN, NN, NN, NN}
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@ -1401,8 +1404,8 @@ Configuration Sub-directories
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This is another version of the NuttShell configuration for the
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STM32F4-Discovery with the STM32F4DIS-BB base board. It is very similar
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to the netnsh configuration except that it has IPv6 enabled and IPv4
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disabled. Several network utilities that are not yet available under
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IPv6 are disabled.
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disabled. Several network utilities that are not yet available when
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IPv6 is disabled.
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NOTES:
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