MMCSD SDIO: Add support for a new SDWAIT_WRCOMPLETE condition. The previous logic used a busy-wait loop to pool the card R1 start to determine when the card was ready for the next transfer. That busy-wait can be quite long -- hundreds of milliseconds. And alternative is to look the the SD D0 pin which will change state when the card is no longer busy.
This logic implements a change the avoids the busy-wait poll by reconfiguring the SD D0 pin as a GPIO interrupt, then waiting for the card to becom ready without taking up CPU cycles. This change is conditioned on CONFIG_MMCSD_SDIOWATI_WRCOMPLETE and is currenlty only implemented for the STM32 SDIO driver. From David Sidrane
This commit is contained in:
Gregory Nutt
parent
1f10c56dd0
commit
1842525cc2
108
arch/arm/src/stm32/stm32_sdio.c
Normal file → Executable file
108
arch/arm/src/stm32/stm32_sdio.c
Normal file → Executable file
@ -400,6 +400,9 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven
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/* Interrupt Handling *******************************************************/
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static int stm32_interrupt(int irq, void *context);
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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static int stm32_rdyinterrupt(int irq, void *context);
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#endif
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/* SDIO interface methods ***************************************************/
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@ -619,12 +622,39 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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sdio_eventset_t wkupevent)
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{
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irqstate_t flags;
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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int pinset;
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#endif
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/* Save all of the data and set the new interrupt mask in one, atomic
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* operation.
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*/
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flags = irqsave();
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0)
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{
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/* Do not use this in STM32_SDIO_MASK register */
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waitmask &= !SDIOWAIT_WRCOMPLETE;
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pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK|GPIO_PIN_MASK);
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pinset |= (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI);
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/* Arm the SDIO_D Ready and install Isr */
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stm32_gpiosetevent(pinset, true, false, false, stm32_rdyinterrupt);
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}
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/* Disarm SDIO_D ready */
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if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
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{
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stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false , NULL);
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stm32_configgpio(GPIO_SDIO_D0);
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}
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#endif
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priv->waitevents = waitevents;
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priv->wkupevent = wkupevent;
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priv->waitmask = waitmask;
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@ -1235,9 +1265,32 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven
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}
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/****************************************************************************
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* Interrrupt Handling
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* Interrupt Handling
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rdyinterrupt
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*
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* Description:
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* SDIO ready interrupt handler
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*
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* Input Parameters:
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* dev - An instance of the SDIO device interface
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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static int stm32_rdyinterrupt(int irq, void *context)
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{
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struct stm32_dev_s *priv = &g_sdiodev;
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: stm32_interrupt
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*
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@ -2236,25 +2289,35 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev,
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* interrupts.
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*/
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waitmask = 0;
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if ((eventset & SDIOWAIT_CMDDONE) != 0)
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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if ((eventset & SDIOWAIT_WRCOMPLETE) != 0)
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{
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waitmask |= SDIO_CMDDONE_MASK;
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waitmask = SDIOWAIT_WRCOMPLETE;
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}
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if ((eventset & SDIOWAIT_RESPONSEDONE) != 0)
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else
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#endif
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{
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waitmask |= SDIO_RESPDONE_MASK;
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}
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waitmask = 0;
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if ((eventset & SDIOWAIT_CMDDONE) != 0)
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{
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waitmask |= SDIO_CMDDONE_MASK;
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}
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if ((eventset & SDIOWAIT_TRANSFERDONE) != 0)
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{
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waitmask |= SDIO_XFRDONE_MASK;
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}
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if ((eventset & SDIOWAIT_RESPONSEDONE) != 0)
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{
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waitmask |= SDIO_RESPDONE_MASK;
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}
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/* Enable event-related interrupts */
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if ((eventset & SDIOWAIT_TRANSFERDONE) != 0)
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{
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waitmask |= SDIO_XFRDONE_MASK;
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}
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/* Enable event-related interrupts */
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putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR);
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}
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putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR);
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stm32_configwaitints(priv, waitmask, eventset, 0);
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}
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@ -2324,6 +2387,21 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
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}
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}
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0)
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{
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/* Atomically read pin to see if ready (true) and determine if ISR fired
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* If Pin is ready and if ISR did NOT fire end the wait here
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*/
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if (stm32_gpioread(GPIO_SDIO_D0) &&
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(priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0)
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{
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stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
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}
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}
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#endif
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/* Loop until the event (or the timeout occurs). Race conditions are avoided
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* by calling stm32_waitenable prior to triggering the logic that will cause
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* the wait to terminate. Under certain race conditions, the waited-for
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17
drivers/mmcsd/Kconfig
Normal file → Executable file
17
drivers/mmcsd/Kconfig
Normal file → Executable file
@ -38,6 +38,23 @@ config MMCSD_HAVECARDDETECT
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SDIO driver card detection is
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100% accurate
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config MMCSD_SDIOWAIT_WRCOMPLETE
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bool "Use SDIO_D Busy to detect Write Complete"
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default n
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---help---
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SDIO driver will use SDIO_D Busy signalling to detect Write Complete.
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This option when selected, will enable the MMCSD driver to use the
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underlying (stm32_sdio only) drivers implementation of the SD specs
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SDIO_D Busy signalling to detect Write Complete. This will avoid
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potentially very long (600Ms+) busy waiting in the MMCSD driver.
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To implement SDIO_D Busy signalling, the underlying driver must
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be capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
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interrupt pin. It must then, condition that pin to detect the rising edge
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on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
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return it back to regular SDIO mode, when either the ISR fires or pin is
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found to be high in the SDIO_EVENTWAIT call.
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config MMCSD_SPI
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bool "MMC/SD SPI transfer support"
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default y
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15
drivers/mmcsd/mmcsd_sdio.c
Normal file → Executable file
15
drivers/mmcsd/mmcsd_sdio.c
Normal file → Executable file
@ -1150,6 +1150,15 @@ static int mmcsd_transferready(FAR struct mmcsd_state_s *priv)
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* the TRANSFER state when the card completes the WRITE operation.
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*/
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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ret = mmcsd_eventwait(priv, SDIOWAIT_TIMEOUT|SDIOWAIT_ERROR,
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MMCSD_BLOCK_WDATADELAY);
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if (ret != OK)
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{
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fdbg("ERROR: mmcsd_eventwait for transfer ready failed: %d\n", ret);
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}
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#endif
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starttime = clock_systimer();
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do
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{
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@ -1721,6 +1730,12 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv,
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return ret;
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}
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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/* Arm the write complete detection with timeout */
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SDIO_WAITENABLE(priv->dev, SDIOWAIT_WRCOMPLETE|SDIOWAIT_TIMEOUT);
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#endif
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/* On success, return the number of blocks written */
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return 1;
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22
include/nuttx/sdio.h
Normal file → Executable file
22
include/nuttx/sdio.h
Normal file → Executable file
@ -63,7 +63,27 @@
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#define SDIOWAIT_TIMEOUT (1 << 3) /* Bit 3: Timeout */
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#define SDIOWAIT_ERROR (1 << 4) /* Bit 4: Some other error occurred */
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#define SDIOWAIT_ALLEVENTS 0x1f
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/* SDIOWAIT_WRCOMPLETE (optional) : SDIO driver will use SDIO_D Busy
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* signalling to detect Write Complete. This option when selected, will
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* enable the MMCSD driver to use the underlying (stm32_sdio only) drivers
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* implementation of the SD specs SDIO_D Busy signalling to detect Write
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* Complete. This will avoid potentially very long (600Ms+) busy waiting
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* in the MMCSD driver.
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*
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* To implement SDIO_D Busy signalling, the underlying driver must be
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* capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
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* interrupt pin. It must then, condition that pin to detect the rising
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* edge on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
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* return it back to regular SDIO mode, when either the ISR fires or pin
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* is found to be high in the SDIO_EVENTWAIT call.
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*/
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#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
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# define SDIOWAIT_WRCOMPLETE (1 << 5) /* Bit 5: Hardware Write Completion */
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# define SDIOWAIT_ALLEVENTS 0x3f
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#else
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# define SDIOWAIT_ALLEVENTS 0x1f
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#endif
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/* Media events are used for enable/disable registered event callbacks */
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