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SAMA5D2 fix printf formatter

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Update sam_adc.c

Update sam_adc.c

%08x -> PRIx32

More %08x

Revert incorrect change (PRIx32)

Update sam_tc.c

Update sam_tc.c

more style corrections/typos

Update arch/arm/src/sama5/sam_adc.c

Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
This commit is contained in:
TimJTi 2022-12-02 16:09:43 +00:00 committed by Petro Karashchenko
parent 6950b67b46
commit 18482efc39
3 changed files with 23 additions and 20 deletions
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20
arch/arm/src/sama5/sam_adc.c
View File

@ -935,7 +935,7 @@ static void sam_adc_endconversion(void *arg)
int ret; int ret;
DEBUGASSERT(priv != NULL); DEBUGASSERT(priv != NULL);
ainfo("pending=%08lx\n", priv->pending); ainfo("pending=%08" PRIx32 "\n", priv->pending);
/* Get the set of unmasked, pending ADC interrupts */ /* Get the set of unmasked, pending ADC interrupts */
@ -1062,7 +1062,7 @@ static int sam_adc_interrupt(int irq, void *context, void *arg)
return OK; return OK;
} }
#ifdef SAMA5_ADC_HAVE_CHANNELS #if defined(SAMA5_ADC_HAVE_CHANNELS)
/**************************************************************************** /****************************************************************************
* ADC methods * ADC methods
****************************************************************************/ ****************************************************************************/
@ -1137,13 +1137,13 @@ static void sam_adc_reset(struct adc_dev_s *dev)
/* Reset gain, offset, differential modes */ /* Reset gain, offset, differential modes */
#if defined (ATSAMA5D3) #if defined(ATSAMA5D3)
sam_adc_putreg(priv, SAM_ADC_CGR, 0); sam_adc_putreg(priv, SAM_ADC_CGR, 0);
#endif #endif
sam_adc_putreg(priv, SAM_ADC_COR, 0); sam_adc_putreg(priv, SAM_ADC_COR, 0);
#if !defined CONFIG_SAMA5_ADC_SWTRIG && !defined CONFIG_SAMA5_TSD #if !defined(CONFIG_SAMA5_ADC_SWTRIG) && !defined(CONFIG_SAMA5_TSD)
/* Select software trigger (i.e., basically no trigger) */ /* Select software trigger (i.e., basically no trigger) */
regval = sam_adc_getreg(priv, SAM_ADC_MR); regval = sam_adc_getreg(priv, SAM_ADC_MR);
@ -1172,7 +1172,6 @@ static int sam_adc_setup(struct adc_dev_s *dev)
{ {
struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv; struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
uint32_t regval; uint32_t regval;
int ret;
ainfo("Setup\n"); ainfo("Setup\n");
@ -1417,7 +1416,7 @@ static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
priv->tc = sam_tc_allocate(channel, mode); priv->tc = sam_tc_allocate(channel, mode);
if (!priv->tc) if (!priv->tc)
{ {
aerr("ERROR: Failed to allocate channel %d mode %08x\n", aerr("ERROR: Failed to allocate channel %d mode %08" PRIx32 "\n",
channel, mode); channel, mode);
return -EINVAL; return -EINVAL;
} }
@ -1890,7 +1889,7 @@ static void sam_adc_gain(struct sam_adc_s *priv)
/* Set GAIN0 only. GAIN0 will be used for all channels. */ /* Set GAIN0 only. GAIN0 will be used for all channels. */
sam_adc_putreg(priv, SAM_ADC_CGR, ADC_CGR_GAIN0(CONFIG_SAMA5_ADC_GAIN)); sam_adc_putreg(priv, SAM_ADC_CGR, ADC_CGR_GAIN0(CONFIG_SAMA5_ADC_GAIN));
#endif /* CONFIG_SAMA5_ADC_ANARCH */ # endif /* CONFIG_SAMA5_ADC_ANARCH */
#endif /* ATSAMA5D3 */ #endif /* ATSAMA5D3 */
} }
@ -1951,7 +1950,8 @@ static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2,
*seqr1 |= ADC_SEQR1_USCH(seq, chan); *seqr1 |= ADC_SEQR1_USCH(seq, chan);
} }
ainfo("chan=%d seqr1=%08x seqr2=%08x seq=%d\n", chan, *seqr1, *seqr2, seq); ainfo("chan=%d seqr1=%08" PRIx32 "x seqr2=%08" PRIx32 "seq=%d\n",
chan, *seqr1, *seqr2, seq);
} }
#endif #endif
@ -2379,7 +2379,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address)
if (sam_adc_checkreg(priv, false, regval, address)) if (sam_adc_checkreg(priv, false, regval, address))
{ {
ainfo("%08x->%08x\n", address, regval); ainfo("%08" PRIx32 "->%08" PRIx32 "\n", address, regval);
} }
return regval; return regval;
@ -2400,7 +2400,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address,
{ {
if (sam_adc_checkreg(priv, true, regval, address)) if (sam_adc_checkreg(priv, true, regval, address))
{ {
ainfo("%08x<-%08x\n", address, regval); ainfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, regval);
} }
putreg32(regval, address); putreg32(regval, address);

21
arch/arm/src/sama5/sam_tc.c
View File

@ -56,6 +56,7 @@
#include <string.h> #include <string.h>
#include <assert.h> #include <assert.h>
#include <errno.h> #include <errno.h>
#include <inttypes.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
@ -481,26 +482,27 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg)
uintptr_t base; uintptr_t base;
base = tc->base; base = tc->base;
tminfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); tmrinfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg);
tminfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n",
getreg32(base + SAM_TC_BMR_OFFSET), getreg32(base + SAM_TC_BMR_OFFSET),
getreg32(base + SAM_TC_QIMR_OFFSET), getreg32(base + SAM_TC_QIMR_OFFSET),
getreg32(base + SAM_TC_QISR_OFFSET), getreg32(base + SAM_TC_QISR_OFFSET),
getreg32(base + SAM_TC_WPMR_OFFSET)); getreg32(base + SAM_TC_WPMR_OFFSET));
base = chan->base; base = chan->base;
tminfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); tmrinfo("TC%d Channel %d [%08x]: %s\n", tc->tc,
tminfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", chan->chan, (int)base, msg);
tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n",
getreg32(base + SAM_TC_CMR_OFFSET), getreg32(base + SAM_TC_CMR_OFFSET),
getreg32(base + SAM_TC_SMMR_OFFSET), getreg32(base + SAM_TC_SMMR_OFFSET),
getreg32(base + SAM_TC_RAB_OFFSET), getreg32(base + SAM_TC_RAB_OFFSET),
getreg32(base + SAM_TC_CV_OFFSET)); getreg32(base + SAM_TC_CV_OFFSET));
tminfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n", tmrinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n",
getreg32(base + SAM_TC_RA_OFFSET), getreg32(base + SAM_TC_RA_OFFSET),
getreg32(base + SAM_TC_RB_OFFSET), getreg32(base + SAM_TC_RB_OFFSET),
getreg32(base + SAM_TC_RC_OFFSET), getreg32(base + SAM_TC_RC_OFFSET),
getreg32(base + SAM_TC_SR_OFFSET)); getreg32(base + SAM_TC_SR_OFFSET));
tminfo(" IMR: %08x\n", tmrinfo(" IMR: %08x\n",
getreg32(base + SAM_TC_IMR_OFFSET)); getreg32(base + SAM_TC_IMR_OFFSET));
} }
#endif #endif
@ -601,7 +603,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG #ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval)) if (sam_checkreg(chan->tc, true, regaddr, regval))
{ {
tmrinfo("%08x<-%08x\n", regaddr, regval); tmrinfo("%08" PRIx32 "<-%08" PRIx32 "\n", regaddr, regval);
} }
#endif #endif
@ -860,6 +862,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
uint32_t regval; uint32_t regval;
uint8_t ch; uint8_t ch;
int i; int i;
int ret;
/* Select the timer/counter and get the index associated with the /* Select the timer/counter and get the index associated with the
* channel. * channel.
@ -1267,7 +1270,7 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval)
chan->chan, regid, (unsigned long)regval); chan->chan, regid, (unsigned long)regval);
sam_chan_putreg(chan, g_regoffset[regid], regval); sam_chan_putreg(chan, g_regoffset[regid], regval);
sam_regdump(chan, "Set register"); sam_regdump(chan, "set register");
} }
/**************************************************************************** /****************************************************************************
@ -1406,7 +1409,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks)
uint32_t ftcin = sam_tc_infreq(); uint32_t ftcin = sam_tc_infreq();
int ndx = 0; int ndx = 0;
tmrinfo("frequency=%d\n", frequency); tmrinfo("frequency=%" PRIu32 "\n", frequency);
/* Satisfy lower bound. That is, the value of the divider such that: /* Satisfy lower bound. That is, the value of the divider such that:
* *

2
arch/arm/src/sama5/sam_tsd.c
View File

@ -1755,7 +1755,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
/* Initialize the touchscreen device driver instance */ /* Initialize the touchscreen device driver instance */
priv->adc = adc; /* Save the ADC device handle */ priv->adc = adc; /* Save the ADC device handle */
/* Register the device as an input device */ /* Register the device as an input device */