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STM32H7 Ethernet: Fix ETH_MACMDIOAR_CR_MASK bit mask.

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This commit is contained in:
Markus Bernet 2019-10-21 06:29:13 -06:00 committed by Gregory Nutt
parent 7042ec883e
commit 185557440b
2 changed files with 6 additions and 6 deletions
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4
arch/arm/src/stm32h7/hardware/stm32_ethernet.h
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@ -289,14 +289,14 @@
# define ETH_MACMDIOAR_GOC_READ (3 << ETH_MACMDIOAR_GOC_SHIFT) /* Read */
#define ETH_MACMDIOAR_SKAP (1 << 4) /* Bit 4: Skip Address Packet */
#define ETH_MACMDIOAR_CR_SHIFT (8) /* Bits 8-11: Clock range */
#define ETH_MACMDIOAR_CR_MASK (7 << ETH_MACMDIOAR_CR_SHIFT)
#define ETH_MACMDIOAR_CR_MASK (15 << ETH_MACMDIOAR_CR_SHIFT)
# define ETH_MACMDIOAR_CR_DIV42 (0 << ETH_MACMDIOAR_CR_SHIFT) /* 60-100 MHz HCLK/42 */
# define ETH_MACMDIOAR_CR_DIV62 (1 << ETH_MACMDIOAR_CR_SHIFT) /* 100-150 MHz HCLK/62 */
# define ETH_MACMDIOAR_CR_DIV16 (2 << ETH_MACMDIOAR_CR_SHIFT) /* 20-35 MHz HCLK/16 */
# define ETH_MACMDIOAR_CR_DIV26 (3 << ETH_MACMDIOAR_CR_SHIFT) /* 35-60 MHz HCLK/26 */
# define ETH_MACMDIOAR_CR_DIV102 (4 << ETH_MACMDIOAR_CR_SHIFT) /* 150-250 MHz HCLK/102 */
# define ETH_MACMDIOAR_CR_DIV124 (5 << ETH_MACMDIOAR_CR_SHIFT) /* 250-300 MHz HCLK/124 */
#define ETH_MACMDIOAR_NTC_SHIFT (12) /* Number of Training Clocks */
#define ETH_MACMDIOAR_NTC_SHIFT (12) /* Bits 12-14: Number of Training Clocks */
#define ETH_MACMDIOAR_NTC_MASK (7 << ETH_MACMDIOAR_NTC_SHIFT)
# define ETH_MACMDIOAR_NTC(n) ((uint32_t)(n) << ETH_MACMDIOAR_NTC_SHIFT)
#define ETH_MACMDIOAR_RDA_SHIFT (16) /* Bits 16-20: MII register */

8
arch/arm/src/stm32h7/stm32_ethernet.c
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@ -3186,7 +3186,7 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr,
volatile uint32_t timeout;
uint32_t regval;
/* Configure the MACMDIOAR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0] bits */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ETH_MACMDIOAR_CR_MASK;
@ -3245,7 +3245,7 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
uint32_t regval;
uint16_t value;
/* Configure the MACMDIOAR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MACMDIOAR register, preserving CSR Clock Range CR[3:0] bits */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ETH_MACMDIOAR_CR_MASK;
@ -3277,7 +3277,7 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
ETH_MACMDIOAR_RDA_MASK);
regval |= (ETH_MACMDIOAR_MB | ETH_MACMDIOAR_GOC_WRITE);
/* Write the value into the MACIIDR register before setting the new
/* Write the value into the MACMDIODR register before setting the new
* MACMDIOAR register value.
*/
@ -3433,7 +3433,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
priv->mbps100 = 0;
priv->fduplex = 0;
/* Setup up PHY clocking by setting the SR field in the MACMDIOAR register */
/* Setup up PHY clocking by setting the CR field in the MACMDIOAR register */
regval = stm32_getreg(STM32_ETH_MACMDIOAR);
regval &= ~ETH_MACMDIOAR_CR_MASK;