Start LPC17 DMA support for SDCARD driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5800 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
af22b6cab7
commit
1866578799
@ -69,7 +69,8 @@
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/* Channel Registers */
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#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */
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#define LPC17_NDMACH 8 /* Eight DMA channels */
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#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...,(LPC17_NDMACH-1) */
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#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */
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#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */
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@ -204,7 +205,10 @@
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/* Register bit definitions *********************************************************/
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/* DMA Request Connections **********************************************************/
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#define LPC17_NDMAREQ (16) /* The number of DMA requests */
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#if defined(LPC176x)
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/* Request Numbers */
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# define DMA_REQ_SSP0TX (0)
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# define DMA_REQ_SSP0RX (1)
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# define DMA_REQ_SSP1TX (2)
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@ -217,25 +221,61 @@
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# define DMA_REQ_DAC (7)
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# define DMA_REQ_UART0TX (8)
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# define DMA_REQ_UART0RX (9)
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# define DMA_REQ_UART1TX (10)
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# define DMA_REQ_UART1RX (11)
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# define DMA_REQ_UART2TX (12)
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# define DMA_REQ_UART2RX (13)
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# define DMA_REQ_UART3TX (14)
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# define DMA_REQ_UART3RX (15)
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# define DMA_REQ_UART0TX (8) /* DMASEL08=0*/
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# define DMA_REQ_UART0RX (9) /* DMASEL09=0*/
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# define DMA_REQ_UART1TX (10) /* DMASEL010=0*/
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# define DMA_REQ_UART1RX (11) /* DMASEL011=0*/
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# define DMA_REQ_UART2TX (12) /* DMASEL012=0*/
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# define DMA_REQ_UART2RX (13) /* DMASEL013=0*/
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# define DMA_REQ_UART3TX (14) /* DMASEL014=0*/
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# define DMA_REQ_UART3RX (15) /* DMASEL015=0*/
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# define DMA_REQ_MAT0p0 (8)
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# define DMA_REQ_MAT0p1 (9)
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# define DMA_REQ_MAT1p0 (10)
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# define DMA_REQ_MAT1p1 (11)
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# define DMA_REQ_MAT2p0 (12)
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# define DMA_REQ_MAT2p1 (13)
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# define DMA_REQ_MAT3p0 (14)
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# define DMA_REQ_MAT3p1 (15)
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# define DMA_REQ_MAT0p0 (8) /* DMASEL08=1 */
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# define DMA_REQ_MAT0p1 (9) /* DMASEL09=1 */
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# define DMA_REQ_MAT1p0 (10) /* DMASEL010=1 */
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# define DMA_REQ_MAT1p1 (11) /* DMASEL011=1 */
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# define DMA_REQ_MAT2p0 (12) /* DMASEL012=1 */
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# define DMA_REQ_MAT2p1 (13) /* DMASEL013=1 */
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# define DMA_REQ_MAT3p0 (14) /* DMASEL014=1 */
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# define DMA_REQ_MAT3p1 (15) /* DMASEL015=1 */
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/* DMASEL values. For the LPC176x family, only request numbers 8-15 have
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* DMASEL bits.
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*/
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# define DMA_DMASEL_SSP0TX (0) /* Not applicable */
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# define DMA_DMASEL_SSP0RX (0) /* Not applicable */
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# define DMA_DMASEL_SSP1TX (0) /* Not applicable */
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# define DMA_DMASEL_SSP1RX (0) /* Not applicable */
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# define DMA_DMASEL_ADC (0) /* Not applicable */
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# define DMA_DMASEL_I2SCH0 (0) /* Not applicable */
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# define DMA_DMASEL_I2SCH1 (0) /* Not applicable */
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# define DMA_DMASEL_DAC (0) /* Not applicable */
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# define DMA_DMASEL_UART0TX (0)
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# define DMA_DMASEL_UART0RX (0)
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# define DMA_DMASEL_UART1TX (0)
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# define DMA_DMASEL_UART1RX (0)
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# define DMA_DMASEL_UART2TX (0)
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# define DMA_DMASEL_UART2RX (0)
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# define DMA_DMASEL_UART3TX (0)
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# define DMA_DMASEL_UART3RX (0)
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# define DMA_DMASEL_MAT0p0 (1)
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# define DMA_DMASEL_MAT0p1 (1)
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# define DMA_DMASEL_MAT1p0 (1)
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# define DMA_DMASEL_MAT1p1 (1)
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# define DMA_DMASEL_MAT2p0 (1)
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# define DMA_DMASEL_MAT2p1 (1)
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# define DMA_DMASEL_MAT3p0 (1)
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# define DMA_DMASEL_MAT3p1 (1)
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#elif defined(LPC178x)
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/* Request Numbers */
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# define DMA_REQ_SDCARD (1) /* DMASEL01=0 */
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# define DMA_REQ_SSP0TX (2) /* DMASEL02=0 */
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@ -251,25 +291,62 @@
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# define DMA_REQ_MAT1p1 (3) /* DMASEL03=1 */
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# define DMA_REQ_MAT2p0 (4) /* DMASEL04=1 */
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# define DMA_REQ_MAT2p1 (5) /* DMASEL05=1 */
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# define DMA_REQ_MAT3p0 (14) /* DMASEL14=0 */
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# define DMA_REQ_MAT3p1 (15) /* DMASEL15=0 */
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# define DMA_REQ_MAT3p0 (14) /* DMASEL14=1 */
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# define DMA_REQ_MAT3p1 (15) /* DMASEL15=1 */
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# define DMA_REQ_I2SCH0 (6) /* DMASEL06=1 */
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# define DMA_REQ_I2SCH1 (7) /* DMASEL07=1 */
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# define DMA_REQ_ADC (8)
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# define DMA_REQ_DAC (9)
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# define DMA_REQ_ADC (8) /* Not applicable */
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# define DMA_REQ_DAC (9) /* Not applicable */
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# define DMA_REQ_UART0TX (10) /* DMASEL10=1 */
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# define DMA_REQ_UART0RX (11) /* DMASEL11=1 */
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# define DMA_REQ_UART1TX (12) /* DMASEL12=1 */
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# define DMA_REQ_UART1RX (13) /* DMASEL13=1 */
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# define DMA_REQ_UART2TX (14) /* DMASEL14=1 */
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# define DMA_REQ_UART2RX (15) /* DMASEL15=1 */
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# define DMA_REQ_UART3TX (10) /* DMASEL10=0 */
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# define DMA_REQ_UART3RX (11) /* DMASEL11=0 */
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# define DMA_REQ_UART4TX (12) /* DMASEL12=0 */
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# define DMA_REQ_UART4RX (13) /* DMASEL13=0 */
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# define DMA_REQ_UART0TX (10) /* DMASEL10=0 */
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# define DMA_REQ_UART0RX (11) /* DMASEL11=0 */
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# define DMA_REQ_UART1TX (12) /* DMASEL12=0 */
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# define DMA_REQ_UART1RX (13) /* DMASEL13=0 */
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# define DMA_REQ_UART2TX (14) /* DMASEL14=0 */
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# define DMA_REQ_UART2RX (15) /* DMASEL15=0 */
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# define DMA_REQ_UART3TX (10) /* DMASEL10=1 */
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# define DMA_REQ_UART3RX (11) /* DMASEL11=1 */
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# define DMA_REQ_UART4TX (12) /* DMASEL12=1 */
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# define DMA_REQ_UART4RX (13) /* DMASEL13=1 */
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/* DMASEL values */
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# define DMA_DMASEL_SDCARD (0)
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# define DMA_DMASEL_SSP0TX (0)
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# define DMA_DMASEL_SSP0RX (0)
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# define DMA_DMASEL_SSP1TX (0)
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# define DMA_DMASEL_SSP1RX (0)
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# define DMA_DMASEL_SSP2TX (0)
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# define DMA_DMASEL_SSP2RX (0)
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# define DMA_DMASEL_MAT0p0 (1)
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# define DMA_DMASEL_MAT0p1 (1)
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# define DMA_DMASEL_MAT1p0 (1)
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# define DMA_DMASEL_MAT1p1 (1)
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# define DMA_DMASEL_MAT2p0 (1)
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# define DMA_DMASEL_MAT2p1 (1)
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# define DMA_DMASEL_MAT3p0 (1)
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# define DMA_DMASEL_MAT3p1 (1)
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# define DMA_DMASEL_I2SCH0 (1)
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# define DMA_DMASEL_I2SCH1 (1)
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# define DMA_DMASEL_ADC (0) /* Not applicable */
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# define DMA_DMASEL_DAC (0) /* Not applicable */
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# define DMA_DMASEL_UART0TX (0)
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# define DMA_DMASEL_UART0RX (0)
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# define DMA_DMASEL_UART1TX (0)
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# define DMA_DMASEL_UART1RX (0)
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# define DMA_DMASEL_UART2TX (0)
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# define DMA_DMASEL_UART2RX (0)
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# define DMA_DMASEL_UART3TX (1)
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# define DMA_DMASEL_UART3RX (1)
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# define DMA_DMASEL_UART4TX (1)
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# define DMA_DMASEL_UART4RX (1)
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#endif
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/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */
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@ -287,6 +364,7 @@
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*/
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#define DMACH(n) (1 << (n)) /* n=0,1,...7 */
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#define DMACH_ALL (0xff)
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/* For each of the following registers, bits 0-15 represent a set of encoded
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* DMA sources. Bits 16-31 are reserved in each case.
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@ -42,7 +42,9 @@
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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@ -82,6 +84,25 @@
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one DMA channel */
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struct lpc17_dmach_s
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{
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bool inuse; /* True: The channel is in use */
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dma_callback_t callback; /* DMA completion callback function */
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void *arg; /* Argument to pass to the callback function */
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};
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/* This structure represents the state of the LPC17 DMA block */
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struct lpc17_gpdma_s
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{
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sem_t exclsem; /* For exclusive access to the DMA channel list */
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/* This is the state of each DMA channel */
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struct lpc17_dmach_s dmach[LPC17_NDMACH];
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};
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/****************************************************************************
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* Private Function Prototypes
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@ -90,6 +111,9 @@
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* The state of the LPC17 DMA block */
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static struct lpc17_gpdma_s g_gpdma;
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/****************************************************************************
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* Public Data
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@ -116,6 +140,75 @@
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void lpc17_dmainitilaize(void)
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{
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uint32_t regval;
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int i;
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/* Enable clocking to the GPDMA block */
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regval = getreg32(LPC17_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCGPDMA;
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putreg32(regval, LPC17_SYSCON_PCONP);
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/* Reset all channel configurations */
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for (i = 0; i < LPC17_NDMACH; i++)
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{
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putreg32(0, LPC17_DMACH_CONFIG(i));
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}
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/* Clear all DMA interrupts */
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putreg32(DMACH_ALL, LPC17_DMA_INTTCCLR);
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putreg32(DMACH_ALL, LPC17_DMA_INTERRCLR);
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/* Initialize the DMA state structure */
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sem_init(&g_gpdma.exclsem, 0, 1);
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}
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/****************************************************************************
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* Name: lpc17_dmaconfigure
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*
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* Description:
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* Configure a DMA request. Each DMA request may have two different DMA
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* request sources. This associates one of the sources with a DMA request.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate)
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{
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uint32_t regval;
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DEBUGASSERT(dmarequest < LPC17_NDMAREQ);
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#ifdef LPC176x
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/* For the LPC176x family, only request numbers 8-15 have DMASEL bits */
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if (dmarequest < 8)
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{
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return;
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}
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dmarequest -= 8;
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#endif
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/* Set or clear the DMASEL bit corresponding to the request number */
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regval = getreg32(LPC17_SYSCON_DMAREQSEL);
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if (alternate)
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{
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regval |= (1 << dmarequest);
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}
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else
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{
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regval &= ~(1 << dmarequest);
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}
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putreg32(regval, LPC17_SYSCON_DMAREQSEL);
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}
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/****************************************************************************
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@ -134,7 +227,37 @@ void lpc17_dmainitilaize(void)
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DMA_HANDLE lpc17_dmachannel(void)
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{
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return NULL;
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struct lpc17_dmach_s *dmach = NULL;
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int ret;
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int i;
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/* Get exclusive access to the GPDMA state structure */
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do
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{
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ret = sem_wait(&g_gpdma.exclsem);
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DEBUGASSERT(ret == 0 || errno == EINTR);
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}
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while (ret < 0);
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/* Find an available DMA channel */
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for (i = 0; i < LPC17_NDMACH; i++)
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{
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if (!g_gpdma.dmach[i].inuse)
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{
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/* Found one! */
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dmach = &g_gpdma.dmach[i];
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g_gpdma.dmach[i].inuse = true;
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break;
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}
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}
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/* Return what we found (or not) */
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sem_post(&g_gpdma.exclsem);
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return (DMA_HANDLE)dmach;
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}
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/****************************************************************************
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@ -152,6 +275,15 @@ DMA_HANDLE lpc17_dmachannel(void)
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void lpc17_dmafree(DMA_HANDLE handle)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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/* Mark the channel available. This is an atomic operation and needs no
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* special protection.
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*/
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dmach->inuse = false;
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}
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/****************************************************************************
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@ -163,8 +295,13 @@ void lpc17_dmafree(DMA_HANDLE handle)
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****************************************************************************/
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int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
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uint32_t srcaddr, uint32_t destaddr, size_t nbytes)
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uint32_t srcaddr, uint32_t destaddr, size_t nxfrs)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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#warning "Missing logic"
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return -ENOSYS;
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}
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@ -178,6 +315,17 @@ int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
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int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse && callback);
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/* Save the callback information */
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dmach->callback = callback;
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dmach->arg = arg;
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/* Start the DMA */
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#warning "Missing logic"
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return -ENOSYS;
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}
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@ -193,6 +341,10 @@ int lpc17_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
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void lpc17_dmastop(DMA_HANDLE handle)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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#warning "Missing logic"
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}
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/****************************************************************************
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@ -206,6 +358,10 @@ void lpc17_dmastop(DMA_HANDLE handle)
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#ifdef CONFIG_DEBUG_DMA
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void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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#warning "Missing logic"
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}
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#endif /* CONFIG_DEBUG_DMA */
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@ -220,6 +376,10 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs)
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#ifdef CONFIG_DEBUG_DMA
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void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, const char *msg)
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{
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struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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#warning "Missing logic"
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}
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#endif /* CONFIG_DEBUG_DMA */
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@ -137,6 +137,20 @@ extern "C"
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void lpc17_dmainitilaize(void);
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/****************************************************************************
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* Name: lpc17_dmaconfigure
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*
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* Description:
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* Configure a DMA request. Each DMA request may have two different DMA
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* request sources. This associates one of the sources with a DMA request.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void lpc17_dmaconfigure(uint8_t dmarequest, bool alternate);
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/****************************************************************************
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* Name: lpc17_dmachannel
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*
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@ -177,7 +191,7 @@ void lpc17_dmafree(DMA_HANDLE handle);
|
||||
****************************************************************************/
|
||||
|
||||
int lpc17_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
|
||||
uint32_t srcaddr, uint32_t destaddr, size_t nbytes);
|
||||
uint32_t srcaddr, uint32_t destaddr, size_t nxfrs);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_dmastart
|
||||
|
||||
@ -2475,7 +2475,7 @@ static int lpc17_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
|
||||
ret = lpc17_dmasetup(priv->dma, SDCARD_RXDMA32_CONTROL,
|
||||
SDCARD_RXDMA32_CONFIG, LPC17_SDCARD_FIFO,
|
||||
(uint32_t)buffer, buflen);
|
||||
(uint32_t)buffer, (buflen + 3) >> 2);
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Start the DMA */
|
||||
@ -2547,7 +2547,7 @@ static int lpc17_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
ret = lpc17_dmasetup(priv->dma, SDCARD_TXDMA32_CONTROL,
|
||||
SDCARD_TXDMA32_CONFIG, (uint32_t)buffer,
|
||||
LPC17_SDCARD_FIFO, buflen);
|
||||
LPC17_SDCARD_FIFO, (buflen + 3) >> 2);
|
||||
if (ret == OK)
|
||||
{
|
||||
lpc17_sample(priv, SAMPLENDX_BEFORE_ENABLE);
|
||||
@ -2711,9 +2711,13 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
|
||||
priv->waitwdog = wd_create();
|
||||
DEBUGASSERT(priv->waitwdog);
|
||||
|
||||
/* Allocate a DMA channel */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
/* Configure the SDCARD DMA request */
|
||||
|
||||
lpc17_dmaconfigure(DMA_REQ_SDCARD, DMA_DMASEL_SDCARD);
|
||||
|
||||
/* Allocate a DMA channel for SDCARD DMA */
|
||||
|
||||
priv->dma = lpc17_dmachannel();
|
||||
DEBUGASSERT(priv->dma);
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user