arch/arm/src/lpc54xx: Add DMA register definition header file.
This commit is contained in:
Gregory Nutt
parent
9bc3c04eaf
commit
187747d2e5
@ -137,17 +137,5 @@
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#define LPC54_CTIMER3_BASE 0x40048000 /* CTIMER3 */
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#define LPC54_CTIMER4_BASE 0x40049000 /* CTIMER4 */
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H */
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246
arch/arm/src/lpc54xx/chip/lpc54_dma.h
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246
arch/arm/src/lpc54xx/chip/lpc54_dma.h
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@ -0,0 +1,246 @@
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/****************************************************************************************************
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* arch/arm/src/lpc54xx/lpc54_dma.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H
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#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/lpc54_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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#define LPC54_DMA_NCHANNELS 29 /* 29 DMA channels, 0..28 */
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/* Register offsets *********************************************************************************/
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/* Global control and status registers */
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#define LPC54_DMA_CTRL_OFFSET 0x0000 /* DMA control */
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#define LPC54_DMA_INTSTA_OFFSET 0x0004 /* Interrupt status */
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#define LPC54_DMA_SRAMBASE_OFFSET 0x0008 /* SRAM address of the channel configuration table */
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/* Shared registers */
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#define LPC54_DMA_ENABLESET0_OFFSET 0x0020 /* Channel enable read and Set for all DMA channels */
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#define LPC54_DMA_ENABLECLR0_OFFSET 0x0028 /* Channel enable clear for all DMA channels */
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#define LPC54_DMA_ACTIVE0_OFFSET 0x0030 /* Channel active status for all DMA channels */
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#define LPC54_DMA_BUSY0_OFFSET 0x0038 /* Channel busy status for all DMA channels */
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#define LPC54_DMA_ERRINT0_OFFSET 0x0040 /* Error interrupt status for all DMA channels */
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#define LPC54_DMA_INTENSET0_OFFSET 0x0048 /* Interrupt enable read and Set for all DMA channels */
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#define LPC54_DMA_INTENCLR0_OFFSET 0x0050 /* Interrupt enable clear for all DMA channels */
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#define LPC54_DMA_INTA0_OFFSET 0x0058 /* Interrupt A status for all DMA channels */
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#define LPC54_DMA_INTB0_OFFSET 0x0060 /* Interrupt B status for all DMA channels */
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#define LPC54_DMA_SETVALID0_OFFSET 0x0068 /* Set ValidPending control bits for all DMA channels */
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#define LPC54_DMA_SETTRIG0_OFFSET 0x0070 /* Set trigger control bits for all DMA channels */
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#define LPC54_DMA_ABORT0_OFFSET 0x0078 /* Channel abort control for all DMA channels */
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/* Channel registers
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*
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* CFGn Configuration register for DMA channel n
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* CTLSTATn Control and status register for DMA channel n
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* XFERCFGn Transfer configuration register for DMA channel n
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*/
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#define LPC54_DMA_CHAN_OFFSET(n) ((n) << 4)
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#define LPC54_DMA_CHAN_BASE_OFFSET 0x0400
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#define LPC54_DMA_CFG_OFFSET 0x0000
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#define LPC54_DMA_CTLSTAT_OFFSET 0x0004
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#define LPC54_DMA_XFERCFG_OFFSET 0x0008
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#define LPC54_DMA_CFGn_OFFSET(n) (LPC54_DMA_CHAN_BASE_OFFSET + LPC54_DMA_CHAN_OFFSET(n) + LPC54_DMA_CFG_OFFSET)
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#define LPC54_DMA_CTLSTATn_OFFSET(n) (LPC54_DMA_CHAN_BASE_OFFSET + LPC54_DMA_CHAN_OFFSET(n) + LPC54_DMA_CTLSTAT_OFFSET)
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#define LPC54_DMA_XFERCFGn_OFFSET(n) (LPC54_DMA_CHAN_BASE_OFFSET + LPC54_DMA_CHAN_OFFSET(n) + LPC54_DMA_CTLSTAT_OFFSET)
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/* Register addresses *******************************************************************************/
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/* Global control and status registers */
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#define LPC54_DMA_CTRL (LPC54_DMA_BASE + LPC54_DMA_CTRL_OFFSET)
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#define LPC54_DMA_INTSTA (LPC54_DMA_BASE + LPC54_DMA_INTSTA_OFFSET)
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#define LPC54_DMA_SRAMBASE (LPC54_DMA_BASE + LPC54_DMA_SRAMBASE_OFFSET)
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/* Shared registers */
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#define LPC54_DMA_ENABLESET0 (LPC54_DMA_BASE + LPC54_DMA_ENABLESET0_OFFSET)
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#define LPC54_DMA_ENABLECLR0 (LPC54_DMA_BASE + LPC54_DMA_ENABLECLR0_OFFSET)
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#define LPC54_DMA_ACTIVE0 (LPC54_DMA_BASE + LPC54_DMA_ACTIVE0_OFFSET)
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#define LPC54_DMA_BUSY0 (LPC54_DMA_BASE + LPC54_DMA_BUSY0_OFFSET)
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#define LPC54_DMA_ERRINT0 (LPC54_DMA_BASE + LPC54_DMA_ERRINT0_OFFSET)
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#define LPC54_DMA_INTENSET0 (LPC54_DMA_BASE + LPC54_DMA_INTENSET0_OFFSET)
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#define LPC54_DMA_INTENCLR0 (LPC54_DMA_BASE + LPC54_DMA_INTENCLR0_OFFSET)
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#define LPC54_DMA_INTA0 (LPC54_DMA_BASE + LPC54_DMA_INTA0_OFFSET)
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#define LPC54_DMA_INTB0 (LPC54_DMA_BASE + LPC54_DMA_INTB0_OFFSET)
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#define LPC54_DMA_SETVALID0 (LPC54_DMA_BASE + LPC54_DMA_SETVALID0_OFFSET)
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#define LPC54_DMA_SETTRIG0 (LPC54_DMA_BASE + LPC54_DMA_SETTRIG0_OFFSET)
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#define LPC54_DMA_ABORT0 (LPC54_DMA_BASE + LPC54_DMA_ABORT0_OFFSET)
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/* Channel registers */
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#define LPC54_DMA_CFG(n) (LPC54_DMA_BASE + LPC54_DMA_CFGn_OFFSET(n))
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#define LPC54_DMA_CTLSTAT(n) (LPC54_DMA_BASE + LPC54_DMA_CTLSTATn_OFFSET(n))
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#define LPC54_DMA_XFERCFG(n) (LPC54_DMA_BASE + LPC54_DMA_XFERCFGn_OFFSET(n))
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/* Register bit definitions *************************************************************************/
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/* DMA control */
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#define DMA_CTRL_ENABLE (1 << 0) /* Bit 0: DMA controller master enable */
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/* Interrupt status */
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#define DMA_INTSTA_ACTIVEINT (1 << 1) /* Bit 1: Interrupt pending */
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#define DMA_INTSTA_ACTIVEERRINTT (1 << 2) /* Bit 2: error interruptpending */
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/* SRAM address of the channel configuration table (Bits 9-31) */
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/* Channel enable read and Set for all DMA channels */
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#define DMA_ENABLESET0(n) (1 << (n)) /* Bit n: Enable/disable DMA channel n */
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/* Channel enable clear for all DMA channels */
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#define DMA_ENABLECLR0(n) (1 << (n)) /* Bit n: Disable DMA channel n */
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/* Channel active status for all DMA channels */
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#define DMA_ACTIVE0(n) (1 << (n)) /* Bit n: Channel n active */
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/* Channel busy status for all DMA channels */
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#define DMA_BUSY0(n) (1 << (n)) /* Bit n: Channel n busy */
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/* Error interrupt status for all DMA channels */
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#define DMA_ERRINT0 (1 << (n)) /* Bit n: Error interrupt active*/
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/* Interrupt enable read and Set for all DMA channels */
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#define DMA_INTENSET0 (1 << (n)) /* Bit n: Enable channel n interrupt */
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/* Interrupt enable clear for all DMA channels */
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#define DMA_INTENCLR0 (1 << (n)) /* Bit n: Disable channel n interrupt */
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/* Interrupt A status for all DMA channels */
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#define DMA_INTA0 (1 << (n)) /* Bit n: DMA channel n interrupt A active */
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/* Interrupt B status for all DMA channels */
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#define DMA_INTB0 (1 << (n)) /* Bit n: DMA channel n interrupt B active */
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/* Set ValidPending control bits for all DMA channels */
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#define DMA_SETVALID0 (1 << (n)) /* Bit n: SETVALID control for DMA channel n */
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/* Set trigger control bits for all DMA channels */
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#define DMA_SETTRIG0 (1 << (n)) /* Bit n: Set Trigger control bit for DMA channel n */
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/* Channel abort control for all DMA channels */
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#define DMA_ABORT0 (1 << (n)) /* Bit n: Abort control for DMA channel n */
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/* Configuration register for DMA channel n=0..28 */
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#define DMA_CFG_PERIPHREQEN (1 << 0) /* Bit 0: Peripheral request Enable */
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#define DMA_CFG_HWTRIGEN (1 << 1) /* Bit 1: Hardware Triggering Enable for this channel */
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#define DMA_CFG_TRIGPOL (1 << 4) /* Bit 4: Trigger Polarity */
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#define DMA_CFG_TRIGTYPE (1 << 5) /* Bit 5: Trigger Type */
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# define DMA_CFG_TRIGTYPE_EDGE (0)
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# define DMA_CFG_TRIGTYPE_LEVEL DMA_CFG_TRIGTYPE
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#define DMA_CFG_TRIGBURST (1 << 6) /* Bit 6: Trigger Burst */
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#define DMA_CFG_BURSTPOWER_SHIFT (8) /* Bits 8-11: Burst Power */
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#define DMA_CFG_BURSTPOWER_MASK (15 << DMA_CFG_BURSTPOWER_SHIFT)
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# define DMA_CFG_BURSTPOWER_SIZE1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 */
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# define DMA_CFG_BURSTPOWER_SIZE2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2) */
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# define DMA_CFG_BURSTPOWER_SIZE4 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4) */
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# define DMA_CFG_BURSTPOWER_SIZE8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8) */
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# define DMA_CFG_BURSTPOWER_SIZE16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 */
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# define DMA_CFG_BURSTPOWER_SIZE32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 */
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# define DMA_CFG_BURSTPOWER_SIZE64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 */
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# define DMA_CFG_BURSTPOWER_SIZE128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 */
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# define DMA_CFG_BURSTPOWER_SIZE256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 */
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# define DMA_CFG_BURSTPOWER_SIZE512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 512 */
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# define DMA_CFG_BURSTPOWER_SIZE1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 */
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#define DMA_CFG_SRCBURSTWRAP (1 << 14) /* Bit 14: Source Burst Wrap */
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#define DMA_CFG_DSTBURSTWRAP (1 << 15) /* Bit 15: Destination Burst Wrap */
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#define DMA_CFG_CHPRIORITY_SHIFT (16) /* Bits 16-18: Priority of this channel */
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#define DMA_CFG_CHPRIORITY_MASK (7 << DMA_CFG_CHPRIORITY_MASK)
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# define DMA_CFG_CHPRIORITY(n) ((uint32_t)(n) << DMA_CFG_CHPRIORITY_MASK)
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# define DMA_CFG_CHPRIORITY_MAX (0 << DMA_CFG_CHPRIORITY_MASK) /* highest priority */
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# define DMA_CFG_CHPRIORITY_MIn (7 << DMA_CFG_CHPRIORITY_MASK) /* lowest priority */
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/* Control and status register for DMA channel n=0..28 */
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#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /* Bit 0: Valid pending flag for this channel */
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#define DMA_CTLSTAT_TRIG (1 << 2) /* Bit 2: Trigger flag */
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/* Transfer configuration register for DMA channel n=0..28 */
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#define DMA_XFERCFG_CFGVALID (1 << 0) /* Bit 0: Configuration Valid flag */
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#define DMA_XFERCFG_RELOAD (1 << 1) /* Bit 1: Channel control structure will be reloaded */
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#define DMA_XFERCFG_SWTRIG (1 << 2 /* Bit 2: Software Trigger */
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#define DMA_XFERCFG_CLRTRIG (1 << 3) /* Bit 3: Clear Trigger. 0 */
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#define DMA_XFERCFG_SETINTA (1 << 4) /* Bit 4: Set Interrupt flag A for this channel */
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#define DMA_XFERCFG_SETINTB (1 << 5) /* Bit 5: Set Interrupt flag B for this channel */
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#define DMA_XFERCFG_WIDTH_SHIFT (8) /* Bits 8-9: Transfer width used for this DMA channel */
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#define DMA_XFERCFG_WIDTH_MASK (3 << DMA_XFERCFG_WIDTH_SHIFT)
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# define DMA_XFERCFG_WIDTH _MASK (0 << DMA_XFERCFG_WIDTH_SHIFT) /* 8-bit */
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# define DMA_XFERCFG_WIDTH _MASK (1 << DMA_XFERCFG_WIDTH_SHIFT) /* 16-bit */
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# define DMA_XFERCFG_WIDTH _MASK (2 << DMA_XFERCFG_WIDTH_SHIFT) /* 32-bit */
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#define DMA_XFERCFG_SRCINC_SHIFT (12) /* Bits 12-13: Source address increment control */
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#define DMA_XFERCFG_SRCINC_MASK (3 << DMA_XFERCFG_SRCINC_SHIFT)
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# define DMA_XFERCFG_SRCINC_NONE (0 << DMA_XFERCFG_SRCINC_SHIFT) /* None */
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# define DMA_XFERCFG_SRCINC_WIDTH (1 << DMA_XFERCFG_SRCINC_SHIFT) /* 1 x width */
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# define DMA_XFERCFG_SRCINC_2xWIDTH (2 << DMA_XFERCFG_SRCINC_SHIFT) /* 2 x width */
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# define DMA_XFERCFG_SRCINC_4xWIDTH (3 << DMA_XFERCFG_SRCINC_SHIFT) /* 4 x width */
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#define DMA_XFERCFG_DSTINC_SHIFT (14) /* Bits 14:15: Destination address increment control */
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#define DMA_XFERCFG_DSTINC_MASK (3 << DMA_XFERCFG_DSTINC_SHIFT)
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# define DMA_XFERCFG_SRCINC_NONE (0 << DMA_XFERCFG_DSTINC_SHIFT) /* None */
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# define DMA_XFERCFG_DSTINC_WIDTH (1 << DMA_XFERCFG_DSTINC_SHIFT) /* 1 x width */
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# define DMA_XFERCFG_DSTINC_2xWIDTH (2 << DMA_XFERCFG_DSTINC_SHIFT) /* 2 x width */
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# define DMA_XFERCFG_DSTINC_4xWIDTH (3 << DMA_XFERCFG_DSTINC_SHIFT) /* 4 x width */
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#define DMA_XFERCFGXFERCOUNT_SHIFT (16) /* Bits 16:25: Total number of transfers to be performed -1 */
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#define DMA_XFERCFGXFERCOUNT_MASK (0x3ff << DMA_XFERCFGXFERCOUNT_SHIFT)
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# define DMA_XFERCFGXFERCOUNT(n) ((uint32_t)((n)-1) << DMA_XFERCFGXFERCOUNT_SHIFT)
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H */
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@ -84,16 +84,4 @@
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/* LS 48-bit counter (Bits 0-31: 48-bit up counter) */
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/* MS 48-bit counter (Bits 32-47: 48-bit up counter) */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H */
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