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Start lpc17xx port

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2687 42af7a65-404d-4744-a932-0658087f49c3
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patacongo 2010-05-21 02:43:40 +00:00
parent d802b86f09
commit 189075d71f
3 changed files with 410 additions and 0 deletions
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205
arch/arm/include/lpc17xx/irq.h Executable file
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/****************************************************************************
* arch/lpc17xxx/irq.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC17XX_IRQ_H
#define __ARCH_LPC17XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_NEXTINT (35)
/* No GPIO interrupts yet */
#define LPC17_NGPIOAIRQS 0
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_LPC17XX_IRQ_H */

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arch/arm/src/lpc17xx/chip.h Executable file
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/************************************************************************************
* arch/arm/src/lpc17xx/chip.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_H
#define __ARCH_ARM_SRC_LPC17XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_LPC17XX_LPC178)
#else
# error "Unsupported STM32 chip"
#endif
/* Include only the memory map. Other chip hardware files should then include this
* file for the proper setup
*/
#include "lpc17xx_memorymap.h"
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_H */

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arch/arm/src/lpc17xx/lpc17_memorymap.h Executable file
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/************************************************************************************
* arch/arm/src/lpc17xx/lpc17_memorymap.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H
#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Memory Map ***********************************************************************/
#define LPC17X_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatilenmemory */
#define LPC17X_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
#define LPC17X_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
#define LPC17X_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
# define LPC17X_SRAM_BANK0 0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
# define LPC17X_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank0 (devices 64Kb) */
#define LPC17X_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
#define LPC17X_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
# define LPC17X_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define LPC17X_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define LPC17X_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
#define LPC17_SCS_BASE 0xe000e000
#define LPC17_DEBUGMCU_BASE 0xe0042000
/* APB0 Peripherals *****************************************************************/
#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */
#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */
#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */
#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */
#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */
/* -0x40017fff: Reserved */
#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */
#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */
#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */
#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */
#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */
#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */
#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */
#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */
#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */
#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */
#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */
#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */
#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */
/* -0x4005bfff: Reserved */
#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */
/* -0x4007ffff: Reserved */
/* APB1 Peripherals *****************************************************************/
/* -0x40087fff: Reserved */
#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */
#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */
#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */
#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */
#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
/* -0x400a7fff: Reserved */
#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
/* -0x400affff: Reserved */
#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */
/* -0x400b7fff: Reserved */
#define LPC17_MPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */
#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */
/* -0x400fbfff: Reserved */
#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */
/* AHB Peripherals ******************************************************************/
#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */
#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */
#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */