From 18d3fa9eea6f092504ec1aef26eef6a8d9c7ea6b Mon Sep 17 00:00:00 2001 From: YAMAMOTO Takashi Date: Tue, 31 Mar 2020 13:06:52 +0900 Subject: [PATCH] xtensa: Save PS correctly in syscall handler "EPS" is not a real register. It's just a base value of EPS_{2..7}. --- arch/xtensa/src/common/xtensa_user_handler.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 9e7b44cd73..d14c6299be 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -287,7 +287,7 @@ _xtensa_syscall_handler: mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS /* Save interruptee's PS */ + rsr a0, PS /* Save interruptee's PS */ s32i a0, sp, (4 * REG_PS) rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ s32i a0, sp, (4 * REG_A0) @@ -390,7 +390,7 @@ _xtensa_syscall_handler: l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ - rsync /* Ensure EPS and EPC written */ + rsync /* Ensure PS and EPC written */ /* Return from exception. RFE returns from either the UserExceptionVector * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then