tiva: Fix nxstyle warnings
arch/arm/include/tiva/cc13x0_irq.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/cc13x2_cc26x2_irq.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/chip.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/irq.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/lm3s_irq.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/lm4f_irq.h:
* Fix nxstyle warnings. No functional changes.
arch/arm/include/tiva/tm4c_irq.h:
* Fix nxstyle warnings. No functional changes.
This commit is contained in:
Nathan Hartman
Abdelatif Guettouche
parent
c59fcd3a53
commit
18edab3ad2
@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/include/tiva/cc13x0_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,24 +31,24 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H
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#define __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/******************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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******************************************************************************/
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* External interrupts (vectors >= 16) */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/include/tiva/cc13x2_cc26x2_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,24 +31,24 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_IRQ_H
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#define __ARCH_ARM_INCLUDE_TIVA_CC13X2_CC26x2_IRQ_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/******************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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******************************************************************************/
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* External interrupts (vectors >= 16) */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/include/tiva/chip.h
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*
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* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
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@ -33,20 +33,20 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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#define __ARCH_ARM_INCLUDE_TIVA_CHIP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Get customizations for each supported chip */
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@ -125,7 +125,8 @@
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || defined(CONFIG_ARCH_CHIP_LM3S9B92)
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
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defined(CONFIG_ARCH_CHIP_LM3S9B92)
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# define LM3S 1 /* LM3S family */
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# undef LM4F /* Not LM4F family */
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# undef TM4C /* Not TM4C family */
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@ -199,7 +200,8 @@
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# define TIVA_NAES 0 /* No AES module */
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# define TIVA_NDES 0 /* No DES module */
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# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
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#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
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defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
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# undef LM3S /* Not LM3S family */
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# undef LM4F /* Not LM4F family */
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@ -411,11 +413,11 @@
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# error "Capabilities not specified for this TIVA/Stellaris chip"
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#endif
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/* The TIVA/Stellaris only supports 8 priority levels. The hardware priority
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* mechanism will only look at the upper N bits of the 8-bit priority level
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* (where N is 3 for the Tiva/Stellaris family), so any prioritization must be
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* performed in those bits. The default priority level is set to the middle
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* value
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/* The TIVA/Stellaris only supports 8 priority levels. The hardware
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* priority mechanism will only look at the upper N bits of the 8-bit
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* priority level (where N is 3 for the Tiva/Stellaris family), so any
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* prioritization must be performed in those bits. The default priority
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* level is set to the middle value
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in minimum priority */
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@ -423,13 +425,13 @@
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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@ -47,7 +47,7 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
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/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
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#if TIVA_NPORTS < 1
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# undef CONFIG_TIVA_GPIOA_IRQS
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@ -124,6 +124,10 @@
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#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#if defined(CONFIG_ARCH_CHIP_LM3S)
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# include <arch/tiva/lm3s_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_LM4F)
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@ -147,7 +151,7 @@
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_TIVA_IRQ_H */
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@ -533,7 +533,7 @@ extern "C"
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#endif
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/************************************************************************************
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* Public Functions
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* Public Function Prototypes
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************************************************************************************/
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#ifdef __cplusplus
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#endif
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/************************************************************************************
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* Public Functions
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* Public Function Prototypes
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************************************************************************************/
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#ifdef __cplusplus
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@ -1074,7 +1074,7 @@ extern "C"
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#endif
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/************************************************************************************
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* Public Functions
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* Public Function Prototypess
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************************************************************************************/
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#ifdef __cplusplus
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