More changes from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3431 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -57,39 +57,47 @@
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/* On-board crystal frequency is 8MHz (HSE) */
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_BOARD_XTAL 8000000ul
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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#define STM32_CFGR_USBPRE 0
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1 */
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#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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@ -99,16 +107,16 @@
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* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
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* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
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@ -116,9 +124,9 @@
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* LED definitions ******************************************************************/
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@ -503,6 +503,13 @@ CONFIG_PREALLOC_TIMERS=4
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CONFIG_FS_FAT=y
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CONFIG_FS_ROMFS=y
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#
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# I2C Settings
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#
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CONFIG_I2C_WRITEREAD=y
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CONFIG_I2C_TRANSFER=y
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CONFIG_I2C_SLAVE=n
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#
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# SPI-based MMC/SD driver
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#
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@ -858,3 +865,6 @@ CONFIG_HEAP_SIZE=
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# Application configuration
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CONFIG_APPS_DIR="../apps"
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# Provide /dev/ramX and then: mount -t binfs /dev/ram0 /bin
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CONFIG_APPS_BINDIR=y
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@ -80,3 +80,27 @@ int rtac_waitg(int group, int time)
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{
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// blocking variant of rtac_exec with timeout if specified
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}
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/** Power optimization of base systick timer
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*
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* 1. Simple method to skip wake-ups:
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* - ask timers about the min. period, which is Ns * systick
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* - set the preload register with floor(Ns) * DEFAULT_PRELOAD
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* - on wake-up call routines Ns times.
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*
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* 2. If intermediate ISR occuried then:
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* - check how many periods have passed by reading the counter: Np
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* - set the new counter value as (counter % DEFAULT_PRELOAD)
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* - call timer routines Np times; the next call is as usual, starting
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* at 1. point above
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*
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* This is okay if ISR's do not read timers, if they read timers then:
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* - on ISR wake-up the code described under 2. must be called first
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* (on wake-up from IDLE)
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*
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* BUT: the problem is that SYSTICK does not run in Stop mode but RTC
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* only, so it might be better to replace SYSTICK with RTAC (this
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* module) and do the job above, permitting ultra low power modes of
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* 25 uA or further down to 5 uA.
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*/
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@ -272,6 +272,25 @@ int sif_gpios_unlock(vsn_sif_state_t peripheral)
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}
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/****************************************************************************
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* ST LIS331DL
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****************************************************************************/
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void st_lis331dl_open(void)
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{
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}
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void st_lis331dl_config(void)
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{
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}
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void st_lis331dl_getreadings(void)
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{
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}
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/****************************************************************************
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* Analog Outputs
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****************************************************************************/
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