arch/sim: Change up_interrupt_context to inline function like arm
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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@ -30,6 +30,7 @@
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****************************************************************************/
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****************************************************************************/
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#include <arch/setjmp.h>
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#include <arch/setjmp.h>
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#include <sys/types.h>
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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# include <stdbool.h>
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#endif
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#endif
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@ -53,13 +54,6 @@ struct xcptcontext
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void *sigdeliver; /* Actual type is sig_deliver_t */
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void *sigdeliver; /* Actual type is sig_deliver_t */
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jmp_buf regs;
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jmp_buf regs;
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};
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};
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#ifdef __cplusplus
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#define EXTERN extern "C"
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#define EXTERN extern "C"
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@ -70,21 +64,25 @@ extern "C"
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#endif
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#endif
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/****************************************************************************
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/****************************************************************************
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* Inline functions
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* Public Data
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****************************************************************************/
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****************************************************************************/
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/* Return the current value of the stack pointer */
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/* g_current_regs[] holds a references to the current interrupt level
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* register storage structure. If is non-NULL only during interrupt
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* processing. Access to g_current_regs[] must be through the macro
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* CURRENT_REGS for portability.
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*/
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static inline uintptr_t up_getsp(void)
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/* For the case of architectures with multiple CPUs, then there must be one
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{
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* such value for each processor that can receive an interrupt.
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#ifdef _MSC_VER
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*/
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uintptr_t regval;
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__asm mov regval, esp;
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EXTERN volatile void *g_current_regs[CONFIG_SMP_NCPUS];
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return regval;
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#define CURRENT_REGS (g_current_regs[up_cpu_index()])
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#else
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return (uintptr_t)__builtin_frame_address(0);
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/****************************************************************************
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#endif
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* Public Function Prototypes
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}
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****************************************************************************/
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/****************************************************************************
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/****************************************************************************
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* Name: up_cpu_index
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* Name: up_cpu_index
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@ -120,6 +118,23 @@ int up_cpu_index(void);
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irqstate_t up_irq_save(void);
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irqstate_t up_irq_save(void);
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void up_irq_restore(irqstate_t flags);
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void up_irq_restore(irqstate_t flags);
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/* Return the current value of the stack pointer */
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static inline uintptr_t up_getsp(void)
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{
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#ifdef _MSC_VER
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uintptr_t regval;
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__asm mov regval, esp;
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return regval;
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#else
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return (uintptr_t)__builtin_frame_address(0);
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#endif
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}
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/****************************************************************************
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/****************************************************************************
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* Name: up_interrupt_context
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* Name: up_interrupt_context
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*
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*
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@ -129,7 +144,10 @@ void up_irq_restore(irqstate_t flags);
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*
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*
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****************************************************************************/
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****************************************************************************/
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bool up_interrupt_context(void);
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static inline bool up_interrupt_context(void)
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{
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return CURRENT_REGS != NULL;
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}
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#undef EXTERN
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#undef EXTERN
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -120,19 +120,6 @@ struct i2c_master_s;
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* Public Data
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* Public Data
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****************************************************************************/
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****************************************************************************/
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/* g_current_regs[] holds a references to the current interrupt level
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* register storage structure. If is non-NULL only during interrupt
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* processing. Access to g_current_regs[] must be through the macro
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* CURRENT_REGS for portability.
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*/
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/* For the case of architectures with multiple CPUs, then there must be one
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* such value for each processor that can receive an interrupt.
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*/
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extern volatile void *g_current_regs[CONFIG_SMP_NCPUS];
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#define CURRENT_REGS (g_current_regs[up_cpu_index()])
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/* The command line arguments passed to simulator */
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/* The command line arguments passed to simulator */
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extern int g_argc;
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extern int g_argc;
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@ -33,20 +33,6 @@
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* Public Functions
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* Public Functions
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****************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: up_interrupt_context
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*
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* Description:
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* Return true is we are currently executing in the interrupt handler
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* context.
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*
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****************************************************************************/
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bool up_interrupt_context(void)
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{
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return CURRENT_REGS != NULL;
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}
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/****************************************************************************
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/****************************************************************************
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* Name: sim_doirq
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* Name: sim_doirq
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****************************************************************************/
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****************************************************************************/
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