Fixes to get USB working on STM32 F3
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5638 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
57be52caf1
commit
19fcd020d7
@ -56,263 +56,268 @@
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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/* Select USART parameters for the selected console */
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#if defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32_CONSOLE_TX GPIO_USART1_TX
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# define STM32_CONSOLE_RX GPIO_USART1_RX
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# ifdef CONFIG_USART1_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
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# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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#ifdef HAVE_CONSOLE
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# if defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32_CONSOLE_TX GPIO_USART1_TX
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# define STM32_CONSOLE_RX GPIO_USART1_RX
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# ifdef CONFIG_USART1_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
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# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32_CONSOLE_TX GPIO_USART2_TX
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# define STM32_CONSOLE_RX GPIO_USART2_RX
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# ifdef CONFIG_USART2_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
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# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART3_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
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# define STM32_CONSOLE_TX GPIO_USART3_TX
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# define STM32_CONSOLE_RX GPIO_USART3_RX
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# ifdef CONFIG_USART3_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
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# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART4_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
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# define STM32_CONSOLE_TX GPIO_UART4_TX
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# define STM32_CONSOLE_RX GPIO_UART4_RX
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# ifdef CONFIG_UART4_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
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# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART5_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
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# define STM32_CONSOLE_TX GPIO_UART5_TX
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# define STM32_CONSOLE_RX GPIO_UART5_RX
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# ifdef CONFIG_UART5_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
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# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART6_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
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# define STM32_CONSOLE_TX GPIO_USART6_TX
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# define STM32_CONSOLE_RX GPIO_USART6_RX
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# ifdef CONFIG_USART6_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
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# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# endif
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32_CONSOLE_TX GPIO_USART2_TX
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# define STM32_CONSOLE_RX GPIO_USART2_RX
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# ifdef CONFIG_USART2_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
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# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART3_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
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# define STM32_CONSOLE_TX GPIO_USART3_TX
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# define STM32_CONSOLE_RX GPIO_USART3_RX
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# ifdef CONFIG_USART3_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
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# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART4_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
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# define STM32_CONSOLE_TX GPIO_UART4_TX
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# define STM32_CONSOLE_RX GPIO_UART4_RX
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# ifdef CONFIG_UART4_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
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# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART5_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
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# define STM32_CONSOLE_TX GPIO_UART5_TX
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# define STM32_CONSOLE_RX GPIO_UART5_RX
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# ifdef CONFIG_UART5_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
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# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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#elif defined(CONFIG_USART6_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART6_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
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# define STM32_CONSOLE_TX GPIO_USART6_TX
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# define STM32_CONSOLE_RX GPIO_USART6_RX
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# ifdef CONFIG_USART6_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
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# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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#endif
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/* CR1 settings */
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/* CR1 settings */
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#if STM32_CONSOLE_BITS == 9
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# define USART_CR1_M_VALUE USART_CR1_M
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#else
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# define USART_CR1_M_VALUE 0
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#endif
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#if STM32_CONSOLE_PARITY == 1
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# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
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#elif STM32_CONSOLE_PARITY == 2
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# define USART_CR1_PARITY_VALUE USART_CR1_PCE
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#else
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# define USART_CR1_PARITY_VALUE 0
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#endif
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#ifdef CONFIG_STM32_STM32F30XX
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# define USART_CR1_CLRBITS\
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(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS |\
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USART_CR1_PCE |USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME |\
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USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK |\
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USART_CR1_ALLINTS)
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#else
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# define USART_CR1_CLRBITS\
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(USART_CR1_M | USART_CR1_PCE |USART_CR1_PS | USART_CR1_TE |\
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USART_CR1_RE | USART_CR1_ALLINTS)
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#endif
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#define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
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/* CR2 settings */
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#if STM32_CONSOLE_2STOP != 0
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# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
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#else
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# define USART_CR2_STOP2_VALUE 0
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#endif
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#ifdef CONFIG_STM32_STM32F30XX
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# define USART_CR2_CLRBITS \
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(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\
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USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\
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USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV |\
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USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK |\
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USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
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#else
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# define USART_CR2_CLRBITS \
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(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|\
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USART_CR2_LBCL|USART_CR2_LBDIE)
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#endif
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#define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
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/* CR3 settings */
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#ifdef CONFIG_STM32_STM32F30XX
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# define USART_CR3_CLRBITS \
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(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\
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USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT |\
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USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT |\
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USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP |\
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USART_CR1_SCARCNT_MASK | USART_CR1_WUS_MASK | USART_CR1_WUFIE)
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#else
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# define USART_CR3_CLRBITS \
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(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
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#endif
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#define USART_CR3_SETBITS 0
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/* Only the STM32 F3 supports oversampling by 8 */
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#undef USE_OVER8
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/* Calculate USART BAUD rate divider */
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#ifdef CONFIG_STM32_STM32F30XX
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/* Baud rate for standard USART (SPI mode included):
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*
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* In case of oversampling by 16, the equation is:
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* baud = fCK / UARTDIV
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* UARTDIV = fCK / baud
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*
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* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / UARTDIV
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* UARTDIV = 2 * fCK / baud
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*/
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# define STM32_USARTDIV8 \
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(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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# define STM32_USARTDIV16 \
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((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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/* Use oversamply by 8 only if the divisor is small. But what is small? */
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# if STM32_USARTDIV8 > 100
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# define STM32_BRR_VALUE STM32_USARTDIV16
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# if STM32_CONSOLE_BITS == 9
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# define USART_CR1_M_VALUE USART_CR1_M
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# else
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# define USE_OVER8 1
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# define STM32_BRR_VALUE \
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((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
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# define USART_CR1_M_VALUE 0
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# endif
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#else
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# if STM32_CONSOLE_PARITY == 1
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# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
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# elif STM32_CONSOLE_PARITY == 2
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# define USART_CR1_PARITY_VALUE USART_CR1_PCE
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# else
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# define USART_CR1_PARITY_VALUE 0
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# endif
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/* The baud rate for the receiver and transmitter (Rx and Tx) are both set
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* to the same value as programmed in the Mantissa and Fraction values of
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* USARTDIV.
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*
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* baud = fCK / (16 * usartdiv)
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* usartdiv = fCK / (16 * baud)
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*
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* Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4,
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* 5 or PCLK2 for USART1). Example, fCK=72MHz baud=115200,
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* usartdiv=39.0625=39 1/16th;
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*
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* First calculate:
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*
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* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
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*
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* (NOTE: all standard baud values are even so dividing by two does not
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* lose precision). Eg. (same fCK and buad), usartdiv32 = 1250
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*/
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# ifdef CONFIG_STM32_STM32F30XX
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# define USART_CR1_CLRBITS\
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(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS |\
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USART_CR1_PCE |USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME |\
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USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK |\
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USART_CR1_ALLINTS)
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# else
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# define USART_CR1_CLRBITS\
|
||||
(USART_CR1_M | USART_CR1_PCE |USART_CR1_PS | USART_CR1_TE |\
|
||||
USART_CR1_RE | USART_CR1_ALLINTS)
|
||||
# endif
|
||||
|
||||
# define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
|
||||
# define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
|
||||
|
||||
/* The mantissa is then usartdiv32 / 32:
|
||||
*
|
||||
* mantissa = usartdiv32 / 32/
|
||||
*
|
||||
* Eg. usartdiv32=1250, mantissa = 39
|
||||
*/
|
||||
/* CR2 settings */
|
||||
|
||||
# define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
# endif
|
||||
|
||||
/* And the fraction:
|
||||
*
|
||||
* fraction = (usartdiv32 - mantissa*32 + 1) / 2
|
||||
*
|
||||
* Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
|
||||
*/
|
||||
# ifdef CONFIG_STM32_STM32F30XX
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\
|
||||
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\
|
||||
USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV |\
|
||||
USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK |\
|
||||
USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
|
||||
# else
|
||||
# define USART_CR2_CLRBITS \
|
||||
(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|\
|
||||
USART_CR2_LBCL|USART_CR2_LBDIE)
|
||||
# endif
|
||||
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
|
||||
|
||||
# define STM32_FRACTION \
|
||||
((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
|
||||
/* CR3 settings */
|
||||
|
||||
/* And, finally, the BRR value is: */
|
||||
# ifdef CONFIG_STM32_STM32F30XX
|
||||
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | \
|
||||
(STM32_FRACTION << USART_BRR_FRAC_SHIFT))
|
||||
#endif
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\
|
||||
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT |\
|
||||
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT |\
|
||||
USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP |\
|
||||
USART_CR1_SCARCNT_MASK | USART_CR1_WUS_MASK | USART_CR1_WUFIE)
|
||||
# else
|
||||
# define USART_CR3_CLRBITS \
|
||||
(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
|
||||
# endif
|
||||
# define USART_CR3_SETBITS 0
|
||||
|
||||
/* Only the STM32 F3 supports oversampling by 8 */
|
||||
|
||||
# undef USE_OVER8
|
||||
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
# ifdef CONFIG_STM32_STM32F30XX
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
|
||||
# else /* CONFIG_STM32_STM32F30XX */
|
||||
|
||||
/* The baud rate for the receiver and transmitter (Rx and Tx) are both set
|
||||
* to the same value as programmed in the Mantissa and Fraction values of
|
||||
* USARTDIV.
|
||||
*
|
||||
* baud = fCK / (16 * usartdiv)
|
||||
* usartdiv = fCK / (16 * baud)
|
||||
*
|
||||
* Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4,
|
||||
* 5 or PCLK2 for USART1). Example, fCK=72MHz baud=115200,
|
||||
* usartdiv=39.0625=39 1/16th;
|
||||
*
|
||||
* First calculate:
|
||||
*
|
||||
* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
|
||||
*
|
||||
* (NOTE: all standard baud values are even so dividing by two does not
|
||||
* lose precision). Eg. (same fCK and buad), usartdiv32 = 1250
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
|
||||
|
||||
/* The mantissa is then usartdiv32 / 32:
|
||||
*
|
||||
* mantissa = usartdiv32 / 32/
|
||||
*
|
||||
* Eg. usartdiv32=1250, mantissa = 39
|
||||
*/
|
||||
|
||||
# define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
|
||||
|
||||
/* And the fraction:
|
||||
*
|
||||
* fraction = (usartdiv32 - mantissa*32 + 1) / 2
|
||||
*
|
||||
* Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
|
||||
*/
|
||||
|
||||
# define STM32_FRACTION \
|
||||
((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
|
||||
|
||||
/* And, finally, the BRR value is: */
|
||||
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | \
|
||||
(STM32_FRACTION << USART_BRR_FRAC_SHIFT))
|
||||
|
||||
# endif /* CONFIG_STM32_STM32F30XX */
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
@ -365,7 +370,7 @@ void up_lowputc(char ch)
|
||||
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif /* HAVE_CONSOLE */
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
@ -503,7 +508,8 @@ void stm32_lowsetup(void)
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
@ -573,7 +579,8 @@ void stm32_lowsetup(void)
|
||||
|
||||
cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
|
||||
@ -84,13 +84,13 @@
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
# ifdef CONFIG_STM32_USB_ITRMP
|
||||
# define STM32_IRQ_USBHP STM32_IRQ_USBHP_1
|
||||
# define STM32_IRQ_USBLP STM32_IRQ_USBLP_1
|
||||
# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_1
|
||||
# else
|
||||
# define STM32_IRQ_USBHP STM32_IRQ_USBHP_2
|
||||
# define STM32_IRQ_USBLP STM32_IRQ_USBLP_2
|
||||
# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_2
|
||||
# else
|
||||
# define STM32_IRQ_USBHP STM32_IRQ_USBHP_1
|
||||
# define STM32_IRQ_USBLP STM32_IRQ_USBLP_1
|
||||
# define STM32_IRQ_USBWKUP STM32_IRQ_USBWKUP_1
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
@ -776,11 +776,20 @@ Where <subdir> is one of the following:
|
||||
sercon : Connect the serial device a create /dev/ttyACM0
|
||||
serdis : Disconnect the serial device.
|
||||
|
||||
NOTE: I don't expect there serial connections/disconnections to work
|
||||
well. the STM32F3Discovery board does not provide circuitry for
|
||||
control for the "soft connect" USB pullup. As a result, the host PC
|
||||
may not know when the USB has been logically connected or disconnected
|
||||
and may not re-enumerate the device.
|
||||
NOTE: The serial connections/disconnections do not work as advertised.
|
||||
This is because the STM32F3Discovery board does not provide circuitry for
|
||||
control of the "soft connect" USB pullup. As a result, the host PC
|
||||
does not know the USB has been logically connected or disconnected. You
|
||||
have to follow these steps to use USB:
|
||||
|
||||
1) Start NSH with USB disconnected
|
||||
2) enter to 'sercon' command to start the CDC/ACM device, then
|
||||
3) Connect the USB device to the host.
|
||||
|
||||
and to close the connection:
|
||||
|
||||
4) Disconnect the USB device from the host
|
||||
5) Enter the 'serdis' command
|
||||
|
||||
4. This example can support the watchdog timer test (apps/examples/watchdog)
|
||||
but this must be enabled by selecting:
|
||||
@ -807,6 +816,9 @@ Where <subdir> is one of the following:
|
||||
Such a configuration is useful on the stm32f3discovery which has no
|
||||
builtin RS-232 drivers.
|
||||
|
||||
Status: As of this writing, this configuration has not ran properly.
|
||||
There appears to be some kind of driver-related issue.
|
||||
|
||||
NOTES:
|
||||
|
||||
1. This configuration uses the mconf-based configuration tool. To
|
||||
@ -858,6 +870,14 @@ Where <subdir> is one of the following:
|
||||
CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
|
||||
CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
|
||||
|
||||
5. The STM32F3Discovery board does not provide circuitry for control of
|
||||
the "soft connect" USB pullup. As a result, the host PC does not know
|
||||
the USB has been logically connected or disconnected. You have to
|
||||
follow these steps to use USB:
|
||||
|
||||
1) Start NSH with USB disconnected, then
|
||||
2) Connect the USB device to the host.
|
||||
|
||||
5. By default, this project assumes that you are *NOT* using the DFU
|
||||
bootloader.
|
||||
|
||||
|
||||
@ -213,6 +213,11 @@ CONFIG_STM32_USART=y
|
||||
# USB Host Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# USB Device Configuration
|
||||
#
|
||||
# CONFIG_STM32_USB_ITRMP is not set
|
||||
|
||||
#
|
||||
# External Memory Configuration
|
||||
#
|
||||
|
||||
Loading…
Reference in New Issue
Block a user