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arm/xtensa:cache: flush/clean dcache all if size large than cache size

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For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit is contained in:
zhuyanlin 2022-01-13 21:02:22 +08:00 committed by Xiang Xiao
parent 4d5c2586a9
commit 1b08f607be
3 changed files with 50 additions and 0 deletions
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20
arch/arm/src/armv7-m/arm_cache.c
View File

@ -536,15 +536,25 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Clean the D-Cache over the range of addresses */
ssize = (1 << sshift);
if ((end - start) >= ssize * (sets + 1) * (ways + 1))
{
return up_clean_dcache_all();
}
start &= ~(ssize - 1);
ARM_DSB();
@ -679,15 +689,25 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Clean and invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
if ((end - start) >= ssize * (sets + 1) * (ways + 1))
{
return up_flush_dcache_all();
}
start &= ~(ssize - 1);
ARM_DSB();

20
arch/arm/src/armv8-m/arm_cache.c
View File

@ -536,15 +536,25 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Clean the D-Cache over the range of addresses */
ssize = (1 << sshift);
if ((end - start) >= ssize * (sets + 1) * (ways + 1))
{
return up_clean_dcache_all();
}
start &= ~(ssize - 1);
ARM_DSB();
@ -679,15 +689,25 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
uint32_t ccsidr;
uint32_t sshift;
uint32_t ssize;
uint32_t sets;
uint32_t ways;
/* Get the characteristics of the D-Cache */
ccsidr = getreg32(NVIC_CCSIDR);
sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
sets = CCSIDR_SETS(ccsidr); /* (Number of sets) - 1 */
ways = CCSIDR_WAYS(ccsidr); /* (Number of ways) - 1 */
/* Clean and invalidate the D-Cache over the range of addresses */
ssize = (1 << sshift);
if ((end - start) >= ssize * (sets + 1) * (ways + 1))
{
return up_flush_dcache_all();
}
start &= ~(ssize - 1);
ARM_DSB();

10
arch/xtensa/src/common/xtensa_cache.c
View File

@ -418,6 +418,11 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
start &= ~(XCHAL_DCACHE_LINESIZE - 1);
if ((end - start) >= XCHAL_DCACHE_SIZE)
{
return up_clean_dcache_all();
}
for (; start < end; start += XCHAL_DCACHE_LINESIZE)
{
__asm__ __volatile__ ("dhwb %0, 0\n" : : "r"(start));
@ -495,6 +500,11 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
start &= ~(XCHAL_DCACHE_LINESIZE - 1);
if ((end - start) >= XCHAL_DCACHE_SIZE)
{
return up_clean_dcache_all();
}
for (; start < end; start += XCHAL_DCACHE_LINESIZE)
{
__asm__ __volatile__ ("dhwbi %0, 0\n" : : "r"(start));