Make filter register accessible for CAN1 and CAN2. Provided by Lorenz Meier
This commit is contained in:
Gregory Nutt
parent
363df90d81
commit
1b17b8fbea
@ -2586,21 +2586,6 @@ config SDIO_WIDTH_D1_ONLY
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endmenu
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menu "CAN Configuration"
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depends on STM32_CAN
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config CAN1_BAUD
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int "Baud rate for CAN1"
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default 250000
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depends on STM32_CAN1
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config CAN2_BAUD
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int "Baud rate for CAN2"
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default 250000
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depends on STM32_CAN2
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endmenu
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if STM32_ETHMAC
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menu "Ethernet MAC configuration"
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@ -2882,3 +2867,22 @@ config STM32_USB_ITRMP
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either retain the legacy F1 behavior or to map the USB interupts to
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there own dedicated vectors. The option is available only for the
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F3 family and selects the use of the dedicated USB interrupts.
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menu "CAN driver configuration"
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depends on STM32_CAN1 || STM32_CAN2
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config CAN1_BAUD
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int "CAN1 BAUD"
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default 250000
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depends on STM32_CAN1
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---help---
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CAN1 BAUD rate. Required if STM32_CAN1 is defined.
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config CAN2_BAUD
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int "CAN2 BAUD"
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default 250000
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depends on STM32_CAN2
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---help---
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CAN2 BAUD rate. Required if STM32_CAN2 is defined.
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endmenu
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@ -107,7 +107,8 @@ struct stm32_can_s
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uint8_t canrx0; /* CAN RX FIFO 0 IRQ number */
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uint8_t cantx; /* CAN TX IRQ number */
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uint8_t filter; /* Filter number */
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uint32_t base; /* Base address of the CAN registers */
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uint32_t base; /* Base address of the CAN control registers */
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uint32_t fbase; /* Base address of the CAN filter registers */
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uint32_t baud; /* Configured baud */
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};
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@ -118,7 +119,9 @@ struct stm32_can_s
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/* CAN Register access */
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset);
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset);
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value);
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value);
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_dumpctrlregs(struct stm32_can_s *priv, FAR const char *msg);
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static void can_dumpmbregs(struct stm32_can_s *priv, FAR const char *msg);
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@ -179,6 +182,7 @@ static struct stm32_can_s g_can1priv =
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.cantx = STM32_IRQ_CAN1TX,
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.filter = 0,
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.base = STM32_CAN1_BASE,
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.fbase = STM32_CAN1_BASE,
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.baud = CONFIG_CAN1_BAUD,
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};
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@ -197,6 +201,7 @@ static struct stm32_can_s g_can2priv =
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.cantx = STM32_IRQ_CAN2TX,
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.filter = CAN_NFILTERS / 2,
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.base = STM32_CAN2_BASE,
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.fbase = STM32_CAN1_BASE,
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.baud = CONFIG_CAN2_BAUD,
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};
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@ -213,9 +218,10 @@ static struct can_dev_s g_can2dev =
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/****************************************************************************
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* Name: can_getreg
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* Name: can_getfreg
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*
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* Description:
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* Read the value of an CAN register.
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* Read the value of a CAN register or filter block register.
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*
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* Input Parameters:
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* priv - A reference to the CAN block status
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@ -226,12 +232,11 @@ static struct can_dev_s g_can2dev =
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****************************************************************************/
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#ifdef CONFIG_CAN_REGDEBUG
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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static uint32_t can_vgetreg(uint32_t addr)
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{
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static uint32_t prevaddr = 0;
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static uint32_t preval = 0;
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static uint32_t count = 0;
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uint32_t addr = priv->base + offset;
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/* Read the value from the register */
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@ -278,18 +283,36 @@ static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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lldbg("%08x->%08x\n", addr, val);
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return val;
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}
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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{
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return can_vgetreg(priv->base + offset);
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}
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset)
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{
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return can_vgetreg(priv->fbase + offset);
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}
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#else
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static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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{
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return getreg32(priv->base + offset);
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}
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static uint32_t can_getfreg(struct stm32_can_s *priv, int offset)
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{
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return getreg32(priv->fbase + offset);
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}
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#endif
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/****************************************************************************
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* Name: can_putreg
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* Name: can_putfreg
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*
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* Description:
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* Set the value of an CAN register.
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* Set the value of a CAN register or filter block register.
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*
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* Input Parameters:
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* priv - A reference to the CAN block status
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@ -302,9 +325,8 @@ static uint32_t can_getreg(struct stm32_can_s *priv, int offset)
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****************************************************************************/
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#ifdef CONFIG_CAN_REGDEBUG
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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static void can_vputreg(uint32_t addr, uint32_t value)
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{
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uint32_t addr = priv->base + offset;
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/* Show the register value being written */
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@ -314,11 +336,27 @@ static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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putreg32(value, addr);
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}
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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{
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can_vputreg(priv->base + offset, value);
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}
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value)
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{
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can_vputreg(priv->fbase + offset, value);
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}
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#else
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static void can_putreg(struct stm32_can_s *priv, int offset, uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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static void can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value)
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{
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putreg32(value, priv->fbase + offset);
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}
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#endif
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/****************************************************************************
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@ -346,7 +384,7 @@ static void can_dumpctrlregs(struct stm32_can_s *priv, FAR const char *msg)
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{
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canlldbg("Control Registers:\n");
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}
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/* CAN control and status registers */
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lldbg(" MCR: %08x MSR: %08x TSR: %08x\n",
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@ -495,14 +533,14 @@ static void can_reset(FAR struct can_dev_s *dev)
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/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
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#ifdef CONFIG_STM32_CAN1
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#ifdef CONFIG_STM32_CAN1
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if (priv->port == 1)
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{
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regbit = RCC_APB1RSTR_CAN1RST;
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}
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else
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#endif
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#ifdef CONFIG_STM32_CAN2
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#ifdef CONFIG_STM32_CAN2
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if (priv->port == 2)
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{
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regbit = RCC_APB1RSTR_CAN2RST;
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@ -1153,7 +1191,7 @@ static int can_txinterrupt(int irq, void *context)
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if ((regval & CAN_TSR_TXOK0) != 0)
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{
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/* Tell the upper half that the tansfer is finished. */
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(void)can_txdone(dev);
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}
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}
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@ -1173,7 +1211,7 @@ static int can_txinterrupt(int irq, void *context)
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if ((regval & CAN_TSR_TXOK1) != 0)
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{
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/* Tell the upper half that the tansfer is finished. */
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(void)can_txdone(dev);
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}
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}
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@ -1193,7 +1231,7 @@ static int can_txinterrupt(int irq, void *context)
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if ((regval & CAN_TSR_TXOK2) != 0)
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{
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/* Tell the upper half that the tansfer is finished. */
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(void)can_txdone(dev);
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}
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}
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@ -1313,7 +1351,7 @@ static int can_bittiming(struct stm32_can_s *priv)
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if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX)
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{
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ts1--;
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ts2++;
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ts2++;
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}
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}
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@ -1427,7 +1465,7 @@ static int can_cellinit(struct stm32_can_s *priv)
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can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
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/* Configure bit timing. */
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ret = can_bittiming(priv);
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if (ret < 0)
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{
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@ -1477,7 +1515,7 @@ static int can_cellinit(struct stm32_can_s *priv)
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* Filters can also be configured as:
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*
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* 3. 16- or 32-bit. The advantage of 16-bit filters is that you get
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* more filters; The advantage of 32-bit filters is that you get
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* more filters; The advantage of 32-bit filters is that you get
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* finer control of the filtering.
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*
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* One filter is set up for each CAN. The filter resources are shared
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@ -1510,52 +1548,52 @@ static int can_filterinit(struct stm32_can_s *priv)
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/* Enter filter initialization mode */
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regval = can_getreg(priv, STM32_CAN_FMR_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
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regval |= CAN_FMR_FINIT;
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can_putreg(priv, STM32_CAN_FMR_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
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/* Disable the filter */
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regval = can_getreg(priv, STM32_CAN_FA1R_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
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regval &= ~bitmask;
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can_putreg(priv, STM32_CAN_FA1R_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
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/* Select the 32-bit scale for the filter */
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regval = can_getreg(priv, STM32_CAN_FS1R_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FS1R_OFFSET);
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regval |= bitmask;
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can_putreg(priv, STM32_CAN_FS1R_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval);
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/* There are 14 or 28 filter banks (depending) on the device. Each filter bank is
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* composed of two 32-bit registers, CAN_FiR:
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*/
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can_putreg(priv, STM32_CAN_FR_OFFSET(priv->filter, 1), 0);
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can_putreg(priv, STM32_CAN_FR_OFFSET(priv->filter, 2), 0);
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can_putfreg(priv, STM32_CAN_FR_OFFSET(priv->filter, 1), 0);
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can_putfreg(priv, STM32_CAN_FR_OFFSET(priv->filter, 2), 0);
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/* Set Id/Mask mode for the filter */
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regval = can_getreg(priv, STM32_CAN_FM1R_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FM1R_OFFSET);
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regval &= ~bitmask;
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can_putreg(priv, STM32_CAN_FM1R_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval);
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/* Assign FIFO 0 for the filter */
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regval = can_getreg(priv, STM32_CAN_FFA1R_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FFA1R_OFFSET);
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regval &= ~bitmask;
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can_putreg(priv, STM32_CAN_FFA1R_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval);
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/* Enable the filter */
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regval = can_getreg(priv, STM32_CAN_FA1R_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
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regval |= bitmask;
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can_putreg(priv, STM32_CAN_FA1R_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
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/* Exit filter initialization mode */
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regval = can_getreg(priv, STM32_CAN_FMR_OFFSET);
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regval = can_getfreg(priv, STM32_CAN_FMR_OFFSET);
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regval &= ~CAN_FMR_FINIT;
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can_putreg(priv, STM32_CAN_FMR_OFFSET, regval);
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can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
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return OK;
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}
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@ -1587,7 +1625,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
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* by stm32_clockconfig() early in the reset sequence.
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*/
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#ifdef CONFIG_STM32_CAN1
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#ifdef CONFIG_STM32_CAN1
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if( port == 1 )
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{
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/* Select the CAN1 device structure */
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@ -1602,8 +1640,8 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
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stm32_configgpio(GPIO_CAN1_TX);
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}
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else
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#endif
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#ifdef CONFIG_STM32_CAN2
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#endif
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#ifdef CONFIG_STM32_CAN2
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if ( port ==2 )
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{
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/* Select the CAN2 device structure */
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@ -1618,7 +1656,7 @@ FAR struct can_dev_s *stm32_caninitialize(int port)
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stm32_configgpio(GPIO_CAN2_TX);
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}
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else
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#endif
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#endif
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{
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candbg("ERROR: Unsupported port %d\n", port);
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return NULL;
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