Merge remote-tracking branch 'origin/master' into ieee802154
This commit is contained in:
Gregory Nutt
commit
1b3cb3752a
@ -64,12 +64,16 @@
|
||||
* STM32L15XCX -- 48-pins
|
||||
* STM32L15XRX -- 64-pins
|
||||
* STM32L15XVX -- 100-pins
|
||||
* STM32L15XZX -- 144-pins
|
||||
*
|
||||
* STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
|
||||
* STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
|
||||
* STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
|
||||
*
|
||||
* STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
|
||||
*
|
||||
* STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density)
|
||||
* STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density)
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
|
||||
@ -320,7 +324,7 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
|
||||
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
|
||||
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
|
||||
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
|
||||
* and STM32L15xxx */
|
||||
@ -331,6 +335,7 @@
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
|
||||
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 0 /* No FSMC */
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
@ -358,17 +363,18 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
|
||||
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
|
||||
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite vamily */
|
||||
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
|
||||
* and STM32L15xxx */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes, STM32L16x w/ 48/384 Kbytes. */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32L16xD w/ 48/384 Kbytes. */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
|
||||
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 1 /* FSMC */
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
@ -395,6 +401,48 @@
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32L162VE)
|
||||
# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
|
||||
# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
|
||||
* and STM32L15xxx */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32L16xE w/ 80/512 Kbytes. */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
|
||||
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 0 /* No FSMC */
|
||||
# define STM32_NATIM 0 /* No advanced timers */
|
||||
# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA
|
||||
* 32-bit general timer TIM5 with DMA */
|
||||
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
|
||||
# define STM32_NDMA 2 /* DMA1, 12-channels */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
|
||||
# define STM32_NUSART 5 /* USART1-3, UART4-5 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
|
||||
# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
|
||||
# define STM32_NGPIO 83 /* GPIOA-G,H */
|
||||
|
||||
# define STM32_NADC 1 /* ADC1, up to 40-channels (medium+ and high density). See for more information RM0038 Reference manual */
|
||||
# define STM32_NDAC 1 /* DAC 1, 2 channels. See for more information RM0038 Reference manual */
|
||||
/* (2) Comparators */
|
||||
# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No ethernet */
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
|
||||
/* STM32 F100 Value Line ************************************************************/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
|
||||
@ -562,7 +610,7 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
|
||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
@ -1129,7 +1177,7 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8)
|
||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
@ -1668,7 +1716,7 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC)
|
||||
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
|
||||
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
|
||||
@ -634,8 +634,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
|
||||
* Name: stm32_iwdginitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the IWDG watchdog time. The watchdog timer is initialized and
|
||||
* registers as 'devpath. The initial state of the watchdog time is
|
||||
* Initialize the IWDG watchdog timer. The watchdog timer is initialized and
|
||||
* registers as 'devpath'. The initial state of the watchdog timer is
|
||||
* disabled.
|
||||
*
|
||||
* Input Parameters:
|
||||
@ -665,7 +665,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
|
||||
priv->started = false;
|
||||
|
||||
/* Make sure that the LSI oscillator is enabled. NOTE: The LSI oscillator
|
||||
* is enabled here but is not disabled by this file (because this file does
|
||||
* is enabled here but is not disabled by this file, because this file does
|
||||
* not know the global usage of the oscillator. Any clock management
|
||||
* logic (say, as part of a power management scheme) needs handle other
|
||||
* LSI controls outside of this file.
|
||||
@ -685,9 +685,9 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
|
||||
|
||||
(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
|
||||
|
||||
/* When the microcontroller enters debug mode (Cortex™-M4F core halted),
|
||||
/* When the microcontroller enters debug mode (Cortex-M4F core halted),
|
||||
* the IWDG counter either continues to work normally or stops, depending
|
||||
* on DBG_WIDG_STOP configuration bit in DBG module.
|
||||
* on DBG_IWDG_STOP configuration bit in DBG module.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
|
||||
@ -695,7 +695,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
|
||||
defined(CONFIG_STM32_JTAG_SW_ENABLE)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX)
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
|
||||
cr |= DBGMCU_APB1_IWDGSTOP;
|
||||
putreg32(cr, STM32_DBGMCU_APB1_FZ);
|
||||
|
||||
@ -734,8 +734,8 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
|
||||
* Name: stm32_wwdginitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the WWDG watchdog time. The watchdog timer is initialized and
|
||||
* registers as 'devpath. The initial state of the watchdog time is
|
||||
* Initialize the WWDG watchdog timer. The watchdog timer is initialized and
|
||||
* registers as 'devpath'. The initial state of the watchdog timer is
|
||||
* disabled.
|
||||
*
|
||||
* Input Parameters:
|
||||
@ -753,7 +753,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
|
||||
|
||||
wdinfo("Entry: devpath=%s\n", devpath);
|
||||
|
||||
/* NOTE we assume that clocking to the IWDG has already been provided by
|
||||
/* NOTE we assume that clocking to the WWDG has already been provided by
|
||||
* the RCC initialization logic.
|
||||
*/
|
||||
|
||||
@ -780,7 +780,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
|
||||
|
||||
(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
|
||||
|
||||
/* When the microcontroller enters debug mode (Cortex<EFBFBD>-M4F core halted),
|
||||
/* When the microcontroller enters debug mode (Cortex-M core halted),
|
||||
* the WWDG counter either continues to work normally or stops, depending
|
||||
* on DBG_WWDG_STOP configuration bit in DBG module.
|
||||
*/
|
||||
@ -790,7 +790,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
|
||||
defined(CONFIG_STM32_JTAG_SW_ENABLE)
|
||||
{
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX)
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
|
||||
cr |= DBGMCU_APB1_WWDGSTOP;
|
||||
putreg32(cr, STM32_DBGMCU_APB1_FZ);
|
||||
|
||||
@ -75,12 +75,41 @@ config SENSOR_KXTJ9_I2C_BUS_SPEED
|
||||
|
||||
endif # SENSOR_KXTJ9
|
||||
|
||||
config LIS2DH
|
||||
bool "STMicro LIS2DH device support"
|
||||
default n
|
||||
select I2C
|
||||
---help---
|
||||
Enable driver support for the STMicro LIS2DH accelerometer
|
||||
|
||||
if LIS2DH
|
||||
|
||||
config DEBUG_LIS2DH
|
||||
bool "Debug support for the LIS2DH"
|
||||
default n
|
||||
---help---
|
||||
Enables debug features for the LIS2DH
|
||||
|
||||
config LIS2DH_NPOLLWAITERS
|
||||
int "Number of waiters to poll"
|
||||
default 2
|
||||
---help---
|
||||
Maximum number of threads that can be waiting on poll()
|
||||
|
||||
config LIS2DH_DRIVER_SELFTEST
|
||||
bool "Enable selftest in LIS2DH driver"
|
||||
default n
|
||||
---help---
|
||||
Enable selftest in LIS2DH driver
|
||||
|
||||
endif # LIS2DH
|
||||
|
||||
config LIS3DSH
|
||||
bool "STMicro LIS3DSH 3-Axis acclerometer support"
|
||||
bool "STMicro LIS3DSH 3-Axis accelerometer support"
|
||||
default n
|
||||
select SPI
|
||||
---help---
|
||||
Enable driver support for the STMicro LIS3DSH 3-Axis acclerometer.
|
||||
Enable driver support for the STMicro LIS3DSH 3-Axis accelerometer.
|
||||
|
||||
config LIS331DL
|
||||
bool "STMicro LIS331DL device support"
|
||||
|
||||
@ -53,6 +53,10 @@ ifeq ($(CONFIG_SENSOR_KXTJ9),y)
|
||||
CSRCS += kxtj9.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIS2DH),y)
|
||||
CSRCS += lis2dh.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIS3DSH),y)
|
||||
CSRCS += lis3dsh.c
|
||||
endif
|
||||
|
||||
2033
drivers/sensors/lis2dh.c
Normal file
2033
drivers/sensors/lis2dh.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -133,4 +133,14 @@
|
||||
#define SNIOC_PRESSURE_OUT _SNIOC(0x0034)
|
||||
#define SNIOC_SENSOR_OFF _SNIOC(0x0035)
|
||||
|
||||
/* IOCTL commands unique to the LIS2DH */
|
||||
|
||||
#define SNIOC_WRITESETUP _SNIOC(0x0036) /* Arg: uint8_t value */
|
||||
#define SNIOC_WRITE_INT1THRESHOLD _SNIOC(0x0037) /* Arg: uint8_t value */
|
||||
#define SNIOC_WRITE_INT2THRESHOLD _SNIOC(0x0038) /* Arg: uint8_t value */
|
||||
#define SNIOC_RESET_HPFILTER _SNIOC(0x0039) /* Arg: uint8_t value */
|
||||
#define SNIOC_START_SELFTEST _SNIOC(0x003a) /* Arg: uint8_t value */
|
||||
#define SNIOC_WHO_AM_I _SNIOC(0x003b)
|
||||
#define SNIOC_READ_TEMP _SNIOC(0x003c) /* Arg: int16_t value */
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_SENSORS_IOCTL_H */
|
||||
|
||||
441
include/nuttx/sensors/lis2dh.h
Normal file
441
include/nuttx/sensors/lis2dh.h
Normal file
@ -0,0 +1,441 @@
|
||||
/****************************************************************************
|
||||
* include/nuttx/sensors/lis2dh.h
|
||||
* LIS2DH accelerometer driver
|
||||
*
|
||||
* Copyright (C) 2014-2017 Haltian Ltd. All rights reserved.
|
||||
* Authors: Timo Voutilainen <timo.voutilainen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __INCLUDE_NUTTX_SENSORS_LIS2DH_H
|
||||
#define __INCLUDE_NUTTX_SENSORS_LIS2DH_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/sensors/ioctl.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Declarations
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#define ST_LIS2DH_WHOAMI_VALUE 0x33 /* Valid WHOAMI register value */
|
||||
|
||||
/* LIS2DH Internal Registers **********************************************/
|
||||
|
||||
#define ST_LIS2DH_WHOAMI_REG 0x0f /* WHOAMI register */
|
||||
|
||||
#define ST_LIS2DH_STATUS_AUX_REG 0x07 /* Temperature status */
|
||||
#define ST_LIS2DH_OUT_TEMP_L_REG 0x0c /* Temperature data */
|
||||
#define ST_LIS2DH_OUT_TEMP_H_REG 0x0d /* Temperature data */
|
||||
|
||||
#define ST_LIS2DH_TEMP_CFG_REG 0x1f
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG1 0x20
|
||||
|
||||
/* CR1 ODR 4 MSBs (XXXX---) */
|
||||
|
||||
#define ST_LIS2DH_CR1_ODR_PWR_DWN 0x00
|
||||
#define ST_LIS2DH_CR1_ODR_1HZ 0x10 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_10HZ 0x20 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_25HZ 0x30 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_50HZ 0x40 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_100HZ 0x50 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_200HZ 0x60 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_400HZ 0x70 /* HR / Normal / Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_1620HZ 0x80 /* Low Power */
|
||||
#define ST_LIS2DH_CR1_ODR_1344_5376HZ 0x90 /* HR / Normal: 1344Hz, Low power: 5376Hz*/
|
||||
#define ST_LIS2DH_CR1_LOWP_ENABLE 0x08 /* Low power mode enable */
|
||||
#define ST_LIS2DH_CR1_ZEN 0x04 /* Z-Axis Enable */
|
||||
#define ST_LIS2DH_CR1_YEN 0x02 /* Y-Axis Enable */
|
||||
#define ST_LIS2DH_CR1_XEN 0x01 /* X-Axis Enable */
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG2 0x21
|
||||
|
||||
/* HPM1 .... HP FILT_MODE (XX------) */
|
||||
|
||||
#define ST_LIS2DH_CR2_HPFILT_M_NORM 0x00 /* Normal mode (reset reading REFERENCE/DATACAPTURE (26h) register) */
|
||||
#define ST_LIS2DH_CR2_HPFILT_M_REFSIG 0x40 /* Reference signal for filtering */
|
||||
#define ST_LIS2DH_CR2_HPFILT_M_NORM2 0x80 /* Normal mode */
|
||||
#define ST_LIS2DH_CR2_HPFILT_M_AUTOR 0xc0 /* Autoreset on interrupt event */
|
||||
#define ST_LIS2DH_CR2_FDS 0x08
|
||||
|
||||
/* HPIS1 HPFILT ENABLE for INT1 (-------X) */
|
||||
|
||||
#define ST_LIS2DH_CR2_HPENABLED_INT1 0x01 /* HP filter enabled for INT1 */
|
||||
|
||||
/* HPIS2 HPFILT ENABLE for INT2 (------X-) */
|
||||
|
||||
#define ST_LIS2DH_CR2_HPENABLED_INT2 0x02 /* HP filter enabled for INT2 */
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG3 0x22
|
||||
|
||||
/* I1_AOI1 ENABLE for INT2 (-X------) */
|
||||
|
||||
#define ST_LIS2DH_CR3_I1_AOI1_ENABLED 0x40 /* AOI1 interrupt on INT1 pin.*/
|
||||
#define ST_LIS2DH_CR3_I1_AOI2_ENABLED 0x20 /* AOI2 interrupt on INT1 pin.*/
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG4 0x23
|
||||
|
||||
/* BDU ... Block Data Update (X-------) */
|
||||
|
||||
#define ST_LIS2DH_CR4_BDU_CONT 0x00 /* Continuous update (Default) */
|
||||
#define ST_LIS2DH_CR4_BDU_UPD_ON_READ 0x80 /* Output registers not updated until MSB and LSB have been read */
|
||||
#define ST_LIS2DH_CR4_FULL_SCALE_2G 0x0
|
||||
#define ST_LIS2DH_CR4_FULL_SCALE_4G 0x10
|
||||
#define ST_LIS2DH_CR4_FULL_SCALE_8G 0x20
|
||||
#define ST_LIS2DH_CR4_FULL_SCALE_16G 0x30
|
||||
|
||||
/* HR .. Operation mode selector (----X---) */
|
||||
|
||||
#define ST_LIS2DH_CR4_HR_ENABLED 0x08 /* See section 2.6.3 in datasheet */
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG5 0x24
|
||||
#define ST_LIS2DH_CR5_BOOT 0x80
|
||||
#define ST_LIS2DH_CR5_FIFO_EN 0x40
|
||||
#define ST_LIS2DH_CR5_LIR_INT1 0x08
|
||||
#define ST_LIS2DH_CR5_D4D_INT1 0x04
|
||||
#define ST_LIS2DH_CR5_LIR_INT2 0x02
|
||||
#define ST_LIS2DH_CR5_D4D_INT2 0x01
|
||||
|
||||
#define ST_LIS2DH_CTRL_REG6 0x25
|
||||
#define ST_LIS2DH_REFERENCE_REG 0x26
|
||||
|
||||
#define ST_LIS2DH_STATUS_REG 0x27 /* Status Register */
|
||||
#define ST_LIS2DH_SR_ZYXOR 0x80 /* OR'ed X,Y and Z data over-run */
|
||||
#define ST_LIS2DH_SR_ZOR 0x40 /* individual data over-run ... */
|
||||
#define ST_LIS2DH_SR_YOR 0x20
|
||||
#define ST_LIS2DH_SR_XOR 0x10
|
||||
#define ST_LIS2DH_SR_ZYXDA 0x08 /* OR'ed X,Y and Z data available */
|
||||
#define ST_LIS2DH_SR_ZDA 0x04 /* individual data available ... */
|
||||
#define ST_LIS2DH_SR_YDA 0x02
|
||||
#define ST_LIS2DH_SR_XDA 0x01
|
||||
|
||||
#define ST_LIS2DH_OUT_X_L_REG 0x28
|
||||
#define ST_LIS2DH_OUT_X_H_REG 0x29
|
||||
#define ST_LIS2DH_OUT_Y_L_REG 0x2a
|
||||
#define ST_LIS2DH_OUT_Y_H_REG 0x2b
|
||||
#define ST_LIS2DH_OUT_Z_L_REG 0x2c
|
||||
#define ST_LIS2DH_OUT_Z_H_REG 0x2d
|
||||
|
||||
#define ST_LIS2DH_FIFO_CTRL_REG 0x2e
|
||||
#define ST_LIS2DH_FIFOCR_THRESHOLD_MASK 0x1f
|
||||
#define ST_LIS2DH_FIFOCR_THRESHOLD(x) ((x) & ST_LIS2DH_FIFOCR_THRESHOLD_MASK)
|
||||
#define ST_LIS2DH_FIFOCR_INT1 0x00
|
||||
#define ST_LIS2DH_FIFOCR_INT2 0x20
|
||||
#define ST_LIS2DH_FIFOCR_MODE_MASK 0xc0
|
||||
|
||||
#define ST_LIS2DH_FIFO_SRC_REG 0x2f
|
||||
#define ST_LIS2DH_FIFOSR_NUM_SAMP_MASK 0x1f
|
||||
#define ST_LIS2DH_FIFOSR_EMPTY 0x20
|
||||
#define ST_LIS2DH_FIFOSR_OVRN_FIFO 0x40
|
||||
#define ST_LIS2DH_FIFOSR_WTM 0x80
|
||||
|
||||
#define ST_LIS2DH_INT1_CFG_REG 0x30
|
||||
#define ST_LIS2DH_INT_CFG_AOI 0x80
|
||||
#define ST_LIS2DH_INT_CFG_6D 0x40
|
||||
#define ST_LIS2DH_INT_CFG_ZHIE 0x20
|
||||
#define ST_LIS2DH_INT_CFG_ZLIE 0x10
|
||||
#define ST_LIS2DH_INT_CFG_YHIE 0x08
|
||||
#define ST_LIS2DH_INT_CFG_YLIE 0x04
|
||||
#define ST_LIS2DH_INT_CFG_XHIE 0x02
|
||||
#define ST_LIS2DH_INT_CFG_XLIE 0x01
|
||||
|
||||
#define ST_LIS2DH_INT1_SRC_REG 0x31
|
||||
#define ST_LIS2DH_INT_SR_XLOW 0x01
|
||||
#define ST_LIS2DH_INT_SR_XHIGH 0x02
|
||||
#define ST_LIS2DH_INT_SR_YLOW 0x04
|
||||
#define ST_LIS2DH_INT_SR_YHIGH 0x08
|
||||
#define ST_LIS2DH_INT_SR_ZLOW 0x10
|
||||
#define ST_LIS2DH_INT_SR_ZHIGH 0x20
|
||||
#define ST_LIS2DH_INT_SR_ACTIVE 0x40
|
||||
|
||||
#define ST_LIS2DH_INT1_THS_REG 0x32 /* 7-bit value for threshold */
|
||||
|
||||
#define ST_LIS2DH_INT1_DUR_REG 0x33 /* 7-bit value for duration */
|
||||
|
||||
#define ST_LIS2DH_INT2_CFG_REG 0x34
|
||||
|
||||
#define ST_LIS2DH_INT2_SRC_REG 0x35
|
||||
|
||||
#define ST_LIS2DH_INT2_THS_REG 0x36 /* 7-bit value for threshold */
|
||||
|
||||
#define ST_LIS2DH_INT2_DUR_REG 0x37 /* 7-bit value for duration */
|
||||
|
||||
#define ST_LIS2DH_CLICK_CFG_REG 0x38
|
||||
|
||||
#define ST_LIS2DH_CLICK_SRC_REG 0x39
|
||||
|
||||
#define ST_LIS2DH_CLICK_THS_REG 0x3a
|
||||
|
||||
#define ST_LIS2DH_TIME_LIMIT_REG 0x3b
|
||||
|
||||
#define ST_LIS2DH_TIME_LATENCY_REG 0x3c
|
||||
|
||||
#define ST_LIS2DH_TIME_WINDOW_REG 0x3d
|
||||
|
||||
#define ST_LIS2DH_ACT_DUR_REG 0x3f
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
enum lis2dh_ouput_data_rate
|
||||
{
|
||||
LIS2DH_ODR_POWER_DOWN = 0x00,
|
||||
LIS2DH_ODR_1HZ = 0x10,
|
||||
LIS2DH_ODR_10HZ = 0x20,
|
||||
LIS2DH_ODR_25HZ = 0x30,
|
||||
LIS2DH_ODR_50HZ = 0x40,
|
||||
LIS2DH_ODR_100HZ = 0x50,
|
||||
LIS2DH_ODR_200HZ = 0x60,
|
||||
LIS2DH_ODR_400HZ = 0x70,
|
||||
LIS2DH_ODR_1620HZ = 0x80,
|
||||
LIS2DH_ODR_5376HZ = 0x90,
|
||||
};
|
||||
|
||||
enum lis2dh_high_pass_filter_mode
|
||||
{
|
||||
LIS2DH_REFERENCE_SIGNAL = 0x40,
|
||||
LIS2DH_NORMAL_MODE = 0x80,
|
||||
LIS2DH_AUTORESET_ON_INTERRUPT = 0xc0,
|
||||
};
|
||||
|
||||
enum lis2dh_scale_range
|
||||
{
|
||||
LIS2DH_RANGE_2G = 0x00,
|
||||
LIS2DH_RANGE_4G = 0x10,
|
||||
LIS2DH_RANGE_8G = 0x20,
|
||||
LIS2DH_RANGE_16G = 0x30,
|
||||
};
|
||||
|
||||
enum lis2dh_self_test
|
||||
{
|
||||
LIS2DH_NORMAL = 0x00,
|
||||
LIS2DH_SELF_TEST0 = 0x02,
|
||||
LIS2DH_SELF_TEST1 = 0x04,
|
||||
};
|
||||
|
||||
enum lis2dh_fifo_mode
|
||||
{
|
||||
LIS2DH_BYPASS_MODE = 0x00,
|
||||
LIS2DH_FIFO_MODE = 0x40,
|
||||
LIS2DH_STREAM_MODE = 0x80,
|
||||
LIS2DH_TRIGGER_MODE = 0xc0,
|
||||
};
|
||||
|
||||
enum lis2dh_interrupt_mode
|
||||
{
|
||||
LIS2DH_OR_COMBINATION = 0x00,
|
||||
LIS2DH_6D_MOVEMENT = 0x40,
|
||||
LIS2DH_AND_COMBINATION = 0x80,
|
||||
LIS2DH_6D_POSITION = 0xc0,
|
||||
};
|
||||
|
||||
struct lis2dh_vector_s
|
||||
{
|
||||
int16_t x, y, z;
|
||||
} packed_struct;
|
||||
|
||||
struct lis2dh_res_header
|
||||
{
|
||||
uint8_t meas_count;
|
||||
bool int1_occurred;
|
||||
uint8_t int1_source;
|
||||
bool int2_occurred;
|
||||
uint8_t int2_source;
|
||||
} packed_struct;
|
||||
|
||||
struct lis2dh_result
|
||||
{
|
||||
struct lis2dh_res_header header;
|
||||
struct lis2dh_vector_s measurements[0];
|
||||
} packed_struct;
|
||||
|
||||
struct lis2dh_setup
|
||||
{
|
||||
bool temp_enable:1;
|
||||
bool xy_axis_fixup:1;
|
||||
|
||||
uint8_t data_rate;
|
||||
uint8_t low_power_mode_enable;
|
||||
uint8_t zen;
|
||||
uint8_t yen;
|
||||
uint8_t xen;
|
||||
|
||||
uint8_t hpmode;
|
||||
uint8_t hpcf;
|
||||
uint8_t fds;
|
||||
uint8_t hpclick;
|
||||
uint8_t hpis2;
|
||||
uint8_t hpis1;
|
||||
|
||||
uint8_t int1_click_enable;
|
||||
uint8_t int1_aoi_enable;
|
||||
uint8_t int2_aoi_enable;
|
||||
uint8_t int1_drdy_enable;
|
||||
uint8_t int2_drdy_enable;
|
||||
uint8_t int_wtm_enable;
|
||||
uint8_t int_overrun_enable;
|
||||
|
||||
uint8_t bdu;
|
||||
uint8_t endian;
|
||||
uint8_t fullscale;
|
||||
uint8_t high_resolution_enable;
|
||||
uint8_t selftest;
|
||||
uint8_t spi_mode;
|
||||
|
||||
uint8_t reboot;
|
||||
uint8_t fifo_enable;
|
||||
uint8_t int1_latch;
|
||||
uint8_t int1_4d_enable;
|
||||
uint8_t int2_latch;
|
||||
uint8_t int2_4d_enable;
|
||||
|
||||
uint8_t int2_click_enable;
|
||||
uint8_t int_enable;
|
||||
uint8_t boot_int1_enable;
|
||||
uint8_t high_low_active;
|
||||
|
||||
uint8_t reference;
|
||||
|
||||
uint8_t fifo_mode;
|
||||
uint8_t trigger_selection;
|
||||
uint8_t fifo_trigger_threshold;
|
||||
|
||||
uint8_t int1_interrupt_mode;
|
||||
uint8_t int1_enable_6d;
|
||||
uint8_t int1_int_z_high_enable;
|
||||
uint8_t int1_int_z_low_enable;
|
||||
uint8_t int1_int_y_high_enable;
|
||||
uint8_t int1_int_y_low_enable;
|
||||
uint8_t int1_int_x_high_enable;
|
||||
uint8_t int1_int_x_low_enable;
|
||||
uint8_t int1_int_threshold;
|
||||
uint8_t int1_int_duration;
|
||||
|
||||
uint8_t int2_interrupt_mode;
|
||||
uint8_t int2_enable_6d;
|
||||
uint8_t int2_int_z_high_enable;
|
||||
uint8_t int2_int_z_low_enable;
|
||||
uint8_t int2_int_y_high_enable;
|
||||
uint8_t int2_int_y_low_enable;
|
||||
uint8_t int2_int_x_high_enable;
|
||||
uint8_t int2_int_x_low_enable;
|
||||
uint8_t int2_int_threshold;
|
||||
uint8_t int2_int_duration;
|
||||
|
||||
uint8_t z_double_click_enable;
|
||||
uint8_t z_single_click_enable;
|
||||
uint8_t y_double_click_enable;
|
||||
uint8_t y_single_click_enable;
|
||||
uint8_t x_double_click_enable;
|
||||
uint8_t x_single_click_enable;
|
||||
|
||||
uint8_t click_threshold;
|
||||
uint8_t click_time_limit;
|
||||
uint8_t click_time_latency;
|
||||
uint8_t click_time_window;
|
||||
};
|
||||
|
||||
struct lis2dh_config_s
|
||||
{
|
||||
/* Device characterization */
|
||||
|
||||
int irq; /* IRQ number received by interrupt handler. */
|
||||
|
||||
/* IRQ/GPIO access callbacks. These operations all hidden behind
|
||||
* callbacks to isolate the lis2dh driver from differences in GPIO
|
||||
* interrupt handling by varying boards and MCUs.
|
||||
*
|
||||
* irq_attach - Attach the lis2dh interrupt handler to the GPIO interrupt
|
||||
* irq_enable - Enable or disable the GPIO interrupt
|
||||
* clear_irq - Acknowledge/clear any pending GPIO interrupt
|
||||
*
|
||||
*/
|
||||
|
||||
CODE int (*irq_attach)(FAR struct lis2dh_config_s *state, xcpt_t isr, FAR void *arg);
|
||||
CODE void (*irq_enable)(FAR const struct lis2dh_config_s *state, bool enable);
|
||||
CODE void (*irq_clear)(FAR const struct lis2dh_config_s *state);
|
||||
CODE bool (*read_int1_pin)(void);
|
||||
CODE bool (*read_int2_pin)(void);
|
||||
};
|
||||
|
||||
struct lis2dh_raw_data_s
|
||||
{
|
||||
uint16_t out_x;
|
||||
uint16_t out_y;
|
||||
uint16_t out_z;
|
||||
} packed_struct;
|
||||
|
||||
typedef struct lis2dh_raw_data_s lis2dh_raw_data_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lis2dh_register
|
||||
*
|
||||
* Description:
|
||||
* Register the LIS2DH character device as 'devpath'
|
||||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the driver to register. E.g., "/dev/acc0"
|
||||
* i2c - An instance of the I2C interface to use to communicate with LIS2DH
|
||||
* addr - The I2C address of the LIS2DH. The base I2C address of the LIS2DH
|
||||
* is 0x18. Bit 0 can be controlled via SA0 pad - when connected to
|
||||
* voltage supply the address is 0x19.
|
||||
* config - Pointer to LIS2DH configuration
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lis2dh_register(FAR const char *devpath, FAR struct i2c_master_s *i2c,
|
||||
uint8_t addr, FAR struct lis2dh_config_s *config);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_SENSORS_LIS2DH_H */
|
||||
@ -130,7 +130,7 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr,
|
||||
FAR socklen_t *addrlen, FAR struct socket *newsock)
|
||||
{
|
||||
int errcode;
|
||||
#ifdef NET_TCP_HAVE_STACK
|
||||
#if defined(NET_TCP_HAVE_STACK) || defined(CONFIG_NET_LOCAL_STREAM)
|
||||
int ret;
|
||||
#endif
|
||||
|
||||
|
||||
@ -124,7 +124,7 @@
|
||||
ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len,
|
||||
int flags)
|
||||
{
|
||||
int ret;
|
||||
ssize_t ret;
|
||||
|
||||
/* Treat as a cancellation point */
|
||||
|
||||
@ -175,9 +175,9 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len,
|
||||
}
|
||||
#endif /* CONFIG_NETDEV_MULTINIC && NET_TCP_HAVE_STACK */
|
||||
#elif defined(NET_TCP_HAVE_STACK)
|
||||
nsent = psock_tcp_send(psock, buf, len, flags, to, tolen);
|
||||
ret = psock_tcp_send(psock, buf, len);
|
||||
#else
|
||||
nsent = -ENOSYS;
|
||||
ret = -ENOSYS;
|
||||
#endif /* CONFIG_NET_6LOWPAN */
|
||||
}
|
||||
#endif /* CONFIG_NET_TCP */
|
||||
@ -219,7 +219,7 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len,
|
||||
#endif /* CONFIG_NETDEV_MULTINIC && NET_UDP_HAVE_STACK */
|
||||
#elif defined(NET_UDP_HAVE_STACK)
|
||||
/* Only UDP/IP packet send */
|
||||
|
||||
|
||||
ret = psock_udp_send(psock, buf, len);
|
||||
#else
|
||||
ret = -ENOSYS;
|
||||
|
||||
@ -68,4 +68,35 @@ config IEEE802154_LOOPBACK_LPWORK
|
||||
endchoice # Work queue
|
||||
endif # IEEE802154_LOOPBACK
|
||||
|
||||
config IEEE802154_LOOPBACK
|
||||
bool "IEEE802154 6loWPAN Loopback"
|
||||
default n
|
||||
depends on NET_6LOWPAN && NET_IPv6
|
||||
select ARCH_HAVE_NETDEV_STATISTICS
|
||||
---help---
|
||||
Add support for the IEEE802154 6loWPAN Loopback test device.
|
||||
|
||||
if IEEE802154_LOOPBACK
|
||||
|
||||
choice
|
||||
prompt "Work queue"
|
||||
default IEEE802154_LOOPBACK_LPWORK if SCHED_LPWORK
|
||||
default IEEE802154_LOOPBACK_HPWORK if !SCHED_LPWORK && SCHED_HPWORK
|
||||
depends on SCHED_WORKQUEUE
|
||||
---help---
|
||||
Work queue support is required to use the loopback driver. If the
|
||||
low priority work queue is available, then it should be used by the
|
||||
loopback driver.
|
||||
|
||||
config IEEE802154_LOOPBACK_HPWORK
|
||||
bool "High priority"
|
||||
depends on SCHED_HPWORK
|
||||
|
||||
config IEEE802154_LOOPBACK_LPWORK
|
||||
bool "Low priority"
|
||||
depends on SCHED_LPWORK
|
||||
|
||||
endchoice # Work queue
|
||||
endif # IEEE802154_LOOPBACK
|
||||
|
||||
endif # IEEE802154
|
||||
|
||||
Loading…
Reference in New Issue
Block a user