SAM4S: Add macros to manage peripheral clocks
This commit is contained in:
Gregory Nutt
parent
93ee6cb291
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1b57fdd7dd
@ -56,9 +56,15 @@
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#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
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#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
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/* 0x000c: Reserved */
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#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */
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#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */
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#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */
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# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */
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# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */
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#elif defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */
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# define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */
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# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
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@ -111,7 +117,13 @@
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#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
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#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
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#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
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#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET)
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#elif defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET)
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#endif
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#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET)
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#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET)
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/sam34/sam3u_periphclks.h
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*
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* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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157
arch/arm/src/sam34/sam4s_periphclks.h
Normal file
157
arch/arm/src/sam34/sam4s_periphclks.h
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@ -0,0 +1,157 @@
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/************************************************************************************
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* arch/arm/src/sam34/sam4s_periphclks.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H
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#define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <arch/irq.h>
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#include "chip/sam4s_pmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Helper macros */
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#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
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#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
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#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
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#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
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#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
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#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)
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#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC)
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#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT)
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#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
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#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC)
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#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0)
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#define sam_eefc1_enableclk() sam_enableperiph0(SAM_PID_EEFC1)
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#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
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#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
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#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
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#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
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#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
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#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
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#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
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#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
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#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI)
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#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
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#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
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#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC)
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#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
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#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
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#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
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#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
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#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
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#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5)
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#define sam_adc12b_enableclk() sam_enableperiph0(SAM_PID_ADC12B)
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#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC)
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#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM)
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#define sam_crccu_enableclk() sam_enableperiph1(SAM_PID_CRCCU)
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#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC)
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#define sam_udp_enableclk() sam_enableperiph1(SAM_PID_UDP)
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#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC)
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#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC)
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#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC)
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#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT)
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#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
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#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC)
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#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0)
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#define sam_eefc1_disableclk() sam_disableperiph0(SAM_PID_EEFC1)
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#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
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#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
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#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
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#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
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#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
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#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
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#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
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#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
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#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI)
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#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
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#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
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#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC)
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#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
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#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
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#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
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#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
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#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
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#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5)
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#define sam_adc12b_disableclk() sam_disableperiph0(SAM_PID_ADC)
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#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC)
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#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM)
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#define sam_crccu_disableclk() sam_disableperiph1(SAM_PID_CRCCU)
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#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC)
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#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H */
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@ -644,7 +644,7 @@ static inline void sam_disable(void)
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{
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/* Disable the MCI peripheral clock */
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putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCDR);
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sam_hsmci_disableclk();
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/* Disable the MCI */
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@ -1224,7 +1224,6 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
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flags = irqsave();
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sam_hsmci_enableclk();
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fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR));
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/* Reset the MCI */
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@ -150,7 +150,7 @@
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* selected by the PBADIVMASK register.
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*/
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
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# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
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#elif defined(CONFIG_ARCH_CHIP_SAM4L)
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@ -60,7 +60,7 @@
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#include "os_internal.h"
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#include "chip.h"
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# include "chip/sam3u_uart.h"
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#elif defined(CONFIG_ARCH_CHIP_SAM4L)
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# include "chip/sam4l_usart.h"
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@ -314,7 +314,7 @@
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* selected by the PBADIVMASK register.
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*/
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
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# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
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#elif defined(CONFIG_ARCH_CHIP_SAM4L)
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@ -64,8 +64,8 @@
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_SYSTICK_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
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#elif defined(CONFIG_ARCH_CHIP_SAM4L)
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# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* PBA frequency is undivided */
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#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */
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#else
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# error Unrecognized SAM architecture
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#endif
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