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Merged in david_s5/nuttx/master_h7 (pull request #1002)

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stm32h7 RTC and friends  support

* stm32h7:Removed f7 in file path

* stm32f7:Fix overwritten IRQ enabled

       System boot order calls clock_initialize then up_initalize.
       clock_initialize was setting up the alarm IRQ
       up_initalize is initializing the NVIC.

       This most likely worked in the past due to a bug in the
       NVIC init code that failed to clear the Interrupt enables.
       That was fixed in 510b0f7e arch/arm/src: Correct all ARMv7-M
       architectures.  Interrupts were not be disabled correctly
       on power up.

* stm32h7:Ported over F7 RTC

* nucleo-h743zi:Add RTC

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane 2019-08-17 14:01:28 +00:00 committed by Gregory Nutt
parent 4383ef6787
commit 1bbf5c9449
19 changed files with 4210 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
arch/arm/src/stm32f7/stm32_rtc.c
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@ -1,9 +1,9 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32f7/stm32_rtc.c * arch/arm/src/stm32f7/stm32_rtc.c
* *
* Copyright (C) 2011, 2015-2018 Gregory Nutt. All rights reserved. * Copyright (C) 2011, 2015-2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com> * David Sidrane <david.sidrane@nscdg.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -1081,23 +1081,6 @@ int up_rtc_initialize(void)
return -ETIMEDOUT; return -ETIMEDOUT;
} }
#ifdef CONFIG_RTC_ALARM
/* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts
* are connected to the EXTI controller. To enable the RTC Alarm
* interrupt, the following sequence is required:
*
* 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode
* and select the rising edge sensitivity.
* For STM32F7:
* EXTI line 21 RTC Tamper & Timestamp
* EXTI line 22 RTC Wakeup
* 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
* 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
*/
(void)stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL);
#endif
g_rtc_enabled = true; g_rtc_enabled = true;
rtc_dumpregs("After Initialization"); rtc_dumpregs("After Initialization");
return OK; return OK;
@ -1460,10 +1443,30 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
FAR struct alm_cbinfo_s *cbinfo; FAR struct alm_cbinfo_s *cbinfo;
rtc_alarmreg_t alarmreg; rtc_alarmreg_t alarmreg;
int ret = -EINVAL; int ret = -EINVAL;
static bool once = false;
DEBUGASSERT(alminfo != NULL); DEBUGASSERT(alminfo != NULL);
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
/* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts
* are connected to the EXTI controller. To enable the RTC Alarm
* interrupt, the following sequence is required:
*
* 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode
* and select the rising edge sensitivity.
* For STM32F7:
* EXTI line 21 RTC Tamper & Timestamp
* EXTI line 22 RTC Wakeup
* 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
* 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
*/
if (!once)
{
once = true;
(void)stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL);
}
/* REVISIT: Should test that the time is in the future */ /* REVISIT: Should test that the time is in the future */
rtc_dumptime(&alminfo->as_time, NULL, "New alarm time"); rtc_dumptime(&alminfo->as_time, NULL, "New alarm time");

81
arch/arm/src/stm32h7/Kconfig
View File

@ -134,6 +134,11 @@ config STM32H7_TIM
bool bool
default n default n
config STM32H7_RTC
bool "RTC"
default n
select RTC
config STM32H7_PWR config STM32H7_PWR
bool "PWR" bool "PWR"
default n default n
@ -1002,6 +1007,82 @@ config STM32H7_SAVE_CRASHDUMP
endif # STM32H7_BKPSRAM endif # STM32H7_BKPSRAM
config STM32H7_HAVE_RTC_SUBSECONDS
bool
select ARCH_HAVE_RTC_SUBSECONDS
default y
menu "RTC Configuration"
depends on STM32H7_RTC
config STM32H7_RTC_MAGIC_REG
int "BKP register"
default 0
range 0 31
---help---
The BKP register used to store/check the Magic value to determine if
RTC is already setup
config STM32H7_RTC_MAGIC
hex "RTC Magic 1"
default 0xfacefeed
---help---
Value used as Magic to determine if the RTC is already setup
config STM32H7_RTC_MAGIC_TIME_SET
hex "RTC Magic 2"
default 0xf00dface
---help---
Value used as Magic to determine if the RTC has been setup and has
time set
choice
prompt "RTC clock source"
default STM32H7_RTC_LSECLOCK
config STM32H7_RTC_HSECLOCK
bool "HSE clock"
---help---
Drive the RTC with the HSE clock, divided down to 1MHz.
config STM32H7_RTC_LSECLOCK
bool "LSE clock"
---help---
Drive the RTC with the LSE clock
config STM32H7_RTC_LSICLOCK
bool "LSI clock"
---help---
Drive the RTC with the LSI clock
endchoice #"RTC clock source"
if STM32H7_RTC_LSECLOCK
config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY
int "LSE oscillator drive capability level at LSE start-up"
default 0
range 0 3
---help---
0 = Low drive capability (default)
1 = Medium high drive capability
2 = Medium low drive capability
3 = High drive capability
config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
int "LSE oscillator drive capability level after LSE start-up"
default 0
range 0 3
---help---
0 = Low drive capability (default)
1 = Medium high drive capability
2 = Medium low drive capability
3 = High drive capability
endif # STM32H7_RTC_LSECLOCK
endmenu # RTC Configuration
config STM32H7_CUSTOM_CLOCKCONFIG config STM32H7_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration" bool "Custom clock configuration"
default n default n

21
arch/arm/src/stm32h7/Make.defs
View File

@ -120,6 +120,14 @@ ifeq ($(CONFIG_STM32H7_DMA),y)
CHIP_CSRCS += stm32_dma.c CHIP_CSRCS += stm32_dma.c
endif endif
ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y)
CHIP_CSRCS += stm32_lsi.c
endif
ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y)
CHIP_CSRCS += stm32_lse.c
endif
ifeq ($(CONFIG_STM32H7_I2C),y) ifeq ($(CONFIG_STM32H7_I2C),y)
CHIP_CSRCS += stm32_i2c.c CHIP_CSRCS += stm32_i2c.c
endif endif
@ -128,6 +136,19 @@ ifeq ($(CONFIG_STM32H7_PWR),y)
CHIP_CSRCS += stm32_pwr.c CHIP_CSRCS += stm32_pwr.c
endif endif
ifeq ($(CONFIG_STM32H7_RTC),y)
CHIP_CSRCS += stm32_rtc.c
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
endif
ifeq ($(CONFIG_RTC_PERIODIC),y)
CHIP_CSRCS += stm32_exti_wakeup.c
endif
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += stm32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_STM32H7_SPI),y) ifeq ($(CONFIG_STM32H7_SPI),y)
CHIP_CSRCS += stm32_spi.c CHIP_CSRCS += stm32_spi.c
endif endif

4
arch/arm/src/stm32h7/hardware/stm32_exti.h
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@ -160,6 +160,10 @@
#define EXIT_EVENT(n) STM32_EXTI_MASK(n) #define EXIT_EVENT(n) STM32_EXTI_MASK(n)
#define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 = RTC Alarm event */
#define EXTI_RTC_TAMPER (1 << 18) /* EXTI line 18 = RTC tamper, RTC timestamp, RCC LSECSS */
#define EXTI_RTC_WAKEUP (1 << 19) /* EXTI line 19 = RTC wakeup timer */
/* D3 pending clear selection register low 1-3. /* D3 pending clear selection register low 1-3.
* D3 pending clear selection register high 1-3 * D3 pending clear selection register high 1-3
* *

400
arch/arm/src/stm32h7/hardware/stm32_rtcc.h Normal file
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@ -0,0 +1,400 @@
/************************************************************************************
* arch/arm/src/stm32h7/hardware/stm32_rtcc.h
*
* Copyright (C) 2011-2016, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */
#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
/* Register Addresses ***************************************************************/
#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET)
#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET)
#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET)
#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET)
#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET)
#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET)
#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET)
#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET)
#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET)
#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET)
#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n))
#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET)
#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET)
#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET)
#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET)
#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET)
#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET)
#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET)
#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET)
#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET)
#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET)
#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET)
#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET)
#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET)
#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET)
#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET)
#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET)
#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET)
#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET)
#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
#define STM32_RTC_BKCOUNT 32
/* Register Bitfield Definitions ****************************************************/
/* RTC time register */
#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT)
#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT)
#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
#define RTC_TR_RESERVED_BITS (0xff808080)
/* RTC date register */
#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT)
#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT)
# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT)
#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
#define RTC_DR_RESERVED_BITS (0xff0000c0)
/* RTC control register */
#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT)
# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */
#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT)
# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
/* RTC initialization and status register */
#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */
#define RTC_ISR_ITSF (1 << 17) /* Bit 17: Internal time-stamp flag */
#define RTC_ISR_ALLFLAGS (0x0003ffff)
/* RTC prescaler register */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
/* RTC wakeup timer register */
#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */
/* RTC alarm A/B registers */
#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT)
#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT)
#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */
#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT)
#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT)
#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */
#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT)
#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */
#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */
#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT)
#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT)
#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */
/* RTC write protection register */
#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */
/* RTC sub second register */
#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC shift control register */
#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT)
#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
/* RTC time stamp time register */
#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT)
#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT)
#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT)
#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT)
#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT)
#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT)
#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
/* RTC time stamp date register */
#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT)
#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT)
#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
#define RTC_TSDR_MU_MASK (15 << RTC_TSDR_MU_SHIFT)
#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT)
/* RTC timestamp sub second register */
#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */
/* RTC calibration register */
#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
/* RTC tamper configuration register */
#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */
#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */
#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: RTC_TAMP2 input detection enable */
#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for RTC_TAMP2 input */
#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV8192 (2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV4096 (3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV2048 (4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT)
#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
#define RTC_TAMPCR_TAMPPRCH_MASK (3 << RTC_TAMPCR_TAMPPRCH_SHIFT)
# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */
#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */
#define RTC_TAMPCR_TAMP1MF (1 << 18) /* Bit 18: Tamper 1 mask flag */
#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: Tamper 2 interrupt enable */
#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: Tamper 2 no erase */
#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: Tamper 2 mask flag */
#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: Tamper 3 interrupt enable */
#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: Tamper 3 no erase */
#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: Tamper 3 mask flag */
/* RTC alarm A/B sub second register */
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
/* RTC option register */
#define RTC_OR_RTC_ALARM_TYPE (1 << 0) /* Bit 0: RTC_ALARM output type on PC13 */
#define RTC_OR_RTC_OUT_RMP (1 << 1) /* Bit 1: RTC_OUT remap */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H */

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arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
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#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ #define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ #define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ #define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */
#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT)
# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */
# define RCC_BDCR_LSEDRV_MEDHI (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability */
# define RCC_BDCR_LSEDRV_MEDLO (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability */
# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */
#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */
#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */
/* Bit 7: Reserved */
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ #define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) #define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ # define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ # define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ # define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
/* Bits 10-15: Reserved */
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ #define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ #define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
/* Bits 17-31: Reserved */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */

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/****************************************************************************
* arch/arm/src/include/stm32f7/stm32_alarm.h
*
* Copyright (C) 2016, 2018, 2019 Gregory Nutt. All rights reserved.
* Authors: Neil Hancock - delegated to Gregory Nutt Mar 30, 2016
* David Sidrane <david.sidrane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_ALARM_H
#define __ARCH_ARM_SRC_STM32H7_STM32_ALARM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <time.h>
/****************************************************************************
* Public Types
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid);
/* These features map to STM32 RTC from stm32H7xx */
enum alm_id_e
{
RTC_ALARMA = 0, /* RTC ALARM A */
RTC_ALARMB, /* RTC ALARM B */
RTC_ALARM_LAST
};
/* Structure used to pass parameters to set an alarm */
struct alm_setalarm_s
{
int as_id; /* enum alm_id_e */
struct tm as_time; /* Alarm expiration time */
alm_callback_t as_cb; /* Callback (if non-NULL) */
FAR void *as_arg; /* Argument for callback */
};
/* Structure used to pass parameters to query an alarm */
struct alm_rdalarm_s
{
int ar_id; /* enum alm_id_e */
FAR struct rtc_time *ar_time; /* Argument for storing ALARM RTC time */
};
#endif
#ifdef CONFIG_RTC_PERIODIC
typedef CODE int (*wakeupcb_t)(void);
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
/****************************************************************************
* Name: stm32_rtc_setalarm
*
* Description:
* Set an alarm to an absolute time using associated hardware.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo);
/****************************************************************************
* Name: stm32_rtc_rdalarm
*
* Description:
* Query an alarm configured in hardware.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo);
/****************************************************************************
* Name: stm32_rtc_cancelalarm
*
* Description:
* Cancel an alarm.
*
* Input Parameters:
* alarmid - Identifies the alarm to be cancelled
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_cancelalarm(enum alm_id_e alarmid);
#endif /* CONFIG_RTC_ALARM */
#ifdef CONFIG_RTC_PERIODIC
/****************************************************************************
* Name: stm32_rtc_setperiodic
*
* Description:
* Set a periodic RTC wakeup
*
* Input Parameters:
* period - Time to sleep between wakeups
* callback - Function to call when the period expires.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_setperiodic(FAR const struct timespec *period,
wakeupcb_t callback);
/****************************************************************************
* Name: stm32_rtc_cancelperiodic
*
* Description:
* Cancel a periodic wakeup
*
* Input Parameters:
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_cancelperiodic(void);
#endif /* CONFIG_RTC_PERIODIC */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_ALARM_H */

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_exti_alarm.c
*
* Copyright (C) 2015, 2017, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
*
* This file derives from similar logic for the STM32 F1:
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Diego Sanchez <dsanchez@nx-engineering.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "stm32_gpio.h"
#include "stm32_exti.h"
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to the ALARM EXTI */
static xcpt_t g_alarm_callback;
static void *g_callback_arg;
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_exti_alarm_isr
*
* Description:
* EXTI ALARM interrupt service routine/dispatcher
*
****************************************************************************/
static int stm32_exti_alarm_isr(int irq, void *context, FAR void *arg)
{
int ret = OK;
/* Clear the pending EXTI interrupt */
putreg32(EXTI_RTC_ALARM, STM32_EXTI_CPUPR1);
/* And dispatch the interrupt to the handler */
if (g_alarm_callback != NULL)
{
ret = g_alarm_callback(irq, context, g_callback_arg);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edget
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
g_alarm_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(STM32_IRQ_RTCALARM, stm32_exti_alarm_isr, NULL);
up_enable_irq(STM32_IRQ_RTCALARM);
}
else
{
up_disable_irq(STM32_IRQ_RTCALARM);
}
/* Configure rising/falling edges */
modifyreg32(STM32_EXTI_RTSR1,
risingedge ? 0 : EXTI_RTC_ALARM,
risingedge ? EXTI_RTC_ALARM : 0);
modifyreg32(STM32_EXTI_FTSR1,
fallingedge ? 0 : EXTI_RTC_ALARM,
fallingedge ? EXTI_RTC_ALARM : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32_EXTI_CPUEMR1,
event ? 0 : EXTI_RTC_ALARM,
event ? EXTI_RTC_ALARM : 0);
modifyreg32(STM32_EXTI_CPUIMR1,
func ? 0 : EXTI_RTC_ALARM,
func ? EXTI_RTC_ALARM : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_exti_wakeup.c
*
* Copyright (C) 2009, 2012, 2017-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Juha Niskanen <juha.niskanen@haltian.com>
* David Sidrane <david.sirane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_exti.h"
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to the RTC WAKEUP EXTI */
static xcpt_t g_wakeup_callback;
static void *g_callback_arg;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_exti_wakeup_isr
*
* Description:
* EXTI periodic WAKEUP interrupt service routine/dispatcher
*
****************************************************************************/
static int stm32_exti_wakeup_isr(int irq, void *context, FAR void *arg)
{
int ret = OK;
/* Dispatch the interrupt to the handler */
if (g_wakeup_callback != NULL)
{
ret = g_wakeup_callback(irq, context, g_callback_arg);
}
/* Clear the pending EXTI interrupt */
putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_CPUPR1);
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg)
{
g_wakeup_callback = func;
g_callback_arg = arg;
/* Install external interrupt handlers (if not already attached) */
if (func)
{
irq_attach(STM32_IRQ_RTCWKUP, stm32_exti_wakeup_isr, NULL);
up_enable_irq(STM32_IRQ_RTCWKUP);
}
else
{
up_disable_irq(STM32_IRQ_RTCWKUP);
}
/* Configure rising/falling edges */
modifyreg32(STM32_EXTI_RTSR1,
risingedge ? 0 : EXTI_RTC_WAKEUP,
risingedge ? EXTI_RTC_WAKEUP : 0);
modifyreg32(STM32_EXTI_FTSR1,
fallingedge ? 0 : EXTI_RTC_WAKEUP,
fallingedge ? EXTI_RTC_WAKEUP : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32_EXTI_CPUEMR1,
event ? 0 : EXTI_RTC_WAKEUP,
event ? EXTI_RTC_WAKEUP : 0);
modifyreg32(STM32_EXTI_CPUIMR1,
func ? 0 : EXTI_RTC_WAKEUP,
func ? EXTI_RTC_WAKEUP : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_lse.c
*
* Copyright (C) 2017, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "stm32_rcc.h"
#include "stm32_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
#endif
#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) oscillator.
*
****************************************************************************/
void stm32_rcc_enablelse(void)
{
uint32_t regval;
/* Check if the External Low-Speed (LSE) oscillator is already running. */
regval = getreg32(STM32_RCC_BDCR);
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) !=
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
{
/* The LSE is in the RTC domain and write access is denied to this
* domain after reset, you have to enable write access using DBP bit
* in the PWR CR register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
/* Enable the External Low-Speed (LSE) oscillator by setting the
* LSEON bit the RCC BDCR register.
*/
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
#endif
putreg32(regval, STM32_RCC_BDCR);
/* Wait for the LSE clock to be ready */
while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0);
#if defined(CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY != \
CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
#endif
/* Disable backup domain access if it was disabled on entry */
stm32_pwr_enablebkp(false);
}
}

89
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/****************************************************************************
* arch/arm/src/stm32h7/stm32_lsi.c
*
* Copyright (C) 2012, 2015-2016, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david.sidrane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "stm32_rcc.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
/* Wait for the internal RC 40 kHz oscillator to be stable. */
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
}
/****************************************************************************
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_disablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC CSR register.
*/
modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_rtc.h
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2011-2013, 2015-2019 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
* Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
* David Sidrane <david.sidrane@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_RTC_H
#define __ARCH_ARM_SRC_STM32H7_STM32_RTC_H
#include <nuttx/config.h>
#include "chip.h"
/* The STMH7 family use a more traditional Realtime Clock/Calendar (RTCC) with
* broken-out data/time in BCD format. The backup registers are integrated into
* the RTCC in these families.
*/
#include "hardware/stm32_rtcc.h"
#include "stm32_alarm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if !defined(CONFIG_STM32H7_RTC_MAGIC)
# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed)
#endif
#if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32H7_RTC_MAGIC_TIME_SET (0xf00dface)
#endif
#if !defined(CONFIG_STM32H7_RTC_MAGIC_REG)
# define CONFIG_STM32H7_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_STM32H7_RTC_MAGIC_TIME_SET
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32H7_RTC_MAGIC_REG)
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: The sub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
#endif
/****************************************************************************
* Name: stm32_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int stm32_rtc_setdatetime(FAR const struct tm *tp);
#endif
/****************************************************************************
* Name: stm32_rtc_havesettime
*
* Description:
* Check if RTC time has been set.
*
* Returned Value:
* Returns true if RTC date-time have been previously set.
*
****************************************************************************/
bool stm32_rtc_havesettime(void);
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
struct rtc_lowerhalf_s;
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_RTC_H */

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/****************************************************************************
* arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c
*
* Copyright (C) 2015-2016, 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include <string.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/timers/rtc.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_rtc.h"
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_NALARMS 2
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct stm32_cbinfo_s
{
volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */
volatile FAR void *priv; /* Private argument to accompany callback */
uint8_t id; /* Identifies the alarm */
};
#endif
/* This is the private type for the RTC state. It must be cast compatible
* with struct rtc_lowerhalf_s.
*/
struct stm32_lowerhalf_s
{
/* This is the contained reference to the read-only, lower-half
* operations vtable (which may lie in FLASH or ROM)
*/
FAR const struct rtc_ops_s *ops;
/* Data following is private to this driver and not visible outside of
* this file.
*/
sem_t devsem; /* Threads can only exclusively access the RTC */
#ifdef CONFIG_RTC_ALARM
/* Alarm callback information */
struct stm32_cbinfo_s cbinfo[STM32_NALARMS];
#endif
#ifdef CONFIG_RTC_PERIODIC
/* Periodic wakeup information */
struct lower_setperiodic_s periodic;
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Prototypes for static methods in struct rtc_ops_s */
static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower,
FAR struct rtc_time *rtctime);
static int stm32_settime(FAR struct rtc_lowerhalf_s *lower,
FAR const struct rtc_time *rtctime);
static bool stm32_havesettime(FAR struct rtc_lowerhalf_s *lower);
#ifdef CONFIG_RTC_ALARM
static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setalarm_s *alarminfo);
static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setrelative_s *alarminfo);
static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower,
int alarmid);
static int stm32_rdalarm(FAR struct rtc_lowerhalf_s *lower,
FAR struct lower_rdalarm_s *alarminfo);
#endif
#ifdef CONFIG_RTC_PERIODIC
static int stm32_setperiodic(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setperiodic_s *alarminfo);
static int stm32_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* STM32 RTC driver operations */
static const struct rtc_ops_s g_rtc_ops =
{
.rdtime = stm32_rdtime,
.settime = stm32_settime,
.havesettime = stm32_havesettime,
#ifdef CONFIG_RTC_ALARM
.setalarm = stm32_setalarm,
.setrelative = stm32_setrelative,
.cancelalarm = stm32_cancelalarm,
.rdalarm = stm32_rdalarm,
#endif
#ifdef CONFIG_RTC_PERIODIC
.setperiodic = stm32_setperiodic,
.cancelperiodic = stm32_cancelperiodic,
#endif
#ifdef CONFIG_RTC_IOCTL
.ioctl = NULL,
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
.destroy = NULL,
#endif
};
/* STM32 RTC device state */
static struct stm32_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_alarm_callback
*
* Description:
* This is the function that is called from the RTC driver when the alarm
* goes off. It just invokes the upper half drivers callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid)
{
FAR struct stm32_lowerhalf_s *lower;
FAR struct stm32_cbinfo_s *cbinfo;
rtc_alarm_callback_t cb;
FAR void *priv;
DEBUGASSERT(arg != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
lower = (struct stm32_lowerhalf_s *)arg;
cbinfo = &lower->cbinfo[alarmid];
/* Sample and clear the callback information to minimize the window in
* time in which race conditions can occur.
*/
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (FAR void *)cbinfo->priv;
DEBUGASSERT(priv != NULL);
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, alarmid);
}
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: stm32_rdtime
*
* Description:
* Implements the rdtime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The location in which to return the current RTC time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower,
FAR struct rtc_time *rtctime)
{
FAR struct stm32_lowerhalf_s *priv;
int ret;
priv = (FAR struct stm32_lowerhalf_s *)lower;
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
#if defined(CONFIG_RTC_DATETIME)
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
ret = up_rtc_getdatetime((FAR struct tm *)rtctime);
#else
time_t timer;
/* The resolution of time is only 1 second */
timer = up_rtc_time();
/* Convert the one second epoch time to a struct tm */
if (!gmtime_r(&timer, (FAR struct tm *)rtctime))
{
int errcode = get_errno();
DEBUGASSERT(errcode > 0);
nxsem_post(&priv->devsem);
return -errcode;
}
#endif
nxsem_post(&priv->devsem);
return ret;
}
/****************************************************************************
* Name: stm32_settime
*
* Description:
* Implements the settime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The new time to set
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int stm32_settime(FAR struct rtc_lowerhalf_s *lower,
FAR const struct rtc_time *rtctime)
{
FAR struct stm32_lowerhalf_s *priv;
int ret;
priv = (FAR struct stm32_lowerhalf_s *)lower;
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
#ifdef CONFIG_RTC_DATETIME
/* This operation depends on the fact that struct rtc_time is cast
* compatible with struct tm.
*/
ret = stm32_rtc_setdatetime((FAR const struct tm *)rtctime);
#else
struct timespec ts;
/* Convert the struct rtc_time to a time_t. Here we assume that struct
* rtc_time is cast compatible with struct tm.
*/
ts.tv_sec = mktime((FAR struct tm *)rtctime);
ts.tv_nsec = 0;
/* Now set the time (to one second accuracy) */
ret = up_rtc_settime(&ts);
#endif
nxsem_post(&priv->devsem);
return ret;
}
/****************************************************************************
* Name: stm32_havesettime
*
* Description:
* Implements the havesettime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
*
* Returned Value:
* Returns true if RTC date-time have been previously set.
*
****************************************************************************/
static bool stm32_havesettime(FAR struct rtc_lowerhalf_s *lower)
{
return stm32_rtc_havesettime();
}
/****************************************************************************
* Name: stm32_setalarm
*
* Description:
* Set a new alarm. This function implements the setalarm() method of the
* RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setalarm_s *alarminfo)
{
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
struct alm_setalarm_s lowerinfo;
int ret;
/* ID0-> Alarm A; ID1 -> Alarm B */
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
priv = (FAR struct stm32_lowerhalf_s *)lower;
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
ret = -EINVAL;
if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
{
/* Remember the callback information */
cbinfo = &priv->cbinfo[alarminfo->id];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
cbinfo->id = alarminfo->id;
/* Set the alarm */
lowerinfo.as_id = alarminfo->id;
lowerinfo.as_cb = stm32_alarm_callback;
lowerinfo.as_arg = priv;
memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm));
/* And set the alarm */
ret = stm32_rtc_setalarm(&lowerinfo);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
}
nxsem_post(&priv->devsem);
return ret;
}
#endif
/****************************************************************************
* Name: stm32_setrelative
*
* Description:
* Set a new alarm relative to the current time. This function implements
* the setrelative() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setrelative_s *alarminfo)
{
struct lower_setalarm_s setalarm;
struct tm time;
time_t seconds;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) &&
alarminfo->reltime > 0)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
/* Get the current time in broken out format */
ret = up_rtc_getdatetime(&time);
if (ret >= 0)
{
/* Convert to seconds since the epoch */
seconds = mktime(&time);
/* Add the seconds offset. Add one to the number of seconds
* because we are unsure of the phase of the timer.
*/
seconds += (alarminfo->reltime + 1);
/* And convert the time back to broken out format */
(void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
setalarm.id = alarminfo->id;
setalarm.cb = alarminfo->cb;
setalarm.priv = alarminfo->priv;
ret = stm32_setalarm(lower, &setalarm);
}
sched_unlock();
}
return ret;
}
#endif
/****************************************************************************
* Name: stm32_cancelalarm
*
* Description:
* Cancel the current alarm. This function implements the cancelalarm()
* method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid)
{
FAR struct stm32_lowerhalf_s *priv;
FAR struct stm32_cbinfo_s *cbinfo;
int ret;
DEBUGASSERT(lower != NULL);
DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
priv = (FAR struct stm32_lowerhalf_s *)lower;
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
/* ID0-> Alarm A; ID1 -> Alarm B */
ret = -EINVAL;
if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB)
{
/* Nullify callback information to reduce window for race conditions */
cbinfo = &priv->cbinfo[alarmid];
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Then cancel the alarm */
ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid);
}
nxsem_post(&priv->devsem);
return ret;
}
#endif
/****************************************************************************
* Name: stm32_rdalarm
*
* Description:
* Query the RTC alarm.
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to query the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int stm32_rdalarm(FAR struct rtc_lowerhalf_s *lower,
FAR struct lower_rdalarm_s *alarminfo)
{
struct alm_rdalarm_s lowerinfo;
int ret = -EINVAL;
DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL);
DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
{
/* Disable pre-emption while we do this so that we don't have to worry
* about being suspended and working on an old time.
*/
sched_lock();
lowerinfo.ar_id = alarminfo->id;
lowerinfo.ar_time = alarminfo->time;
ret = stm32_rtc_rdalarm(&lowerinfo);
sched_unlock();
}
return ret;
}
#endif
/****************************************************************************
* Name: stm32_periodic_callback
*
* Description:
* This is the function that is called from the RTC driver when the
* periodic wakeup goes off. It just invokes the upper half driver's
* callback.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int stm32_periodic_callback(void)
{
FAR struct stm32_lowerhalf_s *lower;
struct lower_setperiodic_s *cbinfo;
rtc_wakeup_callback_t cb;
FAR void *priv;
lower = (FAR struct stm32_lowerhalf_s *)&g_rtc_lowerhalf;
cbinfo = &lower->periodic;
cb = (rtc_wakeup_callback_t)cbinfo->cb;
priv = (FAR void *)cbinfo->priv;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, 0);
}
return OK;
}
#endif /* CONFIG_RTC_PERIODIC */
/****************************************************************************
* Name: stm32_setperiodic
*
* Description:
* Set a new periodic wakeup relative to the current time, with a given
* period. This function implements the setperiodic() method of the RTC
* driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the wakeup activity
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int stm32_setperiodic(FAR struct rtc_lowerhalf_s *lower,
FAR const struct lower_setperiodic_s *alarminfo)
{
FAR struct stm32_lowerhalf_s *priv;
int ret;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
priv = (FAR struct stm32_lowerhalf_s *)lower;
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s));
ret = stm32_rtc_setperiodic(&alarminfo->period, stm32_periodic_callback);
nxsem_post(&priv->devsem);
return ret;
}
#endif
/****************************************************************************
* Name: stm32_cancelperiodic
*
* Description:
* Cancel the current periodic wakeup activity. This function implements
* the cancelperiodic() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
static int stm32_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id)
{
FAR struct stm32_lowerhalf_s *priv;
int ret;
DEBUGASSERT(lower != NULL);
priv = (FAR struct stm32_lowerhalf_s *)lower;
DEBUGASSERT(id == 0);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
}
ret = stm32_rtc_cancelperiodic();
nxsem_post(&priv->devsem);
return ret;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void)
{
nxsem_init(&g_rtc_lowerhalf.devsem, 0, 1);
return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}
#endif /* CONFIG_RTC_DRIVER */

2
arch/arm/src/stm32h7/stm32_sdmmc.c
View File

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32f7/stm32_sdmmc.c * arch/arm/src/stm32h7/stm32_sdmmc.c
* *
* Copyright (C) 2009, 2011-2017, 2019 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2017, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org> * Authors: Gregory Nutt <gnutt@nuttx.org>

2
arch/arm/src/stm32h7/stm32_sdmmc.h
View File

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32f7/stm32_sdmmc.h * arch/arm/src/stm32h7/stm32_sdmmc.h
* *
* Copyright (C) 2009, 2011, 2016, 2019 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011, 2016, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>

2
arch/arm/src/stm32h7/stm32_tim.c
View File

@ -1,5 +1,5 @@
/*************************************************************************** /***************************************************************************
* arm/arm/src/stm32f7/stm32_tim.c * arm/arm/src/stm32h7/stm32_tim.c
* *
* Copyright (C) 2011 Uros Platise. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Uros Platise <uros.platise@isotel.eu> * Author: Uros Platise <uros.platise@isotel.eu>

6
boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h
View File

@ -1,8 +1,9 @@
/************************************************************************************ /************************************************************************************
* boards/nucleo-h743zi/src/nucleo-h743zi.h * boards/nucleo-h743zi/src/nucleo-h743zi.h
* *
# Copyright (C) 2017 Gwenhael Goavec-Merou. All rights reserved. # Copyright (C) 2017, 2019 Gwenhael Goavec-Merou. All rights reserved.
# Author: Gwenhael Goavec-Merou<gwenhael.goavec-merou@trabucayre.com> # Authors: Gwenhael Goavec-Merou<gwenhael.goavec-merou@trabucayre.com>
* David Sidrane <david.sidrane@nscdg.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -59,6 +60,7 @@
# endif # endif
#endif #endif
#define HAVE_RTC_DRIVER 1
/* Configuration ********************************************************************/ /* Configuration ********************************************************************/
/* LED /* LED
* *

34
boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c
View File

@ -50,6 +50,11 @@
# include <nuttx/input/buttons.h> # include <nuttx/input/buttons.h>
#endif #endif
#ifdef HAVE_RTC_DRIVER
# include <nuttx/timers/rtc.h>
# include "stm32_rtc.h"
#endif
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
@ -133,6 +138,9 @@ static void stm32_i2ctool(void)
int stm32_bringup(void) int stm32_bringup(void)
{ {
int ret = OK; int ret = OK;
#ifdef HAVE_RTC_DRIVER
FAR struct rtc_lowerhalf_s *lower;
#endif
UNUSED(ret); UNUSED(ret);
@ -160,6 +168,32 @@ int stm32_bringup(void)
} }
#endif /* CONFIG_FS_PROCFS */ #endif /* CONFIG_FS_PROCFS */
#ifdef HAVE_RTC_DRIVER
/* Instantiate the STM32 lower-half RTC driver */
lower = stm32_rtc_lowerhalf();
if (!lower)
{
syslog(LOG_ERR,
"ERROR: Failed to instantiate the RTC lower-half driver\n");
return -ENOMEM;
}
else
{
/* Bind the lower half driver and register the combined RTC driver
* as /dev/rtc0
*/
ret = rtc_initialize(0, lower);
if (ret < 0)
{
syslog(LOG_ERR,
"ERROR: Failed to bind/register the RTC driver: %d\n", ret);
return ret;
}
}
#endif
#ifdef CONFIG_BUTTONS #ifdef CONFIG_BUTTONS
/* Register the BUTTON driver */ /* Register the BUTTON driver */