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xtensa/esp32s3: Move linker scripts to folder common to all boards

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-10-31 18:43:58 -03:00 committed by Petro Karashchenko
parent 3afc83abc7
commit 1befe6076f
15 changed files with 57 additions and 2990 deletions
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1
boards/xtensa/esp32s3/common/scripts/.gitignore vendored Normal file
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@ -0,0 +1 @@
/*.ld.tmp

8
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.template.ld → boards/xtensa/esp32s3/common/scripts/esp32s3_memory.ld
View File

@ -1,17 +1,13 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.template.ld
* boards/xtensa/esp32s3/common/scripts/esp32s3_memory.ld
* ESP32-S3 Linker Script Memory Layout
*
* This file describes the memory layout (memory blocks) as virtual
* memory addresses.
*
* esp32s3.common.ld contains output sections to link compiler output
* esp32s3_sections.ld contains output sections to link compiler output
* into these memory blocks.
*
* NOTE: That this is not the actual linker script but rather a "template"
* for the esp32s3_out.ld script. This template script is passed through
* the C preprocessor to include selected configuration options.
*
****************************************************************************/
#include <nuttx/config.h>

2
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_peripherals.ld → boards/xtensa/esp32s3/common/scripts/esp32s3_peripherals.ld
View File

@ -1,5 +1,5 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_peripherals.ld
* boards/xtensa/esp32s3/common/scripts/esp32s3_peripherals.ld
****************************************************************************/
PROVIDE ( UART0 = 0x60000000 );

8
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld → boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
View File

@ -1,4 +1,8 @@
/* ROM version variables for esp32s3
/****************************************************************************
* boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
****************************************************************************/
/* ROM version variables for ESP32-S3.
*
* These addresses should be compatible with any ROM version for this chip.
*
@ -7,7 +11,7 @@
_rom_chip_id = 0x40000570;
_rom_eco_version = 0x40000574;
/* ROM function interface esp32s3.rom.ld for esp32s3
/* ROM function interface esp32s3_rom.ld for esp32s3
*
*
* Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b

26
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3.ld → boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld
View File

@ -1,5 +1,5 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_flash.ld
* boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld
****************************************************************************/
/* Default entry point: */
@ -50,7 +50,7 @@ SECTIONS
*(.entry.text)
*(.init.literal)
*(.init)
} > iram0_0_seg
} >iram0_0_seg
.iram0.text :
{
@ -63,7 +63,7 @@ SECTIONS
. = ALIGN(4) + 16;
_iram_text = ABSOLUTE(.);
} > iram0_0_seg
} >iram0_0_seg
.dram0.dummy (NOLOAD) :
{
@ -72,7 +72,7 @@ SECTIONS
*/
. = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
} > dram0_0_seg
} >dram0_0_seg
/* Shared RAM */
@ -99,7 +99,7 @@ SECTIONS
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} > dram0_0_seg
} >dram0_0_seg
.noinit (NOLOAD) :
{
@ -112,7 +112,7 @@ SECTIONS
*(.noinit .noinit.*)
. = ALIGN(4);
} > dram0_0_seg
} >dram0_0_seg
.dram0.data :
{
@ -138,7 +138,7 @@ SECTIONS
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} > dram0_0_seg
} >dram0_0_seg
.flash.text :
{
@ -158,7 +158,7 @@ SECTIONS
. += 16;
_etext = .;
} > default_code_seg
} >default_code_seg
.flash_rodata_dummy (NOLOAD) :
{
@ -180,7 +180,7 @@ SECTIONS
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > default_rodata_seg
} >default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
@ -234,7 +234,7 @@ SECTIONS
_lit4_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
} > default_rodata_seg
} >default_rodata_seg
/* Marks the end of IRAM code segment */
@ -246,7 +246,7 @@ SECTIONS
. += 16;
. = ALIGN(256);
} > iram0_0_seg
} >iram0_0_seg
.iram0.data :
{
@ -254,7 +254,7 @@ SECTIONS
*(.iram.data)
*(.iram.data.*)
} > iram0_0_seg
} >iram0_0_seg
.iram0.bss (NOLOAD) :
{
@ -265,5 +265,5 @@ SECTIONS
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
} >iram0_0_seg
}

1
boards/xtensa/esp32s3/esp32s3-devkit/scripts/.gitignore vendored
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@ -1 +0,0 @@
/esp32s3_out.ld

21
boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
View File

@ -23,10 +23,23 @@ include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32s3/Config.mk
include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_out.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
ifneq ($(wildcard $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld),)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld
else
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld
endif
ifneq ($(wildcard $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld),)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld
else
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -fno-strength-reduce

269
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld
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@ -1,269 +0,0 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_flash.ld
****************************************************************************/
/* Default entry point: */
ENTRY(__start);
_diram_i_start = 0x40378000;
SECTIONS
{
/* Send .iram0 code to iram */
.iram0.vectors :
{
_iram_start = ABSOLUTE(.);
/* Vectors go to IRAM. */
_init_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN(16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram0_0_seg
.iram0.text :
{
/* Code marked as running out of IRAM */
*(.iram1 .iram1.*)
/* align + add 16B for CPU dummy speculative instr. fetch */
. = ALIGN(4) + 16;
_iram_text = ABSOLUTE(.);
} > iram0_0_seg
.dram0.dummy (NOLOAD) :
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
} > dram0_0_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
/* .bss initialized on power-up */
. = ALIGN(8);
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(COMMON)
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.share.mem)
*(.gnu.linkonce.b.*)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} > dram0_0_seg
.noinit (NOLOAD) :
{
/* This section contains data that is not initialized during load,
* or during the application's initialization sequence.
*/
. = ALIGN(4);
*(.noinit .noinit.*)
. = ALIGN(4);
} > dram0_0_seg
.dram0.data :
{
/* .data initialized on power-up in ROMed configurations. */
_sdata = ABSOLUTE(.);
KEEP (*(.data))
KEEP (*(.data.*))
KEEP (*(.gnu.linkonce.d.*))
KEEP (*(.data1))
KEEP (*(.sdata))
KEEP (*(.sdata.*))
KEEP (*(.gnu.linkonce.s.*))
KEEP (*(.sdata2))
KEEP (*(.sdata2.*))
KEEP (*(.gnu.linkonce.s2.*))
KEEP (*(.jcr))
*(.dram1 .dram1.*)
_edata = ABSOLUTE(.);
. = ALIGN(4);
/* Heap starts at the end of .data */
_sheap = ABSOLUTE(.);
} > dram0_0_seg
.flash.text :
{
_stext = .;
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/* CPU will try to prefetch up to 16 bytes of instructions.
* This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += 16;
_etext = .;
} > default_code_seg
.flash_rodata_dummy (NOLOAD) :
{
/* This dummy section represents the .flash.text section but in default_rodata_seg.
* Thus, it must have its alignment and (at least) its size.
*/
/* Start at the same alignment constraint than .flash.text */
. = ALIGN(ALIGNOF(.flash.text));
/* Create an empty gap as big as .flash.text section */
. = SIZEOF(.flash.text);
/* Prepare the alignment of the section above. Few bytes (0x20) must be
* added for the mapping header.
*/
. = ALIGN(0x10000) + 0x20;
_rodata_reserved_start = .;
} > default_rodata_seg
.flash.rodata : ALIGN(0x10)
{
_srodata = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = ALIGN(4);
/* C++ constructor and destructor tables, properly ordered: */
_sinit = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
_einit = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_erodata = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
_rodata_reserved_end = ABSOLUTE(.);
. = ALIGN(4);
} > default_rodata_seg
/* Marks the end of IRAM code segment */
.iram0.text_end (NOLOAD) :
{
/* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and
* 256B alignment for PMS split lines.
*/
. += 16;
. = ALIGN(256);
} > iram0_0_seg
.iram0.data :
{
. = ALIGN(4);
*(.iram.data)
*(.iram.data.*)
} > iram0_0_seg
.iram0.bss (NOLOAD) :
{
. = ALIGN(4);
*(.iram.bss)
*(.iram.bss.*)
. = ALIGN(4);
_iram_end = ABSOLUTE(.);
} > iram0_0_seg
}

111
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.template.ld
View File

@ -1,111 +0,0 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.template.ld
* ESP32-S3 Linker Script Memory Layout
*
* This file describes the memory layout (memory blocks) as virtual
* memory addresses.
*
* esp32s3.common.ld contains output sections to link compiler output
* into these memory blocks.
*
* NOTE: That this is not the actual linker script but rather a "template"
* for the elf32_out.ld script. This template script is passed through
* the C preprocessor to include selected configuration options.
*
****************************************************************************/
#include <nuttx/config.h>
#define SRAM_IRAM_START 0x40370000
#define SRAM_DIRAM_I_START 0x40378000
#define SRAM_IRAM_END 0x403ba000
#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
#define SRAM_DRAM_START 0x3fc88000
/* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET)
#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START)
#define ICACHE_SIZE 0x8000
#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE)
#define DCACHE_SIZE 0x10000
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
#ifdef CONFIG_ESP32S3_FLASH_4M
# define FLASH_SIZE 0x400000
#elif defined (CONFIG_ESP32S3_FLASH_8M)
# define FLASH_SIZE 0x800000
#elif defined (CONFIG_ESP32S3_FLASH_16M)
# define FLASH_SIZE 0x1000000
#endif
MEMORY
{
/* Below values assume the flash cache is on, and have the blocks this
* uses subtracted from the length of the various regions. The 'data access
* port' dram/drom regions map to the same iram/irom regions but are
* connected to the data port of the CPU and eg allow bytewise access.
*/
/* IRAM for CPU */
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE
/* Flash mapped instruction data. */
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
/* Shared data RAM, excluding memory reserved for bootloader and ROM
* bss/data/stack.
*/
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE
/* Flash mapped constant data */
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000
/* RTC slow memory (data accessible). Persists over deep sleep.
* Start of RTC slow memory is reserved for ULP co-processor code + data,
* if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
}
#ifdef CONFIG_ESP32S3_RUN_IRAM
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32S3_RUN_IRAM */

47
boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_peripherals.ld
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@ -1,47 +0,0 @@
/****************************************************************************
* boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_peripherals.ld
****************************************************************************/
PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( SPIMEM1 = 0x60002000 );
PROVIDE ( SPIMEM0 = 0x60003000 );
PROVIDE ( GPIO = 0x60004000 );
PROVIDE ( SIGMADELTA = 0x60004f00 );
PROVIDE ( RTCCNTL = 0x60008000 );
PROVIDE ( RTCIO = 0x60008400 );
PROVIDE ( SENS = 0x60008800 );
PROVIDE ( HINF = 0x6000B000 );
PROVIDE ( I2S0 = 0x6000F000 );
PROVIDE ( I2S1 = 0x6002D000 );
PROVIDE ( UART1 = 0x60010000 );
PROVIDE ( I2C0 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( UHCI1 = 0x60014000 );
PROVIDE ( HOST = 0x60015000 );
PROVIDE ( RMT = 0x60016000 );
PROVIDE ( RMTMEM = 0x60016800 );
PROVIDE ( PCNT = 0x60017000 );
PROVIDE ( SLC = 0x60018000 );
PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( MCPWM0 = 0x6001E000 );
PROVIDE ( MCPWM1 = 0x6002C000 );
PROVIDE ( MCP = 0x600c3000 );
PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2 = 0x60024000 );
PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( I2C1 = 0x60027000 );
PROVIDE ( SDMMC = 0x60028000 );
PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( UART2 = 0x6002E000 );
PROVIDE ( DMA = 0x6003F000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( LCD_CAM = 0x60041000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60038000 );
PROVIDE ( USB0 = 0x60080000 );
PROVIDE ( USBH = 0x60080000 );
PROVIDE ( USB_WRAP = 0x60039000 );

17
boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs
View File

@ -20,10 +20,6 @@
include $(TOPDIR)/Make.defs
SCRIPTDIR = $(BOARD_DIR)$(DELIM)scripts
CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h
CSRCS = esp32s3_boot.c esp32s3_bringup.c
ifeq ($(CONFIG_BOARDCTL),y)
@ -49,19 +45,6 @@ ifeq ($(CONFIG_LCD_ST7735),y)
CSRCS += esp32s3_st7735.c
endif
SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32s3.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32s3_out.ld
.PHONY = context distclean
$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE)
$(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@
context:: $(SCRIPTOUT)
distclean::
$(call DELFILE, $(SCRIPTOUT))
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)

1
boards/xtensa/esp32s3/esp32s3-eye/scripts/.gitignore vendored
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@ -1 +0,0 @@
/esp32s3_out.ld

21
boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
View File

@ -23,10 +23,23 @@ include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32s3/Config.mk
include $(TOPDIR)/arch/xtensa/src/lx7/Toolchain.defs
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_out.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_peripherals.ld
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld
ifneq ($(wildcard $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld),)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld
else
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_memory.ld
endif
ifneq ($(wildcard $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld),)
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld
else
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_sections.ld
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += -fno-strength-reduce

2497
boards/xtensa/esp32s3/esp32s3-eye/scripts/esp32s3_rom.ld
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File diff suppressed because it is too large Load Diff

17
boards/xtensa/esp32s3/esp32s3-eye/src/Make.defs
View File

@ -20,10 +20,6 @@
include $(TOPDIR)/Make.defs
SCRIPTDIR = $(BOARD_DIR)$(DELIM)scripts
CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h
CSRCS = esp32s3_boot.c esp32s3_bringup.c
ifeq ($(CONFIG_BOARDCTL),y)
@ -33,19 +29,6 @@ CSRCS += esp32s3_reset.c
endif
endif
SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32s3.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32s3_out.ld
.PHONY = context distclean
$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE)
$(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@
context:: $(SCRIPTOUT)
distclean::
$(call DELFILE, $(SCRIPTOUT))
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)