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Fix SRAM1 base address

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2530 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-01-30 04:43:54 +00:00
parent 04aba9fc46
commit 1c0703d867
2 changed files with 16 additions and 13 deletions
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11
configs/sam3u-ek/ostest/defconfig
View File

@ -1,7 +1,7 @@
############################################################################
# configs/sam3u-ek/ostest/defconfig
#
# Copyright (C) 2009 Gregory Nutt. All rights reserved.
# Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
#
# Redistribution and use in source and binary forms, with or without
@ -73,11 +73,11 @@ CONFIG_ARCH=arm
CONFIG_ARCH_ARM=y
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP=sam3u
CONFIG_ARCH_CHIP_AT91SAM3U4=y
CONFIG_ARCH_CHIP_AT91SAM3U4E=y
CONFIG_ARCH_BOARD=sam3u-ek
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_DRAM_SIZE=0x0000c000
CONFIG_BOARD_LOOPSPERMSEC=4768
CONFIG_DRAM_SIZE=0x00008000
CONFIG_DRAM_START=0x20000000
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO=y
@ -105,6 +105,7 @@ CONFIG_SAM3U_USART0=n
CONFIG_SAM3U_USART1=n
CONFIG_SAM3U_USART2=n
CONFIG_SAM3U_USART3=n
CONFIG_SAM3U_NAND=n
#
# Some subsystems can be configured to operate in different ways..
@ -293,7 +294,7 @@ CONFIG_EXAMPLE=ostest
CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_SYMBOLS=n
CONFIG_MM_REGIONS=1
CONFIG_MM_REGIONS=3
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_INSTRUMENTATION=n

18
configs/sam3u-ek/ostest/ld.script
View File

@ -33,8 +33,9 @@
*
****************************************************************************/
/* The AT91SAM3U-4 has 256Kb of FLASH beginning at address 0x0008:0000 and
* 48Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH,
/* The AT91SAM3U-4 has 256Kb of FLASH beginning at address 0x0008:0000,
* 32Kb of SRAM beginning at address 0x2000:0000, and 16Kb of SRAM beginning
* at address 0x2008:000 (used only for heap). When booting from FLASH,
* FLASH memory is aliased to address 0x0000:0000 where the code expects to
* begin execution by jumping to the entry point in the 0x0800:0000 address
* range.
@ -42,8 +43,9 @@
MEMORY
{
flash (rx) : ORIGIN = 0x00080000, LENGTH = 256K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
flash (rx) : ORIGIN = 0x00080000, LENGTH = 256K
sram1 (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
sram2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16K
}
OUTPUT_ARCH(arm)
@ -74,17 +76,17 @@ SECTIONS
*(.gnu.linkonce.d.*)
CONSTRUCTORS
_edata = ABSOLUTE(.);
} > sram AT > flash
} > sram1 AT > flash
.ARM.extab : {
*(.ARM.extab*)
} >sram
} >sram1
.ARM.exidx : {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} >sram
} >sram1
.bss : { /* BSS */
_sbss = ABSOLUTE(.);
@ -92,7 +94,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > sram
} > sram1
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }