Merged in plwm/nuttx/stm32f746g-disco-lcd (pull request #661)
add support for STM32F746G-disco board LCD Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
parent
e2c442cdcb
commit
1c76e10c06
@ -59,6 +59,7 @@
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#include "up_internal.h"
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#include "chip/stm32_ltdc.h"
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#include "chip/stm32_dma2d.h"
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#include "stm32_rcc.h"
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#include "stm32_gpio.h"
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#include "stm32_ltdc.h"
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#include "stm32_dma2d.h"
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@ -257,6 +258,7 @@
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#else
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# define STM32_LTDC_L2_FBSIZE (0)
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# define STM32_LTDC_L2_BPP 0
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#endif
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/* Total memory used for framebuffers */
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78
configs/stm32f746g-disco/fb/README.txt
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78
configs/stm32f746g-disco/fb/README.txt
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@ -0,0 +1,78 @@
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README.txt
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==========
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STM32F746G-DISCO LTDC Framebuffer demo example
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Preparation
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-----------
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As of writing this text, SDRAM support is not implemented for this board.
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Therefore to make this demo work following changes are required to heap
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management function:
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diff --git a/stm32_allocateheap.c b/stm32_allocateheap.c
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--- a/stm32_allocateheap.c
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+++ b/stm32_allocateheap.c
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@@ -93,7 +93,7 @@
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/* Set the start and end of SRAM1 and SRAM2 */
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#define SRAM1_START STM32_SRAM1_BASE
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-#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE)
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+#define SRAM1_END (SRAM1_START + 131072)
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#define SRAM2_START STM32_SRAM2_BASE
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#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE)
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@@ -385,17 +385,17 @@ void up_addregion(void)
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/* Allow user-mode access to the STM32F20xxx/STM32F40xxx SRAM2 heap */
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- stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START); */
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#endif
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/* Colorize the heap for debug */
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- up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */
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/* Add the STM32F20xxx/STM32F40xxx SRAM2 user heap region. */
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- kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */
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#ifdef HAVE_DTCM
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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Configure and build
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-------------------
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tools/configure.sh stm32f746g-disco/fb
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make
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Configuration
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------------
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This configuration provides 1 LTDC with
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8pp CLUT pixel format and a resolution of 480x272.
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Loading
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-------
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st-flash write nuttx.bin 0x8000000
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Executing
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---------
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The ltdc is initialized during boot up. Interaction with NSH is via the serial
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console at 115200 8N1 baud. From the nsh comandline execute the fb example:
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nsh> fb
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The test will put a pattern of concentric squares in the framebuffer and
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terminate.
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63
configs/stm32f746g-disco/fb/defconfig
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63
configs/stm32f746g-disco/fb/defconfig
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@ -0,0 +1,63 @@
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# CONFIG_ARCH_FPU is not set
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_STM32F7_LTDC_L2 is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="stm32f746g-disco"
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CONFIG_ARCH_BOARD_STM32F746G_DISCO=y
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CONFIG_ARCH_BUTTONS=y
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CONFIG_ARCH_CHIP_STM32F746NG=y
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CONFIG_ARCH_CHIP_STM32F7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
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CONFIG_BOARD_INITIALIZE=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DISABLE_POLL=y
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CONFIG_DRIVERS_VIDEO=y
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CONFIG_EXAMPLES_FB=y
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CONFIG_EXAMPLES_NSH=y
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CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_HOST_WINDOWS=y
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LCD=y
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CONFIG_MAX_TASKS=16
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CONFIG_MAX_WDOGPARMS=2
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CONFIG_MM_REGIONS=3
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CONFIG_NFILE_DESCRIPTORS=8
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CONFIG_NFILE_STREAMS=8
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_MQ_MSGS=4
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_PREALLOC_WDOGS=4
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SPI=y
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CONFIG_START_DAY=6
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2011
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CONFIG_STM32F7_LTDC=y
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CONFIG_STM32F7_LTDC_FB_BASE=0x20030000
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CONFIG_STM32F7_LTDC_FB_SIZE=130560
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CONFIG_STM32F7_LTDC_INTERFACE=y
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CONFIG_STM32F7_LTDC_L1_L8=y
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CONFIG_STM32F7_USART1=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USART1_SERIAL_CONSOLE=y
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_VIDEO_FB=y
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CONFIG_WDOG_INTRESERVE=0
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@ -151,16 +151,16 @@
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/* Configure factors for PLLSAI clock */
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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@ -374,4 +374,65 @@
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
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/* LCD definitions ******************************************************************/
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#define BOARD_LTDC_WIDTH 480
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#define BOARD_LTDC_HEIGHT 272
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#define BOARD_LTDC_OUTPUT_BPP 24
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#define BOARD_LTDC_HFP 32
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#define BOARD_LTDC_HBP 13
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#define BOARD_LTDC_VFP 2
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#define BOARD_LTDC_VBP 2
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#define BOARD_LTDC_HSYNC 41
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#define BOARD_LTDC_VSYNC 10
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#define BOARD_LTDC_PLLSAIN 192
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#define BOARD_LTDC_PLLSAIR 5
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/* Pixel Clock Polarity */
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#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */
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/* Data Enable Polarity */
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#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */
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/* Vertical Sync Polarity */
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#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */
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/* Horicontal Sync Polarity */
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#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
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/* GPIO pinset */
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#define GPIO_LTDC_PINS 24 /* 24-bit display */
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#define GPIO_LTDC_R0 GPIO_LTDC_R0_3
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#define GPIO_LTDC_R1 GPIO_LTDC_R1_3
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#define GPIO_LTDC_R2 GPIO_LTDC_R2_4
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#define GPIO_LTDC_R3 GPIO_LTDC_R3_3
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#define GPIO_LTDC_R4 GPIO_LTDC_R4_4
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#define GPIO_LTDC_R5 GPIO_LTDC_R5_4
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#define GPIO_LTDC_R6 GPIO_LTDC_R6_4
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#define GPIO_LTDC_R7 GPIO_LTDC_R7_3
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#define GPIO_LTDC_G0 GPIO_LTDC_G0_2
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#define GPIO_LTDC_G1 GPIO_LTDC_G1_2
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#define GPIO_LTDC_G2 GPIO_LTDC_G2_3
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#define GPIO_LTDC_G3 GPIO_LTDC_G3_4
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#define GPIO_LTDC_G4 GPIO_LTDC_G4_3
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#define GPIO_LTDC_G5 GPIO_LTDC_G5_3
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#define GPIO_LTDC_G6 GPIO_LTDC_G6_3
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#define GPIO_LTDC_G7 GPIO_LTDC_G7_3
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#define GPIO_LTDC_B0 GPIO_LTDC_B0_1
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#define GPIO_LTDC_B1 GPIO_LTDC_B1_2
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#define GPIO_LTDC_B2 GPIO_LTDC_B2_3
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#define GPIO_LTDC_B3 GPIO_LTDC_B3_3
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#define GPIO_LTDC_B4 GPIO_LTDC_B4_4
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#define GPIO_LTDC_B5 GPIO_LTDC_B5_3
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#define GPIO_LTDC_B6 GPIO_LTDC_B6_3
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#define GPIO_LTDC_B7 GPIO_LTDC_B7_3
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#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_2
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#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_2
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#define GPIO_LTDC_DE GPIO_LTDC_DE_3
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#define GPIO_LTDC_CLK GPIO_LTDC_CLK_3
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#endif /* __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H */
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@ -64,4 +64,8 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y)
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CSRCS += stm32_sporadic.c
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endif
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ifeq ($(CONFIG_STM32F7_LTDC),y)
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CSRCS += stm32_lcd.c
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endif
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include $(TOPDIR)/configs/Board.mk
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# include <nuttx/input/buttons.h>
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#endif
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#ifdef CONFIG_VIDEO_FB
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# include <nuttx/video/fb.h>
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -70,9 +74,10 @@
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int stm32_bringup(void)
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{
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#ifdef CONFIG_FS_PROCFS
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int ret;
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#ifdef CONFIG_FS_PROCFS
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#ifdef CONFIG_STM32_CCM_PROCFS
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/* Register the CCM procfs entry. This must be done before the procfs is
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* mounted.
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@ -114,5 +119,15 @@ int stm32_bringup(void)
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}
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#endif
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#ifdef CONFIG_VIDEO_FB
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/* Initialize and register the framebuffer driver */
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ret = fb_register(0, 0);
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if (ret < 0)
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{
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syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
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}
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#endif
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return OK;
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}
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130
configs/stm32f746g-disco/src/stm32_lcd.c
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130
configs/stm32f746g-disco/src/stm32_lcd.c
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@ -0,0 +1,130 @@
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/************************************************************************************
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* configs/stm32f746g-disco/src/stm32_lcd.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <nuttx/video/fb.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "stm32f746g-disco.h"
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#include "stm32_gpio.h"
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#include "stm32_ltdc.h"
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#ifdef CONFIG_STM32F7_LTDC
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/****************************************************************************
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* Name: up_fbinitialize
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*
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* Description:
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* Initialize the framebuffer video hardware associated with the display.
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*
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* Input Parameters:
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* display - In the case of hardware with multiple displays, this
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* specifies the display. Normally this is zero.
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*
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* Returned Value:
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* Zero is returned on success; a negated errno value is returned on any
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* failure.
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*
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****************************************************************************/
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int up_fbinitialize(int display)
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{
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/* Custom LCD display with RGB interface */
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stm32_configgpio(GPIO_LCD_DISP);
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stm32_configgpio(GPIO_LCD_BL);
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stm32_gpiowrite(GPIO_LCD_DISP, true);
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stm32_gpiowrite(GPIO_LCD_BL, true);
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return stm32_ltdcinitialize();
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}
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/****************************************************************************
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* Name: up_fbgetvplane
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*
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* Description:
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* Return a a reference to the framebuffer object for the specified video
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* plane of the specified plane. Many OSDs support multiple planes of video.
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*
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* Input Parameters:
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* display - In the case of hardware with multiple displays, this
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* specifies the display. Normally this is zero.
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* vplane - Identifies the plane being queried.
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*
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* Returned Value:
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* A non-NULL pointer to the frame buffer access structure is returned on
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* success; NULL is returned on any failure.
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*
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****************************************************************************/
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FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane)
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{
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return stm32_ltdcgetvplane(vplane);
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}
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/****************************************************************************
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* Name: up_fbuninitialize
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*
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* Description:
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* Uninitialize the framebuffer support for the specified display.
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*
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* Input Parameters:
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* display - In the case of hardware with multiple displays, this
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* specifies the display. Normally this is zero.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void up_fbuninitialize(int display)
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{
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stm32_gpiowrite(GPIO_LCD_DISP, false);
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stm32_gpiowrite(GPIO_LCD_BL, false);
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stm32_ltdcuninitialize();
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}
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#endif /* CONFIG_STM32_LTDC */
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@ -94,6 +94,11 @@
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#define GPIO_SCHED_RUNNING (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
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GPIO_PORTG | GPIO_PIN7)
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#define GPIO_LCD_DISP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
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GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN12)
|
||||
|
||||
#define GPIO_LCD_BL (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTK|GPIO_PIN3)
|
||||
/****************************************************************************************************
|
||||
* Public data
|
||||
****************************************************************************************************/
|
||||
|
Loading…
Reference in New Issue
Block a user