From 1c8a661c9fc6b6b821f52028e43fe77f5eeadfba Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Fri, 17 Jun 2022 10:03:32 +0400 Subject: [PATCH] boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h: Update memory initialization parameters Sync some of the AXI configuration and DDR training parameters with the manufacturer's defaults. The TIP_CFG parameter correction helps with DDR training failures on some individual boards The AXI end address values fix early random crash in power-on boot on some individual boards Signed-off-by: Jukka Laitinen --- .../risc-v/mpfs/m100pfsevp/include/board_liberodefs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h index 0d776674bb..ec80a467a3 100644 --- a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h +++ b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h @@ -474,10 +474,10 @@ #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1 0x00000000 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0 0x00000000 #define LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1 0x00000000 -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 0xffffffff -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 0x00000003 -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 0xffffffff -#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 0x00000003 +#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 0x7fffffff +#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 0x00000000 +#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 0x7fffffff +#define LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 0x00000000 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0 0x00000000 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1 0x00000000 #define LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0 0x00000000 @@ -575,7 +575,7 @@ #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0 -#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02B +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02A #define LIBERO_SETTING_DDR_32_CACHE 0x80000000 #define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000