SAM3/4: Fleshing out environment to support USB device (UDP)
This commit is contained in:
Gregory Nutt
parent
587ade144e
commit
1cde363251
@ -570,7 +570,7 @@ config SAM34_UDPHS
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config SAM34_UOTGHS
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bool "USB OTG High Speed (UOTGHS)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X
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depends on ARCH_CHIP_SAM3A || ARCH_CHIP_SAM3X
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config SAM34_USBC
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bool "USB 2.0 Interface (USBC)"
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@ -1129,6 +1129,17 @@ config SAM34_EMAC_ISETH0
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endmenu # EMAC device driver options
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endif # SAM34_EMAC
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if SAM34_UDP
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menu "USB Full Speed Device Controller driver (DCD) options"
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config SAM34_UDP_REGDEBUG
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bool "Enable low-level UPPHS register debug"
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default n
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depends on DEBUG
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endmenu # USB Full Speed Device Controller driver (DCD) options
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endif # SAM34_UDP
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if SAM34_WDT
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comment "AT91SAM3/4 Watchdog Configuration"|
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@ -108,6 +108,10 @@ ifeq ($(CONFIG_SAM34_EMAC),y)
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CHIP_CSRCS += sam_emac.c
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endif
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ifeq ($(CONFIG_SAM34_UDP),y)
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CHIP_CSRCS += sam_udp.c
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endif
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ifeq ($(CONFIG_SAM34_HSMCI),y)
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CHIP_CSRCS += sam_hsmci.c
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endif
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@ -49,8 +49,32 @@
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* General Definitions ******************************************************************/
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/* Capabilities and characteristics of endpoints
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*
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* EP EP BANKS EP SIZE EP TYPE
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* --- --------- --------- ---------
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* 0 1 64 Control/Bulk/Interrupt
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* 1 2 64 Bulk/Iso/Interrupt
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* 2 2 64 Bulk/Iso/Interrupt
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* 3 1 64 Control/Bulk/Interrupt
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* 4 2 512 Bulk/Iso/Interrupt
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* 5 2 612 Bulk/Iso/Interrupt
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* 6 2 64 Bulk/Iso/Interrupt
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* 7 2 64 Bulk/Iso/Interrupt
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*/
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/* UDP register offsets ***************************************************************/
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#define SAM_UDP_NENDPOINTS 8 /* EP0-7 */
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#define SAM_UDP_MAXPACKETSIZE(ep) ((((unsigned)(ep) & 6) == 4) ? 512 : 64)
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#define SAM_UDP_NBANKS(ep) (((unsigned)(ep) == 0 || (unsigned)(ep) == 3) ? 1 : 2)
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#define SAM_UDP_CONTROL(ep) (((unsigned)(ep) == 0 || (unsigned)(ep) == 3))
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#define SAM_UDP_BULK(ep) (true)
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#define SAM_UDP_ISOCHRONOUS(ep) (((unsigned)(ep) != 0 && (unsigned)(ep) != 3))
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#define SAM_UDP_INTERRUPT(ep) (true)
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/* UDP register offsets *****************************************************************/
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/* Global Registers */
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#define SAM_UDP_FRMNUM_OFFSET 0x0000 /* UDP Frame Number Register */
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#define SAM_UDP_GLBSTAT_OFFSET 0x0004 /* UDP Global State Register */
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@ -62,10 +86,9 @@
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#define SAM_UDP_ISR_OFFSET 0x001c /* UDP Interrupt Status Register */
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#define SAM_UDP_ICR_OFFSET 0x0020 /* UDP Interrupt Clear Register */
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/* 0x0024: Reserved */
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#define SAM_UDP_RSTEP_OFFSET 0x001c /* UDP Reset Endpoint Regis */
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#define SAM_UDP_RSTEP_OFFSET 0x001c /* UDP Reset Endpoint Register */
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/* 0x002c: Reserved */
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/* Endpoint 0-7 registers */
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/* Endpoint registers */
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#define SAM_UDPEP_CSR_OFFSET(n) (0x0030+((n)<<2))
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# define SAM_UDPEP_CSR0_OFFSET 0x0030 /* Endpoint Control and Status Register 0 */
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@ -89,7 +112,9 @@
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#define SAM_UDP_TXVC_OFFSET 0x0074 /* Transceiver Control Register */
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/* 0x0078-0x00fc: Reserved */
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/* UDP register addresses *************************************************************/
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/* UDP register addresses ***************************************************************/
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/* Global Registers */
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#define SAM_UDP_FRMNUM (SAM_UDP_BASE+SAM_UDP_FRMNUM_OFFSET)
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#define SAM_UDP_GLBSTAT (SAM_UDP_BASE+SAM_UDP_GLBSTAT_OFFSET)
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@ -98,10 +123,10 @@
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#define SAM_UDP_IDR (SAM_UDP_BASE+SAM_UDP_IDR_OFFSET)
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#define SAM_UDP_IMR (SAM_UDP_BASE+SAM_UDP_IMR_OFFSET)
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#define SAM_UDP_ISR (SAM_UDP_BASE+SAM_UDP_ISR_OFFSET)
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#define SAM_UDP_ICR (SAM_UDP_BASE+ SAM_UDP_ICR_OFFSET)
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#define SAM_UDP_ICR (SAM_UDP_BASE+SAM_UDP_ICR_OFFSET)
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#define SAM_UDP_RSTEP (SAM_UDP_BASE+SAM_UDP_RSTEP_OFFSET)
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/* Endpoint 0-7 registers */
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/* Endpoint registers */
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#define SAM_UDPEP_CSR(n) (SAM_UDP_BASE+SAM_UDPEP_CSR_OFFSET(n))
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# define SAM_UDPEP_CSR0 (SAM_UDP_BASE+SAM_UDPEP_CSR0_OFFSET)
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@ -124,7 +149,9 @@
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#define SAM_UDP_TXVC (SAM_UDP_BASE+SAM_UDP_TXVC_OFFSET)
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/* UDP register bit definitions *******************************************************/
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/* UDP register bit definitions *********************************************************/
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/* Global Registers */
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/* UDP Frame Number Register */
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@ -145,6 +172,7 @@
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#define UDP_FADDR_SHIFT (0) /* Bits 0-6: Function Address Value */
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#define UDP_FADDR_MASK (0x0000007f)
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# define UDP_FADDR(n) ((uint32_t)(n))
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#define UDP_FADDR_FEN (1 << 8) /* Bit 8: Function Enable */
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/* UDP Interrupt Enable, UDP Interrupt Disable, UDP Interrupt Mask, UDP Interrupt
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@ -152,22 +180,24 @@
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*/
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#define UDP_INT_EP(n) (1 << (n))
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# define UDP_INT_EP0 (1 << 0) /* Bit 0: Enable Endpoint 0 Interrupt (Not ICR) */
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# define UDP_INT_EP1 (1 << 1) /* Bit 1: Enable Endpoint 1 Interrupt (Not ICR) */
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# define UDP_INT_EP2 (1 << 2) /* Bit 2: Enable Endpoint 2 Interrupt (Not ICR) */
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# define UDP_INT_EP3 (1 << 3) /* Bit 3: Enable Endpoint 3 Interrupt (Not ICR) */
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# define UDP_INT_EP4 (1 << 4) /* Bit 4: Enable Endpoint 4 Interrupt (Not ICR) */
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# define UDP_INT_EP5 (1 << 5) /* Bit 5: Enable Endpoint 5 Interrupt (Not ICR) */
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# define UDP_INT_EP6 (1 << 6) /* Bit 6: Enable Endpoint 6 Interrupt (Not ICR) */
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# define UDP_INT_EP7 (1 << 7) /* Bit 7: Enable Endpoint 7 Interrupt (Not ICR) */
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#define UDP_INT_RXSUSP (1 << 8) /* Bit 8: Enable UDP Suspend Interrupt */
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#define UDP_INT_RXRSM (1 << 9) /* Bit 9: Enable UDP Resume Interrupt */
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# define UDP_INT_EP0 (1 << 0) /* Bit 0: Endpoint 0 Interrupt (Not ICR) */
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# define UDP_INT_EP1 (1 << 1) /* Bit 1: Endpoint 1 Interrupt (Not ICR) */
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# define UDP_INT_EP2 (1 << 2) /* Bit 2: Endpoint 2 Interrupt (Not ICR) */
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# define UDP_INT_EP3 (1 << 3) /* Bit 3: Endpoint 3 Interrupt (Not ICR) */
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# define UDP_INT_EP4 (1 << 4) /* Bit 4: Endpoint 4 Interrupt (Not ICR) */
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# define UDP_INT_EP5 (1 << 5) /* Bit 5: Endpoint 5 Interrupt (Not ICR) */
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# define UDP_INT_EP6 (1 << 6) /* Bit 6: Endpoint 6 Interrupt (Not ICR) */
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# define UDP_INT_EP7 (1 << 7) /* Bit 7: Endpoint 7 Interrupt (Not ICR) */
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#define UDP_INT_RXSUSP (1 << 8) /* Bit 8: UDP Suspend Interrupt */
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#define UDP_INT_RXRSM (1 << 9) /* Bit 9: UDP Resume Interrupt */
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#define UDP_INT_EXTRSM (1 << 10) /* Bit 10: */
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#define UDP_INT_SOF (1 << 11) /* Bit 11: Enable Start Of Frame Interrupt */
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#define UDP_INT_SOF (1 << 11) /* Bit 11: Start Of Frame Interrupt */
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#define UDP_ISR_ENDBUSRES (1 << 12) /* Bit 12: End of BUS Reset Interrupt Status (ISR and ICR only) */
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#define UDP_INT_WAKEUP (1 << 13) /* Bit 13: Enable UDP bus Wake-up Interrupt */
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#define UDP_INT_WAKEUP (1 << 13) /* Bit 13: UDP bus Wake-up Interrupt */
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/* UDP Reset Endpoint Regis */
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#define UDP_INT_ALL (0x00003fff)
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/* UDP Reset Endpoint Register */
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#define UDP_RSTEP(n) (1 << (n))
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# define UDP_RSTEP0 (1 << 0) /* Bit 0: Reset Endpoint 0 */
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@ -179,7 +209,7 @@
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# define UDP_RSTEP6 (1 << 6) /* Bit 6: Reset Endpoint 6 */
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# define UDP_RSTEP7 (1 << 7) /* Bit 7: Reset Endpoint 7 */
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/* Endpoint 0-7 registers */
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/* Endpoint registers */
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/* Endpoint Control and Status Registers */
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#define UDPEP_CSR_TXCOMP (1 << 0) /* Bit 0: Generates an IN packet with data */
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@ -227,4 +257,3 @@
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDP_H */
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@ -88,7 +88,7 @@
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#define SAM_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */
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#define SAM_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */
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#define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
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#define SAM_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
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#define SAM_UDPHSDMA_STATUS_OFFSET 0x0c /* UDPHS DMA Channel Status Register */
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/* UDPHS register addresses *************************************************************/
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@ -217,12 +217,12 @@
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#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT10 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT11 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT12 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT13 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT14 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */
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#define UDPHS_IPFEATURES_ISOEPT15 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */
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/* UDPHS Endpoint Configuration Register (0-6) */
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@ -231,7 +231,7 @@
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# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */
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# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */
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# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */
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# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */
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# define UDPHSEP_CFG_SIZE_64b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */
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# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */
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# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */
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# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */
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@ -330,7 +330,7 @@
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#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT)
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#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */
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#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT)
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#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet
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#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet */
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/* UDPHS DMA Channel Control Register */
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@ -237,13 +237,32 @@ static inline void sam_pmcsetup(void)
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#ifdef CONFIG_USBDEV
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/* Setup UTMI for USB and wait for LOCKU */
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#ifdef CONFIG_USBDEV
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#ifdef SAM_PMC_CKGR_UCKR
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/* This MCU has a USB PLL. Configure the UPLL and wait for it to lock. */
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regval = getreg32(SAM_PMC_CKGR_UCKR);
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regval |= BOARD_CKGR_UCKR;
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putreg32(regval, SAM_PMC_CKGR_UCKR);
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sam_pmcwait(PMC_INT_LOCKU);
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#else
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/* This board does not have a UPLL. Use the output of PLLA or PLLA
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* (depending on USBS) and setup the PLL divisor to generate the 48MHz
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* USB clock.
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*/
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regval = (BOARD_PMC_USBS | BOARD_PMC_USBDIV);
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putreg32(regval, SAM_PMC_USB);
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/* Set the UDP bit in the SCER1 register to enable the USB clock output */
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regval = getreg32(SAM_PMC_SCER);
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regval |= PMC_UDP;
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putreg32(regval, SAM_PMC_SCER);
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#endif
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#endif
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/* Switch to the fast clock and wait for MCKRDY */
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@ -225,7 +225,6 @@ config SAMA5_UHPHS
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config SAMA5_UDPHS
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bool "USB Device High Speed (UDPHS)"
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default n
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depends on SAMA5_HAVE_GMAC
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config SAMA5_GMAC
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bool "Gigabit Ethernet MAC (GMAC)"
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@ -869,7 +868,7 @@ choice
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prompt "GMAC Speed"
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default SAMA5_GMAC_ETH100MBPS
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---help---
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If autonegation is not used, then you must select the fixed speed
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If autonegotiation is not used, then you must select the fixed speed
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of the PHY
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config SAMA5_GMAC_ETH10MBPS
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@ -1512,9 +1511,9 @@ config SAMA5_SSC0_MCKDIV_SAMPLERATE
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depends on SAMA5_SSC0_RX_MCKDIV || SAMA5_SSC0_TX_MCKDIV
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---help---
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If the either the receiver or transmitter clock is provided by MCK/2 divided
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down, then the samplerate must be provided. The bitrate will be the product
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down, then the sample rate must be provided. The bit rate will be the product
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of the sample rate and the data width. The SSC driver will determine the best
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divider to obtain that bitrate (up to 4095). If the bitrate can be realized
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divider to obtain that bit rate (up to 4095). If the bit rate can be realized
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by dividing down the MCK/2, a compile time error will occur.
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config SAMA5_SSC0_LOOPBACK
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@ -1524,7 +1523,7 @@ config SAMA5_SSC0_LOOPBACK
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---help---
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If both the receiver and transmitter are enabled, then the SSC can
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be configured in loopback mode. This setting selects SSC loopback
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and will cause the LOOP bit to be set in the SSC_RFMR regsiter. In
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and will cause the LOOP bit to be set in the SSC_RFMR register. In
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this case, RD is connected to TD, RF is connected to TF and RK is
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connected to TK.
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@ -1646,9 +1645,9 @@ config SAMA5_SSC1_MCKDIV_SAMPLERATE
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depends on SAMA5_SSC1_RX_MCKDIV || SAMA5_SSC1_TX_MCKDIV
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---help---
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If the either the receiver or transmitter clock is provided by MCK/2 divided
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down, then the samplerate must be provided. The bitrate will be the product
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down, then the sample rate must be provided. The bit rate will be the product
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of the sample rate and the data width. The SSC driver will determine the best
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divider to obtain that bitrate (up to 4095). If the bitrate can be realized
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divider to obtain that bit rate (up to 4095). If the bit rate can be realized
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by dividing down the MCK/2, a compile time error will occur.
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config SAMA5_SSC1_LOOPBACK
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@ -1658,7 +1657,7 @@ config SAMA5_SSC1_LOOPBACK
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---help---
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If both the receiver and transmitter are enabled, then the SSC can
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be configured in loopback mode. This setting selects SSC loopback
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and will cause the LOOP bit to be set in the SSC_RFMR regsiter. In
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and will cause the LOOP bit to be set in the SSC_RFMR register. In
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this case, RD is connected to TD, RF is connected to TF and RK is
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connected to TK.
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@ -1767,7 +1766,7 @@ config SAMA5_UDPHS_NDTDS
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default 9
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depends on UDPHS_SCATTERGATHER
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---help---
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DMA tranfer descriptors are allocated in a pool at boot time. This
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DMA transfer descriptors are allocated in a pool at boot time. This
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setting provides the number of DMA transfer descriptors to be
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allocated.
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@ -1776,17 +1775,17 @@ config SAMA5_UDPHS_PREALLOCATE
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default y
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depends on UDPHS_SCATTERGATHER
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---help---
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If this option is selected then DMA tranfer descriptors will be
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If this option is selected then DMA transfer descriptors will be
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pre-allocated in .bss. Otherwise, the descriptors will be allocated
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at start-up time with kmalloc(). This might be important if a larger
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memory pool is available after startup.
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config SAMA5_UDPHS_REGDEBUG
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bool "Enable low-level UPPHS register debug"
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bool "Enable low-level UDPHS register debug"
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default n
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depends on DEBUG
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endmenu # USB High Speed Host Device driver (DCD) options
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endmenu # USB High Speed Device Controller driver (DCD) options
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endif # SAMA5_UDPHS
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if SAMA5_UHPHS
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@ -82,23 +82,23 @@
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/* 0x00e4-0x00e8 Reserved */
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/* Endpoint Offsets */
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#define SAM_UPPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5))
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#define SAM_UPPHS_EP0_OFFSET 0x0100
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#define SAM_UPPHS_EP1_OFFSET 0x0120
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#define SAM_UPPHS_EP2_OFFSET 0x0140
|
||||
#define SAM_UPPHS_EP3_OFFSET 0x0160
|
||||
#define SAM_UPPHS_EP4_OFFSET 0x0180
|
||||
#define SAM_UPPHS_EP5_OFFSET 0x01a0
|
||||
#define SAM_UPPHS_EP6_OFFSET 0x01c0
|
||||
#define SAM_UPPHS_EP7_OFFSET 0x01e0
|
||||
#define SAM_UPPHS_EP8_OFFSET 0x0200
|
||||
#define SAM_UPPHS_EP9_OFFSET 0x0220
|
||||
#define SAM_UPPHS_EP10_OFFSET 0x0240
|
||||
#define SAM_UPPHS_EP11_OFFSET 0x0260
|
||||
#define SAM_UPPHS_EP12_OFFSET 0x0280
|
||||
#define SAM_UPPHS_EP13_OFFSET 0x02a0
|
||||
#define SAM_UPPHS_EP14_OFFSET 0x02c0
|
||||
#define SAM_UPPHS_EP15_OFFSET 0x02e0
|
||||
#define SAM_UDPHS_EP_OFFSET(ep) (0x0100+((unsigned int)(ep)<<5))
|
||||
#define SAM_UDPHS_EP0_OFFSET 0x0100
|
||||
#define SAM_UDPHS_EP1_OFFSET 0x0120
|
||||
#define SAM_UDPHS_EP2_OFFSET 0x0140
|
||||
#define SAM_UDPHS_EP3_OFFSET 0x0160
|
||||
#define SAM_UDPHS_EP4_OFFSET 0x0180
|
||||
#define SAM_UDPHS_EP5_OFFSET 0x01a0
|
||||
#define SAM_UDPHS_EP6_OFFSET 0x01c0
|
||||
#define SAM_UDPHS_EP7_OFFSET 0x01e0
|
||||
#define SAM_UDPHS_EP8_OFFSET 0x0200
|
||||
#define SAM_UDPHS_EP9_OFFSET 0x0220
|
||||
#define SAM_UDPHS_EP10_OFFSET 0x0240
|
||||
#define SAM_UDPHS_EP11_OFFSET 0x0260
|
||||
#define SAM_UDPHS_EP12_OFFSET 0x0280
|
||||
#define SAM_UDPHS_EP13_OFFSET 0x02a0
|
||||
#define SAM_UDPHS_EP14_OFFSET 0x02c0
|
||||
#define SAM_UDPHS_EP15_OFFSET 0x02e0
|
||||
|
||||
/* Endpoint registers */
|
||||
|
||||
@ -113,14 +113,14 @@
|
||||
|
||||
/* DMA Channel Offsets */
|
||||
|
||||
#define SAM_UPPHS_CH_OFFSET(ch) (0x0300+((unsigned int)(ch)<<4))
|
||||
#define SAM_UPPHS_CH0_OFFSET 0x0300
|
||||
#define SAM_UPPHS_CH1_OFFSET 0x0310
|
||||
#define SAM_UPPHS_CH2_OFFSET 0x0320
|
||||
#define SAM_UPPHS_CH3_OFFSET 0x0330
|
||||
#define SAM_UPPHS_CH4_OFFSET 0x0340
|
||||
#define SAM_UPPHS_CH5_OFFSET 0x0350
|
||||
#define SAM_UPPHS_CH6_OFFSET 0x0360
|
||||
#define SAM_UDPHS_CH_OFFSET(ch) (0x0300+((unsigned int)(ch)<<4))
|
||||
#define SAM_UDPHS_CH0_OFFSET 0x0300
|
||||
#define SAM_UDPHS_CH1_OFFSET 0x0310
|
||||
#define SAM_UDPHS_CH2_OFFSET 0x0320
|
||||
#define SAM_UDPHS_CH3_OFFSET 0x0330
|
||||
#define SAM_UDPHS_CH4_OFFSET 0x0340
|
||||
#define SAM_UDPHS_CH5_OFFSET 0x0350
|
||||
#define SAM_UDPHS_CH6_OFFSET 0x0360
|
||||
|
||||
/* DMA Channel Registers */
|
||||
|
||||
@ -143,51 +143,51 @@
|
||||
|
||||
/* Endpoint Base Addresses */
|
||||
|
||||
#define SAM_UPPHS_EP_BASE(ep) (SAM_UDPHS_VBASE+SAM_UPPHS_EP_OFFSET(ep))
|
||||
#define SAM_UPPHS_EP0_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP0_OFFSET)
|
||||
#define SAM_UPPHS_EP1_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP1_OFFSET)
|
||||
#define SAM_UPPHS_EP2_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP2_OFFSET)
|
||||
#define SAM_UPPHS_EP3_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP3_OFFSET)
|
||||
#define SAM_UPPHS_EP4_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP4_OFFSET)
|
||||
#define SAM_UPPHS_EP5_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP5_OFFSET)
|
||||
#define SAM_UPPHS_EP6_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP6_OFFSET)
|
||||
#define SAM_UPPHS_EP7_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP7_OFFSET)
|
||||
#define SAM_UPPHS_EP8_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP8_OFFSET)
|
||||
#define SAM_UPPHS_EP9_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP9_OFFSET)
|
||||
#define SAM_UPPHS_EP10_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP10_OFFSET)
|
||||
#define SAM_UPPHS_EP11_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP11_OFFSET)
|
||||
#define SAM_UPPHS_EP12_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP12_OFFSET)
|
||||
#define SAM_UPPHS_EP13_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP13_OFFSET)
|
||||
#define SAM_UPPHS_EP14_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP14_OFFSET)
|
||||
#define SAM_UPPHS_EP15_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_EP15_OFFSET)
|
||||
#define SAM_UDPHS_EP_BASE(ep) (SAM_UDPHS_VBASE+SAM_UDPHS_EP_OFFSET(ep))
|
||||
#define SAM_UDPHS_EP0_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP0_OFFSET)
|
||||
#define SAM_UDPHS_EP1_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP1_OFFSET)
|
||||
#define SAM_UDPHS_EP2_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP2_OFFSET)
|
||||
#define SAM_UDPHS_EP3_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP3_OFFSET)
|
||||
#define SAM_UDPHS_EP4_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP4_OFFSET)
|
||||
#define SAM_UDPHS_EP5_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP5_OFFSET)
|
||||
#define SAM_UDPHS_EP6_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP6_OFFSET)
|
||||
#define SAM_UDPHS_EP7_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP7_OFFSET)
|
||||
#define SAM_UDPHS_EP8_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP8_OFFSET)
|
||||
#define SAM_UDPHS_EP9_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP9_OFFSET)
|
||||
#define SAM_UDPHS_EP10_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP10_OFFSET)
|
||||
#define SAM_UDPHS_EP11_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP11_OFFSET)
|
||||
#define SAM_UDPHS_EP12_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP12_OFFSET)
|
||||
#define SAM_UDPHS_EP13_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP13_OFFSET)
|
||||
#define SAM_UDPHS_EP14_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP14_OFFSET)
|
||||
#define SAM_UDPHS_EP15_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_EP15_OFFSET)
|
||||
|
||||
/* Endpoint registers */
|
||||
|
||||
#define SAM_UDPHS_EPTCFG(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCFG_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTLENB(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLENB_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTLDIS(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLDIS_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTL(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTL_OFFSET)
|
||||
#define SAM_UDPHS_EPTSETSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTSETSTA_OFFSET)
|
||||
#define SAM_UDPHS_EPTCLRSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTCLRSTA_OFFSET)
|
||||
#define SAM_UDPHS_EPTSTA(ep) (SAM_UPPHS_EP_BASE(ep)+SAM_UDPHS_EPTSTA_OFFSET)
|
||||
#define SAM_UDPHS_EPTCFG(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCFG_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTLENB(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLENB_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTLDIS(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTLDIS_OFFSET)
|
||||
#define SAM_UDPHS_EPTCTL(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCTL_OFFSET)
|
||||
#define SAM_UDPHS_EPTSETSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTSETSTA_OFFSET)
|
||||
#define SAM_UDPHS_EPTCLRSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTCLRSTA_OFFSET)
|
||||
#define SAM_UDPHS_EPTSTA(ep) (SAM_UDPHS_EP_BASE(ep)+SAM_UDPHS_EPTSTA_OFFSET)
|
||||
|
||||
/* DMA Channel Base Addresses */
|
||||
|
||||
#define SAM_UPPHS_CH_BASE(ch) (SAM_UDPHS_VBASE+SAM_UPPHS_CH_OFFSET(ch))
|
||||
#define SAM_UPPHS_CH1_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH1_OFFSET)
|
||||
#define SAM_UPPHS_CH2_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH2_OFFSET)
|
||||
#define SAM_UPPHS_CH3_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH3_OFFSET)
|
||||
#define SAM_UPPHS_CH4_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH4_OFFSET)
|
||||
#define SAM_UPPHS_CH5_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH5_OFFSET)
|
||||
#define SAM_UPPHS_CH6_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH6_OFFSET)
|
||||
#define SAM_UPPHS_CH7_BASE (SAM_UDPHS_VBASE+SAM_UPPHS_CH7_OFFSET)
|
||||
#define SAM_UDPHS_CH_BASE(ch) (SAM_UDPHS_VBASE+SAM_UDPHS_CH_OFFSET(ch))
|
||||
#define SAM_UDPHS_CH1_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH1_OFFSET)
|
||||
#define SAM_UDPHS_CH2_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH2_OFFSET)
|
||||
#define SAM_UDPHS_CH3_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH3_OFFSET)
|
||||
#define SAM_UDPHS_CH4_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH4_OFFSET)
|
||||
#define SAM_UDPHS_CH5_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH5_OFFSET)
|
||||
#define SAM_UDPHS_CH6_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH6_OFFSET)
|
||||
#define SAM_UDPHS_CH7_BASE (SAM_UDPHS_VBASE+SAM_UDPHS_CH7_OFFSET)
|
||||
|
||||
/* DMA Channel Registers */
|
||||
|
||||
#define SAM_UDPHS_DMANXTDSC(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMANXTDSC_OFFSET)
|
||||
#define SAM_UDPHS_DMAADDRESS(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMAADDRESS_OFFSET)
|
||||
#define SAM_UDPHS_DMACONTROL(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMACONTROL_OFFSET)
|
||||
#define SAM_UDPHS_DMASTATUS(ch) (SAM_UPPHS_CH_BASE(ch)+SAM_UDPHS_DMASTATUS_OFFSET)
|
||||
#define SAM_UDPHS_DMANXTDSC(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMANXTDSC_OFFSET)
|
||||
#define SAM_UDPHS_DMAADDRESS(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMAADDRESS_OFFSET)
|
||||
#define SAM_UDPHS_DMACONTROL(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMACONTROL_OFFSET)
|
||||
#define SAM_UDPHS_DMASTATUS(ch) (SAM_UDPHS_CH_BASE(ch)+SAM_UDPHS_DMASTATUS_OFFSET)
|
||||
|
||||
/* Register bit-field definitions ***********************************************************/
|
||||
|
||||
|
||||
@ -103,9 +103,22 @@
|
||||
#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
|
||||
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
|
||||
|
||||
/* USB UTMI PLL start-up time */
|
||||
/* The PLL clock (USB_48M or UDPCK) is driven from the output of the PLL,
|
||||
* PLLACK. The PLL clock must be 48MHz. PLLACK can be divided down via the
|
||||
* PMC USB register to provide the PLL clock. So in order to use the USB
|
||||
* feature, the PLL output must be a multiple of 48MHz.
|
||||
*
|
||||
* PLLACK = 240MHz, USBDIV=5, USB_48M = 240 MHz / 5 = 48MHz
|
||||
* PLLACK = 192MHz, USBDIV=4, USB_48M = 192 MHz / 4 = 48MHz
|
||||
*/
|
||||
|
||||
#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
|
||||
#define BOARD_PMC_USBS (0)
|
||||
|
||||
#ifdef CONFIG_SAM4EEK_120MHZ
|
||||
# define BOARD_PMC_USBDIV (4 << PMC_USB_USBDIV_SHIFT)
|
||||
#else
|
||||
# define BOARD_PMC_USBDIV (3 << PMC_USB_USBDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Resulting frequencies */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user