diff --git a/arch/arm/include/tiva/chip.h b/arch/arm/include/tiva/chip.h index ddb246346d..326c1217d9 100644 --- a/arch/arm/include/tiva/chip.h +++ b/arch/arm/include/tiva/chip.h @@ -125,7 +125,7 @@ # define TIVA_NAES 0 /* No AES module */ # define TIVA_NDES 0 /* No DES module */ # define TIVA_NHASH 0 /* No SHA1/MD5 hash module */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || defined(CONFIG_ARCH_CHIP_LM3S9B92) # define LM3S 1 /* LM3S family */ # undef LM4F /* Not LM4F family */ # undef TM4C /* Not TM4C family */ diff --git a/arch/arm/include/tiva/lm3s_irq.h b/arch/arm/include/tiva/lm3s_irq.h index 5f485fe07d..65eb8c7293 100644 --- a/arch/arm/include/tiva/lm3s_irq.h +++ b/arch/arm/include/tiva/lm3s_irq.h @@ -249,7 +249,7 @@ # define NR_IRQS (71) /* (Really less because of reserved vectors) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || defined(CONFIG_ARCH_CHIP_LM3S9B92) # define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */ # define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */ # define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */ diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index b6f8efc3e0..9ed79f0a96 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -20,6 +20,18 @@ config ARCH_CHIP_LM3S6918 select TIVA_HAVE_TIMER3 select TIVA_HAVE_ETHERNET +config ARCH_CHIP_LM3S9B92 + bool "LM3S9B92" + depends on ARCH_CHIP_LM + select ARCH_CORTEXM3 + select ARCH_CHIP_LM3S + select TIVA_HAVE_UART3 + select TIVA_HAVE_I2C1 + select TIVA_HAVE_SSI1 + select TIVA_HAVE_TIMER3 + select TIVA_HAVE_ETHERNET + select TIVA_HAVE_GPIOH_IRQS + config ARCH_CHIP_LM3S9B96 bool "LM3S9B96" depends on ARCH_CHIP_LM diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h b/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h index 79fc675abb..d218a336fe 100644 --- a/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h +++ b/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h @@ -226,6 +226,9 @@ # define tiva_uart6_disableclk() tiva_uart_disableclk(6) # define tiva_uart7_disableclk() tiva_uart_disableclk(7) #else +# define tiva_uart_enableclk(p) tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGCUART(p)) +# define tiva_uart_disableclk(p) tiva_disableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGCUART(p)) + # define tiva_uart0_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART0) # define tiva_uart1_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART1) # define tiva_uart2_enableclk() tiva_enableclk(TIVA_SYSCON_RCGC1,SYSCON_RCGC1_UART2) diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_flash.h b/arch/arm/src/tiva/hardware/lm/lm3s_flash.h index 5c603e6b1c..aafea070d8 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_flash.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_flash.h @@ -50,6 +50,7 @@ #if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \ defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \ + defined(CONFIG_ARCH_CHIP_LM3S9B92) || \ defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI) /* These parts all support a 1KiB erase page size and a total FLASH memory size diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h b/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h index a3cea06911..39e1563a64 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h @@ -80,6 +80,8 @@ #define TIVA_GPIO_DEN_OFFSET 0x051c /* GPIO Digital Enable */ #define TIVA_GPIO_LOCK_OFFSET 0x0520 /* GPIO Lock */ #define TIVA_GPIO_CR_OFFSET 0x0524 /* GPIO Commit */ +#define TIVA_GPIO_AMSEL_OFFSET 0x0528 /* GPIO Analog Mode Select */ +#define TIVA_GPIO_PCTL_OFFSET 0x052c /* GPIO Port Control */ #define TIVA_GPIO_PERIPHID4_OFFSET 0x0fd0 /* GPIO Peripheral Identification 4 */ #define TIVA_GPIO_PERIPHID5_OFFSET 0x0fd4 /* GPIO Peripheral Identification 5 */ @@ -118,6 +120,8 @@ # define TIVA_GPIOA_DEN (TIVA_GPIOA_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOA_LOCK (TIVA_GPIOA_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOA_CR (TIVA_GPIOA_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOA_AMSEL (TIVA_GPIOA_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOA_PCTL (TIVA_GPIOA_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOA_PERIPHID4 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOA_PERIPHID5 (TIVA_GPIOA_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -155,6 +159,8 @@ # define TIVA_GPIOB_DEN (TIVA_GPIOB_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOB_LOCK (TIVA_GPIOB_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOB_CR (TIVA_GPIOB_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOB_AMSEL (TIVA_GPIOB_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOB_PCTL (TIVA_GPIOB_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOB_PERIPHID4 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOB_PERIPHID5 (TIVA_GPIOB_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -192,6 +198,8 @@ # define TIVA_GPIOC_DEN (TIVA_GPIOC_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOC_LOCK (TIVA_GPIOC_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOC_CR (TIVA_GPIOC_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOC_AMSEL (TIVA_GPIOC_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOC_PCTL (TIVA_GPIOC_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOC_PERIPHID4 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOC_PERIPHID5 (TIVA_GPIOC_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -229,6 +237,8 @@ # define TIVA_GPIOD_DEN (TIVA_GPIOD_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOD_LOCK (TIVA_GPIOD_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOD_CR (TIVA_GPIOD_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOD_AMSEL (TIVA_GPIOD_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOD_PCTL (TIVA_GPIOD_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOD_PERIPHID4 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOD_PERIPHID5 (TIVA_GPIOD_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -266,6 +276,8 @@ # define TIVA_GPIOE_DEN (TIVA_GPIOE_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOE_LOCK (TIVA_GPIOE_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOE_CR (TIVA_GPIOE_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOE_AMSEL (TIVA_GPIOE_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOE_PCTL (TIVA_GPIOE_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOE_PERIPHID4 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOE_PERIPHID5 (TIVA_GPIOE_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -303,6 +315,8 @@ # define TIVA_GPIOF_DEN (TIVA_GPIOF_BASE + TIVA_GPIO_DEN_OFFSET) # define TIVA_GPIOF_LOCK (TIVA_GPIOF_BASE + TIVA_GPIO_LOCK_OFFSET) # define TIVA_GPIOF_CR (TIVA_GPIOF_BASE + TIVA_GPIO_CR_OFFSET) +# define TIVA_GPIOF_AMSEL (TIVA_GPIOF_BASE + TIVA_GPIO_AMSEL_OFFSET) +# define TIVA_GPIOF_PCTL (TIVA_GPIOF_BASE + TIVA_GPIO_PCTL_OFFSET) # define TIVA_GPIOF_PERIPHID4 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID4_OFFSET) # define TIVA_GPIOF_PERIPHID5 (TIVA_GPIOF_BASE + TIVA_GPIO_PERIPHID5_OFFSET) @@ -436,6 +450,28 @@ #define GPIO_LOCK_UNLOCK 0x4c4f434b #define GPIO_LOCK_LOCKED (1 << 0) /* Bit 0: GPIOCR register is locked */ +/* GPIO Port Control */ + +#define GPIO_PCTL_PMC_SHIFT(n) ((n) << 2) +#define GPIO_PCTL_PMC_MASK(n) (15 << GPIO_PCTL_PMC_SHIFT(n)) + +#define GPIO_PCTL_PMC0_SHIFT (0) /* Bits 0-3: Port Mux Control 0 */ +#define GPIO_PCTL_PMC0_MASK (15 << GPIO_PCTL_PMC0_SHIFT) +#define GPIO_PCTL_PMC1_SHIFT (4) /* Bits 4-7: Port Mux Control 1 */ +#define GPIO_PCTL_PMC1_MASK (15 << GPIO_PCTL_PMC1_SHIFT) +#define GPIO_PCTL_PMC2_SHIFT (8) /* Bits 8-11: Port Mux Control 2 */ +#define GPIO_PCTL_PMC2_MASK (15 << GPIO_PCTL_PMC2_SHIFT) +#define GPIO_PCTL_PMC3_SHIFT (12) /* Bits 12-15: Port Mux Control 3 */ +#define GPIO_PCTL_PMC3_MASK (15 << GPIO_PCTL_PMC3_SHIFT) +#define GPIO_PCTL_PMC4_SHIFT (16) /* Bits 16-19: Port Mux Control 4 */ +#define GPIO_PCTL_PMC4_MASK (15 << GPIO_PCTL_PMC4_SHIFT) +#define GPIO_PCTL_PMC5_SHIFT (20) /* Bits 20-23: Port Mux Control 5 */ +#define GPIO_PCTL_PMC5_MASK (15 << GPIO_PCTL_PMC5_SHIFT) +#define GPIO_PCTL_PMC6_SHIFT (24) /* Bits 24-27: Port Mux Control 6 */ +#define GPIO_PCTL_PMC6_MASK (15 << GPIO_PCTL_PMC6_SHIFT) +#define GPIO_PCTL_PMC7_SHIFT (28) /* Bits 28-31: Port Mux Control 7 */ +#define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h b/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h index f69603fec7..a53a4f47de 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h @@ -68,7 +68,7 @@ /* -0xe003ffff: Reserved */ # define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ /* -0xffffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || defined(CONFIG_ARCH_CHIP_LM3S9B92) # define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ /* -0x1fffffff: Reserved */ # define TIVA_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ @@ -266,7 +266,7 @@ # define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ # define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) || defined(CONFIG_ARCH_CHIP_LM3S9B92) /* FiRM Peripheral Base Addresses */ # define TIVA_WDOG_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h b/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h index 69414e11bd..66e3252432 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h @@ -169,6 +169,21 @@ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ # define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B92) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_0) +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_1) +# define GPIO_UART1_RX_0 (GPIO_FUNC_PFINPUT | GPIO_ALT_5 | GPIO_PORTD | GPIO_PIN_0) +# define GPIO_UART1_TX_0 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTD | GPIO_PIN_1) +# define GPIO_UART1_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_2) +# define GPIO_UART1_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_3) +# define GPIO_UART1_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_5 | GPIO_PORTC | GPIO_PIN_6) +# define GPIO_UART1_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTC | GPIO_PIN_7) +# define GPIO_UART1_RX_3 (GPIO_FUNC_PFINPUT | GPIO_ALT_9 | GPIO_PORTA | GPIO_PIN_0) +# define GPIO_UART1_TX_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_9 | GPIO_PORTA | GPIO_PIN_1) +# define GPIO_UART1_RX_4 (GPIO_FUNC_PFINPUT | GPIO_ALT_5 | GPIO_PORTB | GPIO_PIN_0) +# define GPIO_UART1_TX_4 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_5 | GPIO_PORTB | GPIO_PIN_1) +# define GPIO_UART1_RX_5 (GPIO_FUNC_PFINPUT | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_4) +# define GPIO_UART1_TX_5 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_5) #elif defined(CONFIG_ARCH_CHIP_LM3S9B96) # define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ # define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h b/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h index e1ae854923..ec1dff7ff4 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h @@ -322,6 +322,15 @@ # define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ # define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ # define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ +#ifdef CONFIG_ARCH_CHIP_LM3S9B92 +# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ +# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ +# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ +# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ +# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ +# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ +#endif #ifdef CONFIG_ARCH_CHIP_LM3S9B96 # define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ # define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ @@ -480,6 +489,10 @@ #define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ #define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) +/* UART Run Mode Clock Gating Control*/ + +#define SYSCON_RCGCUART(n) (1 << (n)) /* Bit n: UART Module n Run Mode Clock Gating Control */ + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/tiva/lm/lm3s_gpio.c b/arch/arm/src/tiva/lm/lm3s_gpio.c index 32dd85603f..89b71dd5b6 100644 --- a/arch/arm/src/tiva/lm/lm3s_gpio.c +++ b/arch/arm/src/tiva/lm/lm3s_gpio.c @@ -656,6 +656,44 @@ static inline void tiva_interrupt(pinconfig_t pinconfig) } #endif +/**************************************************************************** + * Name: tiva_portcontrol + * + * Description: + * Set the pin alternate function in the port control register. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_LM3S9B92) +static inline void tiva_portcontrol(uint32_t base, uint32_t pinno, + pinconfig_t pinconfig, + const struct gpio_func_s *func) +{ + uint32_t alt = 0; + uint32_t mask; + uint32_t regval; + + /* Is this pin an alternate function pin? */ + + if ((func->setbits & AFSEL_1) != 0) + { + /* Yes, extract the alternate function number from the pin + * configuration. + */ + + alt = (pinconfig & GPIO_ALT_MASK) >> GPIO_ALT_SHIFT; + } + + /* Set the alternate function in the port control register */ + + regval = getreg32(base + TIVA_GPIO_PCTL_OFFSET); + mask = GPIO_PCTL_PMC_MASK(pinno); + regval &= ~mask; + regval |= (alt << GPIO_PCTL_PMC_SHIFT(pinno)) & mask; + putreg32(regval, base + TIVA_GPIO_PCTL_OFFSET); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -708,6 +746,9 @@ int tiva_configgpio(pinconfig_t pinconfig) */ tiva_gpiofunc(base, pinno, &g_funcbits[0]); +#if defined(CONFIG_ARCH_CHIP_LM3S9B92) + tiva_portcontrol(base, pinno, pinconfig, &g_funcbits[0]); +#endif /* Then set up pad strengths and pull-ups. These setups should be done before * setting up the function because some function settings will over-ride these @@ -720,6 +761,9 @@ int tiva_configgpio(pinconfig_t pinconfig) /* Then set up the real pin function */ tiva_gpiofunc(base, pinno, &g_funcbits[func]); +#if defined(CONFIG_ARCH_CHIP_LM3S9B92) + tiva_portcontrol(base, pinno, pinconfig, &g_funcbits[func]); +#endif /* Special case GPIO digital output pins */ diff --git a/arch/arm/src/tiva/lm/lm3s_gpio.h b/arch/arm/src/tiva/lm/lm3s_gpio.h index ca654a3bc7..9608d9349f 100644 --- a/arch/arm/src/tiva/lm/lm3s_gpio.h +++ b/arch/arm/src/tiva/lm/lm3s_gpio.h @@ -186,6 +186,31 @@ # define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */ # define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */ +/* The LM3S supports up to 15 alternate functions per pin: + * + * .... .... .... AAAA .... .... .... .... + */ + +#define GPIO_ALT_SHIFT 16 /* Bits 16-19: Alternate function */ +#define GPIO_ALT_MASK (15 << GPIO_ALT_SHIFT) +# define GPIO_ALT(n) ((n) << GPIO_ALT_SHIFT) +# define GPIO_ALT_NONE (0 << GPIO_ALT_SHIFT) +# define GPIO_ALT_1 (1 << GPIO_ALT_SHIFT) +# define GPIO_ALT_2 (2 << GPIO_ALT_SHIFT) +# define GPIO_ALT_3 (3 << GPIO_ALT_SHIFT) +# define GPIO_ALT_4 (4 << GPIO_ALT_SHIFT) +# define GPIO_ALT_5 (5 << GPIO_ALT_SHIFT) +# define GPIO_ALT_6 (6 << GPIO_ALT_SHIFT) +# define GPIO_ALT_7 (7 << GPIO_ALT_SHIFT) +# define GPIO_ALT_8 (8 << GPIO_ALT_SHIFT) +# define GPIO_ALT_9 (9 << GPIO_ALT_SHIFT) +# define GPIO_ALT_10 (10 << GPIO_ALT_SHIFT) +# define GPIO_ALT_11 (11 << GPIO_ALT_SHIFT) +# define GPIO_ALT_12 (12 << GPIO_ALT_SHIFT) +# define GPIO_ALT_13 (13 << GPIO_ALT_SHIFT) +# define GPIO_ALT_14 (14 << GPIO_ALT_SHIFT) +# define GPIO_ALT_15 (15 << GPIO_ALT_SHIFT) + /* If the pin is an GPIO digital output, then this identifies the initial output value: * .... .... .... .... .... ...V .... .... */