Add ENC28J80 control reg logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2628 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
b6a6c21d01
commit
1d050f61cc
@ -42,11 +42,11 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_NET) && defined(CONFIG_ENC28J60_NET)
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#if defined(CONFIG_NET) && defined(CONFIG_NET_ENC28J60)
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#include <stdint.h>
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#include <stdbool.h>
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#include <stding.h>
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#include <stdint.h>
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#include <time.h>
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#include <string.h>
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#include <debug.h>
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@ -80,7 +80,7 @@
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* devices that will be supported.
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*/
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#ifdef CONFIG_ENC28J60_SPIMODE
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#ifndef CONFIG_ENC28J60_SPIMODE
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# define CONFIG_ENC28J60_SPIMODE SPIDEV_MODE2
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#endif
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@ -105,6 +105,15 @@
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/* Misc. Helper Macros ******************************************************/
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#define enc28j60_rdglobal(priv,ctrlref) \
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enc28j60_rdglobal2(priv, ENC28J60_RCR | GETADDR(ctrlreg))
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#define enc28j60_wrglobal(priv,ctrlreg,wrdata) \
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enc28j60_wrglobal2(priv, ENC28J60_WCR | GETADDR(ctrlreg), wrdata)
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#define enc28j60_clrglobal(priv,ctrlreg,clrbits) \
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enc28j60_wrglobal2(priv, ENC28J60_BFC | GETADDR(ctrlreg), clrbits)
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#define enc28j60_setglobal(priv,ctrlreg,setbits) \
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enc28j60_wrglobal2(priv, ENC28J60_BFS | GETADDR(ctrlreg), setbits)
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/* This is a helper pointer for accessing the contents of the Ethernet header */
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#define BUF ((struct uip_eth_hdr *)priv->dev.d_buf)
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@ -147,16 +156,32 @@ static struct enc28j60_driver_s g_enc28j60[CONFIG_ENC28J60_NINTERFACES];
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/* Low-level SPI helpers */
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static inline void enc28j60_configspi(FAR struct spi_dev_s *spi);
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#ifdef CONFIG_ENC28J60_OWNBUS
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static inline uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
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static inline uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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#else
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static uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
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static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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#endif
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static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd);
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static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd, uint8_t wrdata);
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static void enc28j60_setbank(FAR struct enc28j60_driver_s *priv, uint8_t bank);
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static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg);
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static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg);
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/* Common TX logic */
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static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv);
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static int enc28j60_transmit(FAR struct enc28j60_driver_s *priv);
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static int enc28j60_uiptxpoll(struct uip_driver_s *dev);
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/* Interrupt handling */
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static void enc28j60_receive(FAR struct enc28j60_drver_s *priv);
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static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv);
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static void enc28j60_receive(FAR struct enc28j60_driver_s *priv);
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static void enc28j60_txdone(FAR struct enc28j60_driver_s *priv);
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static int enc28j60_interrupt(int irq, FAR void *context);
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/* Watchdog timer expirations */
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@ -259,6 +284,219 @@ static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi)
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}
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#endif
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/****************************************************************************
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* Function: enc28j60_rdglobal2
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*
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* Description:
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* Read a global register (EIE, EIR, ESTAT, ECON2, or ECON1). The cmd
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* include the CMD 'OR'd with the the global address register.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Send the read command and (maybe collect the return data) */
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rddata = SPI_SEND(spi, cmd);
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_wrglobal2
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*
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* Description:
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* Write to a global register (EIE, EIR, ESTAT, ECON2, or ECON1). The cmd
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* include the CMD 'OR'd with the the global address register.
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*
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****************************************************************************/
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static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd, uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Send the write command */
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(void)SPI_SEND(spi, cmd);
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_setbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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* Assumption:
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* The caller has exclusive access to the SPI bus
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*
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****************************************************************************/
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static void enc28j60_setbank(FAR struct enc28j60_driver_s *priv, uint8_t bank)
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{
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/* Check if the bank setting has changed*/
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if (bank != priv->bank)
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{
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/* Select bank 0 (just so that all of the bits are cleared) */
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enc28j60_clrglobal(priv, ECON1, ECON1_BSEL_MASK);
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/* Then OR in bits to get the correct bank */
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if (bank != 0)
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{
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enc28j60_setglobal(priv, ECON1, (bank << ECON1_BSEL_SHIFT));
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}
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/* Then remember the bank setting */
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priv->bank = bank;
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}
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}
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/****************************************************************************
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* Function: enc28j60_rdbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command and collect the return data. */
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rddata = SPI_SEND(spi, ENC28J60_RCR | GETADDR(ctrlreg));
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_rdphymac
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*
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* Description:
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* Somewhat different timing is required to read from any PHY or MAC
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* registers. The PHY/MAC data is returned on the second byte after the
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* command.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command (discarding the return data) */
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(void)SPI_SEND(spi, ENC28J60_RCR | GETADDR(ctrlreg));
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/* Do an extra transfer to get the data from the MAC or PHY */
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rddata = SPI_SEND(spi, 0);
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_wrbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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****************************************************************************/
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static void enc28j60_wrbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg, uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the write command */
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(void)SPI_SEND(spi, ENC28J60_WCR | GETADDR(ctrlreg));
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_transmit
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*
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@ -276,7 +514,7 @@ static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi)
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*
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****************************************************************************/
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static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_transmit(FAR struct enc28j60_driver_s *priv)
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{
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/* Verify that the hardware is ready to send another packet */
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@ -317,7 +555,7 @@ static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_uiptxpoll(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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/* If the polling resulted in data that should be sent out on the network,
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* the field d_len is set to a value > 0.
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@ -356,7 +594,7 @@ static int enc28j60_uiptxpoll(struct uip_driver_s *dev)
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*
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****************************************************************************/
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static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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static void enc28j60_receive(FAR struct enc28j60_driver_s *priv)
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{
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do
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{
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@ -384,27 +622,26 @@ static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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*/
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if (priv->dev.d_len > 0)
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{
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uip_arp_out(&priv->dev);
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enc28j60_transmit(priv);
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}
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{
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uip_arp_out(&priv->dev);
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enc28j60_transmit(priv);
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}
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}
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else if (BUF->type == htons(UIP_ETHTYPE_ARP))
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{
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uip_arp_arpin(&priv->dev);
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/* If the above function invocation resulted in data that should be
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* sent out on the network, the field d_len will set to a value > 0.
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*/
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if (priv->dev.d_len > 0)
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{
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enc28j60_transmit(priv);
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}
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}
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else if (BUF->type == htons(UIP_ETHTYPE_ARP))
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{
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uip_arp_arpin(&priv->dev);
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/* If the above function invocation resulted in data that should be
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* sent out on the network, the field d_len will set to a value > 0.
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*/
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if (priv->dev.d_len > 0)
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{
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enc28j60_transmit(priv);
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}
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}
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}
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}
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while (); /* While there are more packets to be processed */
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}
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while (false); /* While there are more packets to be processed */
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}
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/****************************************************************************
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@ -423,7 +660,7 @@ static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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*
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****************************************************************************/
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static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv)
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static void enc28j60_txdone(FAR struct enc28j60_driver_s *priv)
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{
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/* Check for errors and update statistics */
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@ -455,7 +692,7 @@ static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_interrupt(int irq, FAR void *context)
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{
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register FAR struct enc28j60_drver_s *priv = &g_enc28j60[0];
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register FAR struct enc28j60_driver_s *priv = &g_enc28j60[0];
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/* Disable Ethernet interrupts */
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@ -498,7 +735,7 @@ static int enc28j60_interrupt(int irq, FAR void *context)
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static void enc28j60_txtimeout(int argc, uint32_t arg, ...)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)arg;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)arg;
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/* Increment statistics and dump debug info */
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@ -528,7 +765,7 @@ static void enc28j60_txtimeout(int argc, uint32_t arg, ...)
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static void enc28j60_polltimer(int argc, uint32_t arg, ...)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)arg;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)arg;
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/* Check if there is room in the send another TXr packet. */
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@ -560,7 +797,7 @@ static void enc28j60_polltimer(int argc, uint32_t arg, ...)
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static int enc28j60_ifup(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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@ -597,7 +834,7 @@ static int enc28j60_ifup(struct uip_driver_s *dev)
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static int enc28j60_ifdown(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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irqstate_t flags;
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/* Disable the Ethernet interrupt */
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@ -638,7 +875,7 @@ static int enc28j60_ifdown(struct uip_driver_s *dev)
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static int enc28j60_txavail(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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irqstate_t flags;
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flags = irqsave();
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@ -1,166 +1,184 @@
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/****************************************************************************
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* drivers/net/enc28j60.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_NET_ENC28J60_H
|
||||
#define __DRIVERS_NET_ENC28J60_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* A total of seven instructions are implemented on the ENC28J60 */
|
||||
|
||||
#define ENC28J60_RCR (0x00) /* Read Control Register
|
||||
* 000 | aaaaa | (Registe value returned)) */
|
||||
#define ENC28J60_RBM (0x3a) /* Read Buffer Memory
|
||||
* 001 | 11010 | (Read buffer data follows) */
|
||||
#define ENC28J60_WCR (0x40) /* Write Control Register
|
||||
* 010 | aaaaa | dddddddd */
|
||||
#define ENC28J60_WBM (0x7a) /* Write Buffer Memory
|
||||
* 011 | 11010 | (Write buffer data follows) */
|
||||
#define ENC28J60_BFS (0x80) /* Bit Field Set
|
||||
* 100 | aaaaa | dddddddd */
|
||||
#define ENC28J60_BFC (0xa0) /* Bit Field Clear
|
||||
* 101 | aaaaa | dddddddd */
|
||||
#define ENC28J60_SRC (0xff) /* System Reset
|
||||
* 111 | 11111 | (No data) */
|
||||
|
||||
/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC commands.
|
||||
* The following identifies all ENC28J60 control registers. The Control register
|
||||
* memory is partitioned into four banks, selectable by the bank select bits,
|
||||
* BSEL1:BSEL0, in the ECON1 register.
|
||||
*
|
||||
* The last five locations (0x1b to 0x1f) of all banks point to a common set of
|
||||
* registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used
|
||||
* in controlling and monitoring the operation of the device. Their common
|
||||
* mapping allows easy access without switching the bank.
|
||||
*
|
||||
* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
|
||||
* MII registers. Register names starting with E belong to the ETH group. Similarly,
|
||||
* registers names starting with MA belong to the MAC group and registers prefixed
|
||||
* with MI belong to the MII group.
|
||||
*/
|
||||
|
||||
#define EIE (0x1b) /* Ethernet Interrupt Enable Register */
|
||||
#define EIR (0x1c) /* Ethernet Interupt Request Register */
|
||||
#define ESTAT (0x1d) /* Ethernet Status Register */
|
||||
#define ECON2 (0x1e) /* Ethernet Control 2 Register */
|
||||
#define ECON1 (0x1f) /* Ethernet Control 1 Register */
|
||||
|
||||
/* Ethernet Interrupt Enable Register Bit Definitions */
|
||||
|
||||
#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
|
||||
#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
|
||||
/* Bit 2: Reserved */
|
||||
#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
|
||||
#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
|
||||
#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
|
||||
#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
|
||||
#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
|
||||
|
||||
/* Ethernet Interupt Request Register Bit Definitions */
|
||||
|
||||
#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
|
||||
#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
|
||||
/* Bit 2: Reserved */
|
||||
#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
|
||||
#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
|
||||
#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
|
||||
#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
|
||||
/* Bit 7: Reserved */
|
||||
|
||||
/* Ethernet Status Register Bit Definitions */
|
||||
|
||||
#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
|
||||
#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
|
||||
#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
|
||||
/* Bit 3: Reserved */
|
||||
#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
|
||||
/* Bit 5: Reserved */
|
||||
#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
|
||||
#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
|
||||
|
||||
/* Ethernet Control 1 Register Bit Definitions */
|
||||
|
||||
#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
|
||||
#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
|
||||
# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
|
||||
# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
|
||||
# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
|
||||
# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
|
||||
#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
|
||||
#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
|
||||
#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
|
||||
#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
|
||||
#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
|
||||
#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
|
||||
|
||||
/* Ethernet Control 2 Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
|
||||
/* Bit 4: Reserved */
|
||||
#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
|
||||
#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
|
||||
#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRIVERS_NET_ENC28J60_H */
|
||||
/****************************************************************************
|
||||
* drivers/net/enc28j60.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_NET_ENC28J60_H
|
||||
#define __DRIVERS_NET_ENC28J60_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* A total of seven instructions are implemented on the ENC28J60 */
|
||||
|
||||
#define ENC28J60_RCR (0x00) /* Read Control Register
|
||||
* 000 | aaaaa | (Registe value returned)) */
|
||||
#define ENC28J60_RBM (0x3a) /* Read Buffer Memory
|
||||
* 001 | 11010 | (Read buffer data follows) */
|
||||
#define ENC28J60_WCR (0x40) /* Write Control Register
|
||||
* 010 | aaaaa | dddddddd */
|
||||
#define ENC28J60_WBM (0x7a) /* Write Buffer Memory
|
||||
* 011 | 11010 | (Write buffer data follows) */
|
||||
#define ENC28J60_BFS (0x80) /* Bit Field Set
|
||||
* 100 | aaaaa | dddddddd */
|
||||
#define ENC28J60_BFC (0xa0) /* Bit Field Clear
|
||||
* 101 | aaaaa | dddddddd */
|
||||
#define ENC28J60_SRC (0xff) /* System Reset
|
||||
* 111 | 11111 | (No data) */
|
||||
|
||||
/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC commands.
|
||||
* The following identifies all ENC28J60 control registers. The Control register
|
||||
* memory is partitioned into four banks, selectable by the bank select bits,
|
||||
* BSEL1:BSEL0, in the ECON1 register.
|
||||
*
|
||||
* The last five locations (0x1b to 0x1f) of all banks point to a common set of
|
||||
* registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used
|
||||
* in controlling and monitoring the operation of the device. Their common
|
||||
* mapping allows easy access without switching the bank.
|
||||
*
|
||||
* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
|
||||
* MII registers. Register names starting with E belong to the ETH group. Similarly,
|
||||
* registers names starting with MA belong to the MAC group and registers prefixed
|
||||
* with MI belong to the MII group.
|
||||
*/
|
||||
|
||||
#define EIE (0x1b) /* Ethernet Interrupt Enable Register */
|
||||
#define EIR (0x1c) /* Ethernet Interupt Request Register */
|
||||
#define ESTAT (0x1d) /* Ethernet Status Register */
|
||||
#define ECON2 (0x1e) /* Ethernet Control 2 Register */
|
||||
#define ECON1 (0x1f) /* Ethernet Control 1 Register */
|
||||
|
||||
/* The remaining control registers are identified with a a 5 bit address and a
|
||||
* bank selection. We pack the bank number and the control register address
|
||||
* together to keep the design simpler.
|
||||
*/
|
||||
|
||||
#define ENC28J60_ADDR_SHIFT (0) /* Bits 0-4: Register address */
|
||||
#define ENC28J60_ADDR_MASK (0x1f << ENC28J60_ADDR_SHIFT)
|
||||
#define ENC28J60_BANK_SHIFT (5) /* Bits 5-6: Bank number */
|
||||
#define ENC28J60_BANK_MASK (3 << ENC28J60_BSEL_SHIFT)
|
||||
# define ENC28J60_BANK0 (0 << ENC28J60_BSEL_SHIFT)
|
||||
# define ENC28J60_BANK1 (1 << ENC28J60_BSEL_SHIFT)
|
||||
# define ENC28J60_BANK2 (2 << ENC28J60_BSEL_SHIFT)
|
||||
# define ENC28J60_BANK3 (3 << ENC28J60_BSEL_SHIFT)
|
||||
|
||||
#define REGADDR(a,b) ((b) << ENC28J60_BANK_SHIFT | (a))
|
||||
#define GETADDR(a) ((a) & ENC28J60_ADDR_MASK)
|
||||
#define GETBANK(a) (((a) >> ENC28J60_BANK_SHIFT) & 3)
|
||||
|
||||
/* Ethernet Interrupt Enable Register Bit Definitions */
|
||||
|
||||
#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
|
||||
#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
|
||||
/* Bit 2: Reserved */
|
||||
#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
|
||||
#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
|
||||
#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
|
||||
#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
|
||||
#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
|
||||
|
||||
/* Ethernet Interupt Request Register Bit Definitions */
|
||||
|
||||
#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
|
||||
#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
|
||||
/* Bit 2: Reserved */
|
||||
#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
|
||||
#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
|
||||
#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
|
||||
#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
|
||||
/* Bit 7: Reserved */
|
||||
|
||||
/* Ethernet Status Register Bit Definitions */
|
||||
|
||||
#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
|
||||
#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
|
||||
#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
|
||||
/* Bit 3: Reserved */
|
||||
#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
|
||||
/* Bit 5: Reserved */
|
||||
#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
|
||||
#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
|
||||
|
||||
/* Ethernet Control 1 Register Bit Definitions */
|
||||
|
||||
#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
|
||||
#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
|
||||
# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
|
||||
# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
|
||||
# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
|
||||
# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
|
||||
#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
|
||||
#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
|
||||
#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
|
||||
#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
|
||||
#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
|
||||
#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
|
||||
|
||||
/* Ethernet Control 2 Register */
|
||||
/* Bits 0-2: Reserved */
|
||||
#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
|
||||
/* Bit 4: Reserved */
|
||||
#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
|
||||
#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
|
||||
#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRIVERS_NET_ENC28J60_H */
|
||||
|
||||
@ -264,21 +264,20 @@ static void skel_receive(FAR struct skel_driver_s *skel)
|
||||
uip_arp_out(&skel->sk_dev);
|
||||
skel_transmit(skel);
|
||||
}
|
||||
}
|
||||
else if (BUF->type == htons(UIP_ETHTYPE_ARP))
|
||||
{
|
||||
uip_arp_arpin(&skel->sk_dev);
|
||||
}
|
||||
else if (BUF->type == htons(UIP_ETHTYPE_ARP))
|
||||
{
|
||||
uip_arp_arpin(&skel->sk_dev);
|
||||
|
||||
/* If the above function invocation resulted in data that should be
|
||||
* sent out on the network, the field d_len will set to a value > 0.
|
||||
*/
|
||||
/* If the above function invocation resulted in data that should be
|
||||
* sent out on the network, the field d_len will set to a value > 0.
|
||||
*/
|
||||
|
||||
if (skel->sk_dev.d_len > 0)
|
||||
{
|
||||
skel_transmit(skel);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (skel->sk_dev.d_len > 0)
|
||||
{
|
||||
skel_transmit(skel);
|
||||
}
|
||||
}
|
||||
}
|
||||
while (); /* While there are more packets to be processed */
|
||||
}
|
||||
@ -592,4 +591,3 @@ int skel_initialize(void)
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NET && CONFIG_skeleton_NET */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user