Add ENC28J80 control reg logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2628 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
b6a6c21d01
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1d050f61cc
@ -42,11 +42,11 @@
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****************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_NET) && defined(CONFIG_ENC28J60_NET)
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#if defined(CONFIG_NET) && defined(CONFIG_NET_ENC28J60)
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#include <stdint.h>
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#include <stdbool.h>
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#include <stding.h>
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#include <stdint.h>
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#include <time.h>
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#include <string.h>
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#include <debug.h>
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@ -80,7 +80,7 @@
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* devices that will be supported.
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*/
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#ifdef CONFIG_ENC28J60_SPIMODE
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#ifndef CONFIG_ENC28J60_SPIMODE
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# define CONFIG_ENC28J60_SPIMODE SPIDEV_MODE2
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#endif
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@ -105,6 +105,15 @@
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/* Misc. Helper Macros ******************************************************/
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#define enc28j60_rdglobal(priv,ctrlref) \
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enc28j60_rdglobal2(priv, ENC28J60_RCR | GETADDR(ctrlreg))
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#define enc28j60_wrglobal(priv,ctrlreg,wrdata) \
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enc28j60_wrglobal2(priv, ENC28J60_WCR | GETADDR(ctrlreg), wrdata)
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#define enc28j60_clrglobal(priv,ctrlreg,clrbits) \
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enc28j60_wrglobal2(priv, ENC28J60_BFC | GETADDR(ctrlreg), clrbits)
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#define enc28j60_setglobal(priv,ctrlreg,setbits) \
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enc28j60_wrglobal2(priv, ENC28J60_BFS | GETADDR(ctrlreg), setbits)
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/* This is a helper pointer for accessing the contents of the Ethernet header */
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#define BUF ((struct uip_eth_hdr *)priv->dev.d_buf)
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@ -147,16 +156,32 @@ static struct enc28j60_driver_s g_enc28j60[CONFIG_ENC28J60_NINTERFACES];
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/* Low-level SPI helpers */
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static inline void enc28j60_configspi(FAR struct spi_dev_s *spi);
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#ifdef CONFIG_ENC28J60_OWNBUS
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static inline uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
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static inline uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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#else
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static uint8_t enc28j60_select(FAR struct spi_dev_s *spi);
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static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi);
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#endif
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static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd);
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static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd, uint8_t wrdata);
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static void enc28j60_setbank(FAR struct enc28j60_driver_s *priv, uint8_t bank);
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static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg);
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static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg);
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/* Common TX logic */
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static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv);
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static int enc28j60_transmit(FAR struct enc28j60_driver_s *priv);
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static int enc28j60_uiptxpoll(struct uip_driver_s *dev);
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/* Interrupt handling */
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static void enc28j60_receive(FAR struct enc28j60_drver_s *priv);
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static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv);
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static void enc28j60_receive(FAR struct enc28j60_driver_s *priv);
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static void enc28j60_txdone(FAR struct enc28j60_driver_s *priv);
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static int enc28j60_interrupt(int irq, FAR void *context);
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/* Watchdog timer expirations */
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@ -259,6 +284,219 @@ static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi)
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}
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#endif
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/****************************************************************************
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* Function: enc28j60_rdglobal2
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*
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* Description:
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* Read a global register (EIE, EIR, ESTAT, ECON2, or ECON1). The cmd
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* include the CMD 'OR'd with the the global address register.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Send the read command and (maybe collect the return data) */
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rddata = SPI_SEND(spi, cmd);
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_wrglobal2
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*
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* Description:
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* Write to a global register (EIE, EIR, ESTAT, ECON2, or ECON1). The cmd
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* include the CMD 'OR'd with the the global address register.
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*
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****************************************************************************/
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static void enc28j60_wrglobal2(FAR struct enc28j60_driver_s *priv,
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uint8_t cmd, uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Send the write command */
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(void)SPI_SEND(spi, cmd);
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_setbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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* Assumption:
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* The caller has exclusive access to the SPI bus
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*
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****************************************************************************/
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static void enc28j60_setbank(FAR struct enc28j60_driver_s *priv, uint8_t bank)
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{
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/* Check if the bank setting has changed*/
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if (bank != priv->bank)
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{
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/* Select bank 0 (just so that all of the bits are cleared) */
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enc28j60_clrglobal(priv, ECON1, ECON1_BSEL_MASK);
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/* Then OR in bits to get the correct bank */
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if (bank != 0)
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{
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enc28j60_setglobal(priv, ECON1, (bank << ECON1_BSEL_SHIFT));
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}
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/* Then remember the bank setting */
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priv->bank = bank;
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}
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}
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/****************************************************************************
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* Function: enc28j60_rdbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command and collect the return data. */
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rddata = SPI_SEND(spi, ENC28J60_RCR | GETADDR(ctrlreg));
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_rdphymac
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*
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* Description:
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* Somewhat different timing is required to read from any PHY or MAC
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* registers. The PHY/MAC data is returned on the second byte after the
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* command.
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*
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****************************************************************************/
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static uint8_t enc28j60_rdphymac(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg)
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{
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FAR struct spi_dev_s *spi;
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uint8_t rddata;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the read command (discarding the return data) */
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(void)SPI_SEND(spi, ENC28J60_RCR | GETADDR(ctrlreg));
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/* Do an extra transfer to get the data from the MAC or PHY */
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rddata = SPI_SEND(spi, 0);
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/* De-select ENC28J60 chip */
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enc28j60_deselect(spi);
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return rddata;
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}
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/****************************************************************************
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* Function: enc28j60_wrbank
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*
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* Description:
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* Set the bank for these next control register access.
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*
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****************************************************************************/
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static void enc28j60_wrbank(FAR struct enc28j60_driver_s *priv,
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uint8_t ctrlreg, uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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DEBUGASSERT(priv && priv->spi);
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spi = priv->spi;
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/* Select ENC2J60 chip */
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enc28j60_select(spi);
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/* Set the bank */
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enc28j60_setbank(priv, GETBANK(ctrlreg));
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/* Send the write command */
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(void)SPI_SEND(spi, ENC28J60_WCR | GETADDR(ctrlreg));
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/* Send the data byte */
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(void)SPI_SEND(spi, wrdata);
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/* De-select ENC28J60 chip. */
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enc28j60_deselect(spi);
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}
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/****************************************************************************
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* Function: enc28j60_transmit
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*
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@ -276,7 +514,7 @@ static uint8_t enc28j60_deselect(FAR struct spi_dev_s *spi)
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*
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****************************************************************************/
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static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_transmit(FAR struct enc28j60_driver_s *priv)
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{
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/* Verify that the hardware is ready to send another packet */
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@ -317,7 +555,7 @@ static int enc28j60_transmit(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_uiptxpoll(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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/* If the polling resulted in data that should be sent out on the network,
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* the field d_len is set to a value > 0.
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@ -356,7 +594,7 @@ static int enc28j60_uiptxpoll(struct uip_driver_s *dev)
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*
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****************************************************************************/
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static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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static void enc28j60_receive(FAR struct enc28j60_driver_s *priv)
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{
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do
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{
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@ -403,8 +641,7 @@ static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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}
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}
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}
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}
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while (); /* While there are more packets to be processed */
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while (false); /* While there are more packets to be processed */
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}
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/****************************************************************************
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@ -423,7 +660,7 @@ static void enc28j60_receive(FAR struct enc28j60_drver_s *priv)
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*
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****************************************************************************/
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static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv)
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static void enc28j60_txdone(FAR struct enc28j60_driver_s *priv)
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{
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/* Check for errors and update statistics */
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@ -455,7 +692,7 @@ static void enc28j60_txdone(FAR struct enc28j60_drver_s *priv)
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static int enc28j60_interrupt(int irq, FAR void *context)
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{
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register FAR struct enc28j60_drver_s *priv = &g_enc28j60[0];
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register FAR struct enc28j60_driver_s *priv = &g_enc28j60[0];
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/* Disable Ethernet interrupts */
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@ -498,7 +735,7 @@ static int enc28j60_interrupt(int irq, FAR void *context)
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static void enc28j60_txtimeout(int argc, uint32_t arg, ...)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)arg;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)arg;
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/* Increment statistics and dump debug info */
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@ -528,7 +765,7 @@ static void enc28j60_txtimeout(int argc, uint32_t arg, ...)
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static void enc28j60_polltimer(int argc, uint32_t arg, ...)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)arg;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)arg;
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/* Check if there is room in the send another TXr packet. */
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@ -560,7 +797,7 @@ static void enc28j60_polltimer(int argc, uint32_t arg, ...)
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static int enc28j60_ifup(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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@ -597,7 +834,7 @@ static int enc28j60_ifup(struct uip_driver_s *dev)
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static int enc28j60_ifdown(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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irqstate_t flags;
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/* Disable the Ethernet interrupt */
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@ -638,7 +875,7 @@ static int enc28j60_ifdown(struct uip_driver_s *dev)
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static int enc28j60_txavail(struct uip_driver_s *dev)
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{
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FAR struct enc28j60_drver_s *priv = (FAR struct enc28j60_drver_s *)dev->d_private;
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FAR struct enc28j60_driver_s *priv = (FAR struct enc28j60_driver_s *)dev->d_private;
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irqstate_t flags;
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flags = irqsave();
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@ -83,6 +83,24 @@
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#define ECON2 (0x1e) /* Ethernet Control 2 Register */
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#define ECON1 (0x1f) /* Ethernet Control 1 Register */
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/* The remaining control registers are identified with a a 5 bit address and a
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* bank selection. We pack the bank number and the control register address
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* together to keep the design simpler.
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*/
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#define ENC28J60_ADDR_SHIFT (0) /* Bits 0-4: Register address */
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#define ENC28J60_ADDR_MASK (0x1f << ENC28J60_ADDR_SHIFT)
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#define ENC28J60_BANK_SHIFT (5) /* Bits 5-6: Bank number */
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#define ENC28J60_BANK_MASK (3 << ENC28J60_BSEL_SHIFT)
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# define ENC28J60_BANK0 (0 << ENC28J60_BSEL_SHIFT)
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# define ENC28J60_BANK1 (1 << ENC28J60_BSEL_SHIFT)
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# define ENC28J60_BANK2 (2 << ENC28J60_BSEL_SHIFT)
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# define ENC28J60_BANK3 (3 << ENC28J60_BSEL_SHIFT)
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#define REGADDR(a,b) ((b) << ENC28J60_BANK_SHIFT | (a))
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#define GETADDR(a) ((a) & ENC28J60_ADDR_MASK)
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#define GETBANK(a) (((a) >> ENC28J60_BANK_SHIFT) & 3)
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/* Ethernet Interrupt Enable Register Bit Definitions */
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
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@ -279,7 +279,6 @@ static void skel_receive(FAR struct skel_driver_s *skel)
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}
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}
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}
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}
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while (); /* While there are more packets to be processed */
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}
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@ -592,4 +591,3 @@ int skel_initialize(void)
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}
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#endif /* CONFIG_NET && CONFIG_skeleton_NET */
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