sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add LPC43 pin configuration logic

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4914 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-07-06 18:39:04 +00:00
parent 7dd6f23388
commit 1d050fa992
4 changed files with 923 additions and 866 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1685
arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/src/lpc43xx/chip/lpc43_scu.h
View File

@ -220,7 +220,7 @@
/* Bits 0-4: Same as common bit definitions */ /* Bits 0-4: Same as common bit definitions */
#define SCU_NDPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */ #define SCU_NDPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */
/* Bits 6-31: Same as common bit definitions */ /* Bits 6-31: Same as common bit definitions */
/* Pin configuration registers for high-speed pins /* Pin configuration registers for high-drive pins
* *
* P1_17 * P1_17
* P2_3 to P2_5 * P2_3 to P2_5

72
arch/arm/src/lpc43xx/lpc43_pinconfig.c
View File

@ -77,6 +77,74 @@
int lpc43_pin_config(uint32_t pinconf) int lpc43_pin_config(uint32_t pinconf)
{ {
#warning "Missing logic" unsigned int pinset = ((pinconf & PINCONF_PINS_MASK) >> PINCONF_PINS_SHIFT);
return -ENOSYS; unsigned int pin = ((pinconf & PINCONF_PIN_MASK) >> PINCONF_PIN_SHIFT);
unsigned int func = ((pinconf & PINCONF_FUNC_MASK) >> PINCONF_FUNC_SHIFT);
uintptr_t regaddr;
uint32_t regval;
/* Get the address of the pin configuration register */
regaddr = LPC43_SCU_SFSP(pinset, pin);
/* Set up common pin configurations */
regval = (func << SCU_PIN_MODE_SHIFT);
/* Enable/disable pull-down resistor */
if (PINCONF_IS_PULLDOWN(pinconf))
{
regval |= SCU_PIN_EPD; /* Set bit to enable */
}
if (!PINCONF_IS_PULLUP(pinconf))
{
regval |= SCU_PIN_EPUN; /* Set bit to disable */
}
/* Enable/disable input buffering */
if (PINCONF_INBUFFER_ENABLED(pinconf))
{
regval |= SCU_PIN_EZI; /* Set bit to enable */
}
/* Enable/disable glitch filtering */
if (!PINCONF_GLITCH_ENABLE(pinconf))
{
regval |= SCU_PIN_ZIF; /* Set bit to disable */
}
/* Only normal and high speed pins support the slew rate setting */
if (PINCONF_IS_SLEW_FAST(pinconf))
{
regval |= SCU_NDPIN_EHS; /* 0=slow; 1=fast */
}
/* Only high drive pins suppose drive strength */
switch (pinconf & PINCONF_DRIVE_MASK)
{
default:
case PINCONF_DRIVE_NORMAL: /* Normal-drive: 4 mA drive strength (or not high drive pin) */
regval |= SCU_HDPIN_EHD_NORMAL;
break;
case PINCONF_DRIVE_MEDIUM: /* Medium-drive: 8 mA drive strength */
regval |= SCU_HDPIN_EHD_MEDIUM;
break;
case PINCONF_DRIVE_HIGH: /* High-drive: 14 mA drive strength */
regval |= SCU_HDPIN_EHD_HIGH;
break;
case PINCONF_DRIVE_ULTRA: /* Ultra high-drive: 20 mA drive strength */
regval |= SCU_HDPIN_EHD_ULTRA;
break;
}
return OK;
} }

30
arch/arm/src/lpc43xx/lpc43_pinconfig.h
View File

@ -58,23 +58,9 @@
* 1111 1111 1100 0000 0000 * 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210 * 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ---- * ---- ---- ---- ---- ----
* AFFF UUDD IGWS SSSP PPPP * .FFF UUDD IGWS SSSP PPPP
*/ */
/* Analog (input) / digital:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* A... .... .... .... ....
*/
#define PINCONF_ANALOG (1 << 19) /* Bit 19: 1=Analog */
#define PINCONF_DIGITAL (0) /* Bit 19: 0=Digial */
#define PINCONF_IS_ANALOG(p) ((p) & PINCONF_ANALOG) != 0)
#define PINCONF_IS_DIGITAL(p) ((p) & PINCONF_ANALOG) == 0)
/* Alternate function number: /* Alternate function number:
* *
* 1111 1111 1100 0000 0000 * 1111 1111 1100 0000 0000
@ -108,9 +94,9 @@
#define PINCONF_PULLDOWN (1 << 14) /* Bit 14: 1=Pull-down */ #define PINCONF_PULLDOWN (1 << 14) /* Bit 14: 1=Pull-down */
#define PINCONF_FLOAT (0) /* Bit 14-15=0 if neither */ #define PINCONF_FLOAT (0) /* Bit 14-15=0 if neither */
#define PINCONF_IS_PULLUP(p) ((p) & PINCONF_PULLUP) != 0) #define PINCONF_IS_PULLUP(p) (((p) & PINCONF_PULLUP) != 0)
#define PINCONF_IS_PULLDOWN(p) ((p) & PINCONF_PULLDOWN) != 0) #define PINCONF_IS_PULLDOWN(p) (((p) & PINCONF_PULLDOWN) != 0)
#define PINCONF_IS_FLOAT(p) ((p) & (PINCONF_PULLUP|PINCONF_PULLDOWN) == 0) #define PINCONF_IS_FLOAT(p) (((p) & (PINCONF_PULLUP|PINCONF_PULLDOWN) == 0)
/* Drive strength. These selections are available only for high-drive pins /* Drive strength. These selections are available only for high-drive pins
* *
@ -136,7 +122,7 @@
*/ */
#define PINCONF_INBUFFER (1 << 11) /* Bit 11: 1=Enabled input buffer */ #define PINCONF_INBUFFER (1 << 11) /* Bit 11: 1=Enabled input buffer */
#define PINCONF_INBUFFER_ENABLED(p) ((p) & PINCONF_INBUFFER) != 0) #define PINCONF_INBUFFER_ENABLED(p) (((p) & PINCONF_INBUFFER) != 0)
/* Glitch filter enable /* Glitch filter enable
* *
@ -147,7 +133,7 @@
*/ */
#define PINCONF_GLITCH (1 << 10) /* Bit 10: 1=Glitch filter enable */ #define PINCONF_GLITCH (1 << 10) /* Bit 10: 1=Glitch filter enable */
#define PINCONF_GLITCH_ENABLE(p) ((p) & PINCONF_GLITCH) == 0) #define PINCONF_GLITCH_ENABLE(p) (((p) & PINCONF_GLITCH) == 0)
/* Slew rate /* Slew rate
* *
@ -160,8 +146,8 @@
#define PINCONF_SLEW_FAST (1 << 9) /* Bit 9: 1=Alternate function */ #define PINCONF_SLEW_FAST (1 << 9) /* Bit 9: 1=Alternate function */
#define PINCONF_SLEW_SLOW (0) /* Bit 9: 0=Normal function */ #define PINCONF_SLEW_SLOW (0) /* Bit 9: 0=Normal function */
#define PINCONF_IS_SLEW_FAST(p) ((p) & PINCONF_SLEW_FAST) != 0) #define PINCONF_IS_SLEW_FAST(p) (((p) & PINCONF_SLEW_FAST) != 0)
#define PINCONF_IS_SLOW_SLOW(p) ((p) & PINCONF_SLEW_FAST) == 0) #define PINCONF_IS_SLOW_SLOW(p) (((p) & PINCONF_SLEW_FAST) == 0)
/* Pin configuration sets: /* Pin configuration sets:
* *