SAMA5 LCDC: Wait when the LCDC is resynchronizing (SIF); Try start-up parameters from Barebox (this still don't work)
This commit is contained in:
Gregory Nutt
parent
57d04d3ff5
commit
1d0e7aaeff
@ -77,7 +77,19 @@
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#endif
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#define SAMA5_LCDC_BACKLIGHT_OFF 0x00
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/* Color formats */
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/* Color/video formats */
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#if defined(CONFIG_SAMA5_LCDC_OUTPUT_12BPP)
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# define SAMA5_LCDC_OUTPUT_BPP 12
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_16BPP)
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# define SAMA5_LCDC_OUTPUT_BPP 16
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_18BPP)
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# define SAMA5_LCDC_OUTPUT_BPP 18
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_24BPP)
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# define SAMA5_LCDC_OUTPUT_BPP 24
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#else
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# error No output resolution defined
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#endif
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#if defined(CONFIG_SAMA5_LCDC_BASE_RGB444)
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# define SAMA5_LCDC_BASE_BPP 16 /* 12BPP but must be 16-bit aligned */
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@ -589,6 +601,7 @@ static void sam_putreg(uintptr_t addr, uint32_t val);
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# define sam_getreg(addr) getreg32(addr)
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# define sam_putreg(addr,val) putreg32(val,addr)
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#endif
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static void sam_wait_lcdstatus(uint32_t mask, uint32_t value);
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/* Frame buffer interface ***************************************************/
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/* Get information about the video controller configuration and the
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@ -700,13 +713,18 @@ static pio_pinset_t g_lcdcpins[] =
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{
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PIO_LCD_DAT0, PIO_LCD_DAT2, PIO_LCD_DAT1, PIO_LCD_DAT3,
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PIO_LCD_DAT4, PIO_LCD_DAT5, PIO_LCD_DAT6, PIO_LCD_DAT7,
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PIO_LCD_DAT8, PIO_LCD_DAT9, PIO_LCD_DAT10, PIO_LCD_DAT11,
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#if SAMA5_LCDC_OUTPUT_BPP > 12
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PIO_LCD_DAT12, PIO_LCD_DAT13, PIO_LCD_DAT14, PIO_LCD_DAT15,
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#if SAMA5_LCDC_BASE_BPP > 16
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PIO_LCD_DAT16, PIO_LCD_DAT17, PIO_LCD_DAT18, PIO_LCD_DAT19,
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#if SAMA5_LCDC_OUTPUT_BPP > 16
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PIO_LCD_DAT16, PIO_LCD_DAT17,
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#if SAMA5_LCDC_OUTPUT_BPP > 18
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PIO_LCD_DAT18, PIO_LCD_DAT19,
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PIO_LCD_DAT20, PIO_LCD_DAT21, PIO_LCD_DAT22, PIO_LCD_DAT23,
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#endif
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#endif
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#endif
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PIO_LCD_PWM, PIO_LCD_DISP, PIO_LCD_VSYNC, PIO_LCD_HSYNC,
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@ -1044,6 +1062,20 @@ static void sam_putreg(uintptr_t address, uint32_t regval)
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}
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#endif
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/****************************************************************************
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* Name: sam_wait_lcdstatus
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*
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* Description:
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* Wait for the masked set of bits in the LCDC status register to take a
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* specific value.
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*
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****************************************************************************/
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static void sam_wait_lcdstatus(uint32_t mask, uint32_t value)
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{
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while ((sam_getreg(SAM_LCDC_LCDSR) & mask) != value);
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}
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/****************************************************************************
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* Name: sam_base_getvideoinfo
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****************************************************************************/
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@ -1503,7 +1535,7 @@ static void sam_backlight(uint32_t level)
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/* And wait for the PWM to be disabled */
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_PWM) != 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_PWM, 0);
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}
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#ifdef CONFIG_SAMA5_LCDC_BACKLIGHT
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else
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@ -1865,7 +1897,7 @@ static void sam_lcd_disable(void)
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* is no longer activated.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_DISP) != 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_DISP, 0);
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/* 3. Disable the hsync and vsync signals by writing one to SYNCDIS field of
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* the LCDC_LCDDIS register.
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@ -1877,7 +1909,7 @@ static void sam_lcd_disable(void)
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* synchronization is off.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_LCD) != 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_LCD, 0);
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/* 5. Disable the Pixel clock by writing one in the CLKDIS field of the
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* LCDC_LCDDIS register.
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@ -1889,7 +1921,7 @@ static void sam_lcd_disable(void)
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* is disabled.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_CLK) != 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_CLK, 0);
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/* Disable peripheral clock */
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@ -2029,21 +2061,30 @@ static void sam_layer_color(void)
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/* Base channel color configuration */
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#ifdef CONFIG_SAMA5_LCDC_BASE_RGB888P
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#if defined(CONFIG_SAMA5_LCDC_BASE_RGB888P)
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LAYER_BASE->bpp = 24;
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sam_putreg(SAM_LCDC_BASECFG0,
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LCDC_BASECFG0_DLBO | LCDC_BASECFG0_BLEN_INCR16);
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sam_putreg(SAM_LCDC_BASECFG1,
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LCDC_BASECFG1_24BPP_RGB888P);
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# elif defined(CONFIG_SAMA5_LCDC_BASE_RGB565)
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LAYER_BASE->bpp = 16;
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sam_putreg(SAM_LCDC_BASECFG0,
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LCDC_BASECFG0_DLBO | LCDC_BASECFG0_BLEN_INCR4);
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sam_putreg(SAM_LCDC_BASECFG1,
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LCDC_BASECFG1_16BPP_RGB565);
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#else
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# error Support for this resolution is not yet supported
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# error Support for this resolution is not yet supported
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#endif
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#ifdef CONFIG_SAMA5_LCDC_OVR1
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# ifdef CONFIG_SAMA5_LCDC_OVR1_RGB888P
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/* Overlay 1 color configuration, GA 0xff */
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# if defined(CONFIG_SAMA5_LCDC_OVR1_RGB888P)
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LAYER_OVR1->bpp = 24;
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sam_putreg(SAM_LCDC_OVR1CFG0,
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@ -2053,15 +2094,27 @@ static void sam_layer_color(void)
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LCDC_OVR1CFG1_24BPP_RGB888P);
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sam_putreg(SAM_LCDC_OVR1CFG9,
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LCDC_OVR1CFG9_GA(0xff) | LCDC_OVR1CFG9_GAEN);
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# elif defined(CONFIG_SAMA5_LCDC_OVR1_RGB565)
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LAYER_OVR1->bpp = 16;
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sam_putreg(SAM_LCDC_OVR1CFG0,
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LCDC_OVR1CFG0_DLBO | LCDC_OVR1CFG0_BLEN_INCR4 |
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LCDC_OVR1CFG0_ROTDIS);
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sam_putreg(SAM_LCDC_OVR1CFG1,
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LCDC_OVR1CFG1_16BPP_RGB565);
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sam_putreg(SAM_LCDC_OVR1CFG9,
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LCDC_OVR1CFG9_GA(0xff) | LCDC_OVR1CFG9_GAEN);
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# else
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# error Support for this resolution is not yet supported
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# error Support for this resolution is not yet supported
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# endif
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#endif
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#ifdef CONFIG_SAMA5_LCDC_OVR2
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# ifdef CONFIG_SAMA5_LCDC_OVR2_RGB888P
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/* Overlay 2 color configuration, GA 0xff */
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# if defined(CONFIG_SAMA5_LCDC_OVR2_RGB888P)
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LAYER_OVR2->bpp = 24;
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sam_putreg(SAM_LCDC_OVR2CFG0,
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@ -2071,15 +2124,27 @@ static void sam_layer_color(void)
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LCDC_OVR2CFG1_24BPP_RGB888P);
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sam_putreg(SAM_LCDC_OVR2CFG9,
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LCDC_OVR2CFG9_GA(0xff) | LCDC_OVR2CFG9_GAEN;
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# elif defined(CONFIG_SAMA5_LCDC_OVR2_RGB565)
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LAYER_OVR2->bpp = 16;
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sam_putreg(SAM_LCDC_OVR2CFG0,
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LCDC_OVR2CFG0_DLBO | LCDC_OVR2CFG0_BLEN_INCR4 |
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LCDC_OVR2CFG0_ROTDIS);
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sam_putreg(SAM_LCDC_OVR2CFG1,
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LCDC_OVR2CFG1_16BPP_RGB565);
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sam_putreg(SAM_LCDC_OVR2CFG9,
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LCDC_OVR2CFG9_GA(0xff) | LCDC_OVR2CFG9_GAEN);
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# else
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# error Support for this resolution is not yet supported
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# error Support for this resolution is not yet supported
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# endif
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#endif
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#ifdef CONFIG_SAMA5_LCDC_HEO
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# ifdef CONFIG_SAMA5_LCDC_HEO_RGB888P
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/* High End Overlay color configuration, GA 0xff */
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# if defined(CONFIG_SAMA5_LCDC_HEO_RGB888P)
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LAYER_HEO->bpp = 24;
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sam_putreg(SAM_LCDC_HEOCFG0,
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@ -2089,15 +2154,27 @@ static void sam_layer_color(void)
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LCDC_HEOCFG1_24BPP_RGB888P);
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sam_putreg(SAM_LCDC_HEOCFG12,
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LCDC_HEOCFG12_GA(0xff) | LCDC_HEOCFG12_GAEN);
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# elif defined(CONFIG_SAMA5_LCDC_HEO_RGB565)
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LAYER_HEO->bpp = 16;
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sam_putreg(SAM_LCDC_HEOCFG0,
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LCDC_HEOCFG0_DLBO | LCDC_HEOCFG0_BLEN_INCR4 |
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LCDC_HEOCFG0_ROTDIS);
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sam_putreg(SAM_LCDC_HEOCFG1,
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LCDC_HEOCFG1_16BPP_RGB565);
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sam_putreg(SAM_LCDC_HEOCFG9,
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LCDC_HEOCFG9_GA(0xff) | LCDC_HEOCFG9_GAEN);
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# else
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# error Support for this resolution is not yet supported
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# error Support for this resolution is not yet supported
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# endif
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#endif
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#ifdef CONFIG_FB_HWCURSOR
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# ifdef CONFIG_SAMA5_LCDC_HEO_RGB888P
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/* Hardware Cursor color configuration, GA 0xff, Key #000000 */
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# if defined(CONFIG_SAMA5_LCDC_HCR_RGB888P)
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LAYER_HCR->bpp = 24;
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sam_putreg(SAM_LCDC_HCRCFG0,
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@ -2110,8 +2187,20 @@ static void sam_layer_color(void)
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0xffffff);
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sam_putreg(SAM_LCDC_HCRCFG9,
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LCDC_HCRCFG9_GAEN(0xff) | LCDC_HCRCFG9_GAEN);
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# elif defined(CONFIG_SAMA5_LCDC_HCR_RGB565)
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LAYER_HCR->bpp = 16;
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sam_putreg(SAM_LCDC_HCRCFG0,
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LCDC_HCRCFG0_DLBO | LCDC_HCRCFG0_BLEN_INCR4 |
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LCDC_HCRCFG0_ROTDIS);
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sam_putreg(SAM_LCDC_HCRCFG1,
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LCDC_HCRCFG1_16BPP_RGB565);
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sam_putreg(SAM_LCDC_HCRCFG9,
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LCDC_HCRCFG9_GA(0xff) | LCDC_HCRCFG9_GAEN);
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# else
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# error Support for this resolution is not yet supported
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# error Support for this resolution is not yet supported
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# endif
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#endif
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}
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@ -2139,24 +2228,35 @@ static void sam_lcd_enable(void)
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/* 1. Configure LCD timing parameters, signal polarity and clock period. */
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div = ((2 * BOARD_MCK_FREQUENCY) / BOARD_LCD_PIXELCLOCK) - 2;
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regval = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CLKSEL |
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LCDC_LCDCFG0_CLKPWMSEL | LCDC_LCDCFG0_CGDISBASE |
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LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISOVR2 |
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LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISHCR |
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LCDC_LCDCFG0_CLKDIV(div);
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div = (BOARD_MCK_FREQUENCY + (BOARD_LCD_PIXELCLOCK-1)) / BOARD_LCD_PIXELCLOCK;
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DEBUGASSERT(div > 1);
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regval = LCDC_LCDCFG0_CLKPOL | LCDC_LCDCFG0_CGDISBASE |
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LCDC_LCDCFG0_CLKDIV(div - 2);
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#ifdef CONFIG_SAMA5_LCDC_OVR1
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regval |= LCDC_LCDCFG0_CGDISOVR1;
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#endif
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#ifdef CONFIG_SAMA5_LCDC_OVR2
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regval |= LCDC_LCDCFG0_CGDISOVR2;
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#endif
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#ifdef CONFIG_SAMA5_LCDC_HEO
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regval |= LCDC_LCDCFG0_CGDISHEO;
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#endif
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#ifdef CONFIG_SAMA5_LCDC_HCR
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regval |= LCDC_LCDCFG0_CGDISHCR;
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#endif
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sam_putreg(SAM_LCDC_LCDCFG0, regval);
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regval = LCDC_LCDCFG1_HSPW(BOARD_LCD_TIMING_HPW - 1) |
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LCDC_LCDCFG1_VSPW(BOARD_LCD_TIMING_VPW - 1);
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regval = LCDC_LCDCFG1_HSPW(BOARD_LCD_HSPW - 1) |
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LCDC_LCDCFG1_VSPW(BOARD_LCD_VSPW - 1);
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sam_putreg(SAM_LCDC_LCDCFG1, regval);
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regval = LCDC_LCDCFG2_VFPW(BOARD_LCD_TIMING_VFP - 1) |
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LCDC_LCDCFG2_VBPW(BOARD_LCD_TIMING_VBP);
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regval = LCDC_LCDCFG2_VFPW(BOARD_LCD_VFPW - 1) |
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LCDC_LCDCFG2_VBPW(BOARD_LCD_VBPW);
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sam_putreg(SAM_LCDC_LCDCFG2, regval);
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regval = LCDC_LCDCFG3_HFPW(BOARD_LCD_TIMING_HFP - 1) |
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LCDC_LCDCFG3_HBPW(BOARD_LCD_TIMING_HBP - 1);
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regval = LCDC_LCDCFG3_HFPW(BOARD_LCD_HFPW - 1) |
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LCDC_LCDCFG3_HBPW(BOARD_LCD_HBPW - 1);
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sam_putreg(SAM_LCDC_LCDCFG3, regval);
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regval = LCDC_LCDCFG4_PPL(BOARD_LCD_WIDTH - 1) |
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@ -2165,7 +2265,18 @@ static void sam_lcd_enable(void)
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regval = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL |
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LCDC_LCDCFG5_VSPDLYS | LCDC_LCDCFG5_DISPDLY |
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LCDC_LCDCFG5_MODE_24BPP | LCDC_LCDCFG5_GUARDTIME(30);
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LCDC_LCDCFG5_GUARDTIME(BOARD_LCDC_GUARDTIME);
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#if defined(CONFIG_SAMA5_LCDC_OUTPUT_12BPP)
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regval |= LCDC_LCDCFG5_MODE_12BPP;
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_16BPP)
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regval |= LCDC_LCDCFG5_MODE_16BPP;
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_18BPP)
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regval |= LCDC_LCDCFG5_MODE_18BPP;
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#elif defined(CONFIG_SAMA5_LCDC_OUTPUT_24BPP)
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regval |= LCDC_LCDCFG5_MODE_24BPP;
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#else
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# error Unknown output resolution
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#endif
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sam_putreg(SAM_LCDC_LCDCFG5, regval);
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regval = LCDC_LCDCFG6_PWMPS_DIV64 | LCDC_LCDCFG6_PWMPOL |
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@ -2182,7 +2293,7 @@ static void sam_lcd_enable(void)
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* is running.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_CLK) == 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_CLK, LCDC_LCDSR_CLK);
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/* 4. Enable Horizontal and Vertical Synchronization by writing one to the
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* SYNCEN field of the LCDC_LCDEN register.
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@ -2194,7 +2305,7 @@ static void sam_lcd_enable(void)
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* synchronization is up.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_LCD) == 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_LCD, LCDC_LCDSR_LCD);
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/* 6. Enable the display power signal writing one to the DISPEN field of the
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* LCDC_LCDEN register.
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@ -2206,7 +2317,7 @@ static void sam_lcd_enable(void)
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* signal is activated.
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*/
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while ((sam_getreg(SAM_LCDC_LCDSR) & LCDC_LCDSR_DISP) == 0);
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sam_wait_lcdstatus(LCDC_LCDSR_SIP | LCDC_LCDSR_DISP, LCDC_LCDSR_DISP);
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}
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/****************************************************************************
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