xtensa: move fpu register to XCPTCONTEXT_REGS

1 move fpu register to XCP_REGS
2 move save & restore fpu register to context_save/restore

Consistency with other archs.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>

arch/xtensa/include/irq.h

@@ -118,12 +118,25 @@
 /* Storage for overlay state */
 
 #  error Overlays not supported
-#  define XCPTCONTEXT_REGS  _REG_OVLY_START
+#  define _REG_CP_START  _REG_OVLY_START
 #else
-#  define XCPTCONTEXT_REGS  _REG_OVLY_START
+#  define _REG_CP_START  _REG_OVLY_START
 #endif
 
+#if XCHAL_CP_NUM > 0
+#  if (XCHAL_TOTAL_SA_ALIGN == 8) && ((_REG_CP_START & 1) == 1)
+  /* Fpu first address must align to cp align size. */
+
+#    define REG_CP_DUMMY      (_REG_CP_START + 0)
+#    define XCPTCONTEXT_REGS  (_REG_CP_START + 1)
+#  else
+#    define XCPTCONTEXT_REGS  _REG_CP_START
+#  endif
+#  define XCPTCONTEXT_SIZE    ((4 * XCPTCONTEXT_REGS) + XTENSA_CP_SA_SIZE + 0x20)
+#else
+#  define XCPTCONTEXT_REGS    _REG_CP_START
 #  define XCPTCONTEXT_SIZE    ((4 * XCPTCONTEXT_REGS) + 0x20)
+#endif
 
 /****************************************************************************
  * Public Types
@@ -155,12 +168,6 @@ struct xcptcontext
 
   uint32_t *regs;
 
-#if XCHAL_CP_NUM > 0
-  /* Co-processor save area */
-
-  struct xtensa_cpstate_s cpstate;
-#endif
-
 #ifdef CONFIG_LIB_SYSCALL
   /* The following array holds the return address and the exc_return value
    * needed to return from each nested system call.

arch/xtensa/src/common/xtensa.h

@@ -285,11 +285,6 @@ int xtensa_intercpu_interrupt(int tocpu, int intcode);
 void xtensa_pause_handler(void);
 #endif
 
-#if XCHAL_CP_NUM > 0
-void xtensa_coproc_savestate(struct xtensa_cpstate_s *cpstate);
-void xtensa_coproc_restorestate(struct xtensa_cpstate_s *cpstate);
-#endif
-
 /* Signals */
 
 void _xtensa_sig_trampoline(void);

arch/xtensa/src/common/xtensa_context.S

@@ -200,6 +200,15 @@ _xtensa_context_save:
 
 #endif
 
+#if XCHAL_CP_NUM > 0
+	s32i    a0, sp, (4 * REG_TMP0)     /* Save return address */
+
+	mov	a2, sp
+	call0	_xtensa_coproc_savestate
+
+	l32i	a0, sp, (4 * REG_TMP0)       /* Restore return address */
+#endif
+
 	ret
 
 	.size	_xtensa_context_save, . - _xtensa_context_save
@@ -239,6 +248,14 @@ _xtensa_context_save:
 
 _xtensa_context_restore:
 
+#if XCHAL_CP_NUM > 0
+	s32i    a0, a2, (4 * REG_TMP0)	     /* Save return address */
+
+	call0	_xtensa_coproc_restorestate
+
+	l32i	a0, a2, (4 * REG_TMP0)       /* Restore return address */
+#endif
+
 #if XCHAL_HAVE_LOOPS != 0
 	l32i	a3, a2, (4 * REG_LBEG)
 	l32i	a4, a2, (4 * REG_LEND)

arch/xtensa/src/common/xtensa_coproc.S

@@ -39,6 +39,7 @@
 
 #include <nuttx/config.h>
 
+#include <arch/irq.h>
 #include <arch/xtensa/core.h>
 #include <arch/xtensa/xtensa_abi.h>
 #include <arch/xtensa/xtensa_coproc.h>
@@ -88,9 +89,7 @@ _xtensa_coproc_saoffsets:
  *   around the assembly language call to _xtensa_coproc_savestate.
  *
  * Entry Conditions:
- *   - A2 holds the address of the co-processor state save area
+ *   - A2 holds the address of current interrupt stack pointer.
- *   - The thread being switched out is still the current thread.
- *   - CPENABLE state reflects which coprocessors are active.
  *   - Registers have been saved/spilled already.
  *
  * Exit conditions:
@@ -112,21 +111,31 @@ _xtensa_coproc_savestate:
 
 	/* Move the address of the thread state save area to R15 */
 
-	mov		a15, a2							/* A15 is now the address of the save area */
+	mov		a3, a2					/* A3 is now the address of the save area */
+
+	/* The stack when interrupt happened (the register a2)
+	* ----------------------------------------------------
+	* | Reserve area (0x20)                              |
+	* ----------------------------------------------------
+	* | Coproc context                                   |
+	* ----------------------------------------------------
+	* | Xtensa common regs                               |
+	* ---------------------------------------------------| <- SP
+	*/
+
+	addi		a3, a3, (4 * XCPTCONTEXT_REGS)
 
 	/* CPENABLE should show which CPs are enabled. */
 
 	rsr		a2, CPENABLE				/* a2 = which CPs are enabled */
 	beqz		a2, .Ldone1				/* Quick exit if none */
 
-	s16i	a2, a15, XTENSA_CPSTORED		/* Save mask of CPs being stored */
 	movi		a13, _xtensa_coproc_saoffsets		/* Array of CP save offsets */
-	addi	a15, a15, XTENSA_CPASA			/* a15 = base of aligned save area */
 
 #if XCHAL_CP0_SA_SIZE > 0
 	bbci.l		a2,  0,   2f				/* CP 0 not enabled */
 	l32i		a14, a13, 0				/* a14 = _xtensa_coproc_saoffsets[0] */
-	add		a3, a14, a15					/* a3 = save area for CP 0 */
+	add		a3,  a14, a3				/* a3 = save area for CP 0 */
 	xchal_cp0_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -134,7 +143,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP1_SA_SIZE > 0
 	bbci.l		a2,  1,   2f				/* CP 1 not enabled */
 	l32i		a14, a13, 4				/* a14 = _xtensa_coproc_saoffsets[1] */
-	add		a3, a14, a15					/* a3 = save area for CP 1 */
+	add		a3,  a14, a3				/* a3 = save area for CP 1 */
 	xchal_cp1_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -142,7 +151,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP2_SA_SIZE > 0
 	bbci.l		a2,  2,   2f
 	l32i		a14, a13, 8
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp2_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -150,7 +159,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP3_SA_SIZE > 0
 	bbci.l		a2,  3,   2f
 	l32i		a14, a13, 12
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp3_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -158,7 +167,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP4_SA_SIZE > 0
 	bbci.l		a2,  4,   2f
 	l32i		a14, a13, 16
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp4_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -166,7 +175,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP5_SA_SIZE > 0
 	bbci.l		a2,  5,   2f
 	l32i		a14, a13, 20
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp5_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -174,7 +183,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP6_SA_SIZE > 0
 	bbci.l		a2,  6,   2f
 	l32i		a14, a13, 24
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp6_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -182,7 +191,7 @@ _xtensa_coproc_savestate:
 #if XCHAL_CP7_SA_SIZE > 0
 	bbci.l		a2,  7,   2f
 	l32i		a14, a13, 28
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp7_store	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -192,83 +201,6 @@ _xtensa_coproc_savestate:
 
 	.size	_xtensa_coproc_savestate, . - _xtensa_coproc_savestate
 
-/****************************************************************************
- * Name: xtensa_coproc_savestate
- *
- * Description:
- *   If there is a current thread and it has a coprocessor state save area,
- *   then save all callee-saved state into this area. xtensa_coproc_savestate()
- *   is simply a C wrapper around the assembly language call to
- *   _xtensa_coproc_savestate.
- *
- * Input Parameters:
- *   A2 - Address of co-processor save area
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *   Called with interrupts disabled.
- *
- ****************************************************************************/
-
-	.global	xtensa_coproc_savestate
-	.type	xtensa_coproc_savestate, @function
-
-	.align	4
-	.literal_position
-	.align	4
-
-xtensa_coproc_savestate:
-
-#ifdef __XTENSA_CALL0_ABI__
-	/* Need to preserve a8-11.  _xtensa_coproc_savestate modifies a2-a7,
-	 * a13-a15. a12-a15 are callee saved registers so a13-a14 must be
-	 * preserved.
-	 */
-
-	ENTRY(16)
-	s32i	a13, sp, LOCAL_OFFSET(1)		/* Save clobbered registers */
-	s32i	a14, sp, LOCAL_OFFSET(2)
-	s32i	a15, sp, LOCAL_OFFSET(3)
-
-	/* Call _xtensa_coproc_savestate() with A2=address of co-processor
-	 * save area.
-	 */
-
-	call0 _xtensa_coproc_savestate
-
-	/* Restore a13-15 and return */
-
-	l32i	a13, sp, LOCAL_OFFSET(1)		/* Restore clobbered registers */
-	l32i	a14, sp, LOCAL_OFFSET(2)
-	l32i	a15, sp, LOCAL_OFFSET(3)
-	RET(16)
-
-#else
-	/* Allocate the stack frame.  This function needs to allocate the usual 16
-	 * byte for the base save area + space for one variable.
-	 * NOTE: entry works in multiples of 8 bytes.
-	 */
-
-	ENTRY(24)
-	s32i	a0,  sp, LOCAL_OFFSET(0)		/* Save return address */
-
-	/* Call _xtensa_coproc_savestate() with A2=address of co-processor
-	 * save area.
-	 */
-
-	call0 _xtensa_coproc_savestate
-
-	/* Restore a0 and return */
-
-	l32i	a0,  sp, LOCAL_OFFSET(0)		/* Recover return address */
-	RET(24)
-
-#endif
-
-	.size	xtensa_coproc_savestate, . - xtensa_coproc_savestate
-
 /****************************************************************************
  * Name: _xtensa_coproc_restorestate
  *
@@ -284,12 +216,10 @@ xtensa_coproc_savestate:
  *   around the assembly language call to _xtensa_coproc_restorestate.
  *
  * Entry Conditions:
- *   - A2 holds the address of the co-processor state save area
+ *   - A2 holds the address of the current interrupt stack pointer.
- *   - The incoming thread is set as the current thread.
  *
  * Exit conditions:
  *   - All necessary CP callee-saved state has been restored.
- *   - CPENABLE - Set up correctly for the current thread.
  *   - Registers a2-a7, a13-a15 have been trashed.
  *
  * Must be called from assembly code only, using CALL0.
@@ -307,81 +237,85 @@ _xtensa_coproc_restorestate:
 
 	/* Move the address of the thread state save area to R15 */
 
-	mov		a15, a2							/* A15 is now the address of the save area */
+	mov		a3, a2				/* A3 is now the address of the save area */
 
-#ifdef CONFIG_XTENSA_CP_LAZY
+	/* The stack when interrupt happened (the register A2)
-	movi	a2, 0							/* a2 = Will disable all coprocessors */
+	* ----------------------------------------------------
-#else
+	* | Reserve area (0x20)                              |
-	l16ui	a2, a15, XTENSA_CPENABLE		/* a2 = Which CPs have been enable for this thread? */
+	* ----------------------------------------------------
-#endif
+	* | Coproc context                                   |
-	wsr		a2, CPENABLE					/* Set CPENABLE correctly for this thread */
+	* ----------------------------------------------------
-	l16ui	a2, a15, XTENSA_CPSTORED		/* a2 = Which CPs have been saved for this thread? */
+	* | Xtensa common regs                               |
-	movi	a3, 0							/* Clear the ones being restored (all of them) */
+	* ---------------------------------------------------| <- SP
-	s16i	a3, a15, XTENSA_CPSTORED		/* Clear saved CP mask */
+	*/
+
+	addi		a3, a3, (4 * XCPTCONTEXT_REGS)
+
+	rsr		a8, CPENABLE			/* Set CPENABLE correctly for this thread */
+	beqz		a8, .Ldone1			/* Quick exit if none */
 
 	movi		a13, _xtensa_coproc_saoffsets	/* Array of CP save offsets */
-	addi	a15, a15, XTENSA_CPASA			/* a15 = base of aligned save area */
 
 #if XCHAL_CP0_SA_SIZE
-	bbci.l	a2, 0, 2f						/* CP 0 not enabled */
+	bbci.l		a8,  0,   2f			/* CP 0 not enabled */
 	l32i		a14, a13, 0			/* a14 = _xtensa_coproc_saoffsets[0] */
-	add		a3, a14, a15					/* a3 = save area for CP 0 */
+	add		a3,  a14, a3			/* a3 = save area for CP 0 */
 	xchal_cp0_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP1_SA_SIZE
-	bbci.l	a2, 1, 2f						/* CP 1 not enabled */
+	bbci.l		a8,  1,   2f			/* CP 1 not enabled */
 	l32i		a14, a13, 4			/* a14 = _xtensa_coproc_saoffsets[1] */
-	add		a3, a14, a15					/* a3 = save area for CP 1 */
+	add		a3,  a14, a3			/* a3 = save area for CP 1 */
 	xchal_cp1_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP2_SA_SIZE
-	bbci.l	a2, 2, 2f
+	bbci.l		a8,  2,   2f
 	l32i		a14, a13, 8
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp2_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP3_SA_SIZE
-	bbci.l	a2, 3, 2f
+	bbci.l		a8,  3,   2f
 	l32i		a14, a13, 12
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp3_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP4_SA_SIZE
-	bbci.l	a2, 4, 2f
+	bbci.l		a8,  4,   2f
 	l32i		a14, a13, 16
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp4_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP5_SA_SIZE
-	bbci.l	a2, 5, 2f
+	bbci.l		a8,  5,   2f
 	l32i		a14, a13, 20
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp5_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP6_SA_SIZE
-	bbci.l	a2, 6, 2f
+	bbci.l		a8,  6,   2f
 	l32i		a14, a13, 24
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp6_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
 
 #if XCHAL_CP7_SA_SIZE
-	bbci.l	a2, 7, 2f
+	bbci.l		a8,  7,   2f
 	l32i		a14, a13, 28
-	add		a3, a14, a15
+	add		a3,  a14, a3
 	xchal_cp7_load	a3,  a4,  a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
 2:
 #endif
@@ -392,80 +326,4 @@ _xtensa_coproc_restorestate:
 
 	.size	_xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate
 
-/****************************************************************************
- * Name: xtensa_coproc_restorestate
- *
- * Description:
- *   Restore any callee-saved coprocessor state for the incoming thread.
- *   xtensa_coproc_restorestate() is simply a C wrapper around the assembly
- *   language call to _xtensa_coproc_restorestate.
- *
- * Input Parameters:
- *   - A2 holds the address of the threads state save area
- *
- * Returned Value:
- *   None
- *
- * Assumptions:
- *   Called with interrupts disabled.
- *
- ****************************************************************************/
-
-	.global	xtensa_coproc_restorestate
-	.type	xtensa_coproc_restorestate, @function
-
-	.align	4
-	.literal_position
-	.align	4
-
-xtensa_coproc_restorestate:
-
-#ifdef __XTENSA_CALL0_ABI__
-	/* Need to preserve a8-11.  _xtensa_coproc_restorestate modifies a2-a7,
-	 * a13-a15. a12-a15 are callee saved registers so a13-a14 must be
-	 * preserved.
-	 */
-
-	ENTRY(16)
-	s32i	a13, sp, LOCAL_OFFSET(1)		/* Save clobbered values */
-	s32i	a14, sp, LOCAL_OFFSET(2)
-	s32i	a15, sp, LOCAL_OFFSET(3)
-
-	/* Call _xtensa_coproc_restorestate() with A2=address of co-processor
-	 * save area.   Registers a0, a2-a7, a13-a15 have been trashed.
-	 */
-
-	call0 _xtensa_coproc_restorestate
-
-	/* Restore a13-a15 and return */
-
-	l32i	a13, sp, LOCAL_OFFSET(1)		/* Restore clobbered registers */
-	l32i	a14, sp, LOCAL_OFFSET(2)
-	l32i	a15, sp, LOCAL_OFFSET(3)
-	RET(16)
-
-#else
-	/* Allocate the stack frame.  This function needs to allocate the usual 16
-	 * byte for the base save area + space for one variable.
-	 * NOTE: entry works in multiples of 8 bytes.
-	 */
-
-	ENTRY(24)
-	s32i	a0,  sp, LOCAL_OFFSET(0)		/* Save return address */
-
-	/* Call _xtensa_coproc_restorestate() with A2=address of co-processor
-	 * save area.   Registers a0, a2-a7, a13-a15 have been trashed.
-	 */
-
-	call0 _xtensa_coproc_restorestate
-
-	/* Restore a0 and return */
-
-	l32i	a0,  sp, LOCAL_OFFSET(0)		/* Recover return address */
-	RET(24)
-
-#endif
-
-  .size	xtensa_coproc_restorestate, . - xtensa_coproc_restorestate
-
 #endif /* XCHAL_CP_NUM > 0 */

arch/xtensa/src/common/xtensa_exit.c

@@ -116,12 +116,6 @@ void up_exit(int status)
 
   sinfo("TCB=%p exiting\n", tcb);
 
-#if XCHAL_CP_NUM > 0
-  /* Disable co-processor support for the task that is exit-ing. */
-
-  xtensa_coproc_disable(&tcb->xcp.cpstate, XTENSA_CP_ALLSET);
-#endif
-
   /* Destroy the task at the head of the ready to run list. */
 
   nxtask_exit();

arch/xtensa/src/common/xtensa_initialize.c

@@ -84,6 +84,10 @@ static inline void xtensa_color_intstack(void)
 
 void up_initialize(void)
 {
+#if XCHAL_CP_NUM > 0
+  xtensa_set_cpenable(CONFIG_XTENSA_CP_INITSET);
+#endif
+
   xtensa_color_intstack();
 
   /* Add any extra memory fragments to the memory manager */

arch/xtensa/src/common/xtensa_initialstate.c

@@ -108,18 +108,4 @@ void up_initial_state(struct tcb_s *tcb)
 
   xcp->regs[REG_PS]   = PS_UM | PS_WOE | PS_CALLINC(1);
 #endif
-
-#if XCHAL_CP_NUM > 0
-  /* Set up the co-processors that will be enabled initially when the thread
-   * starts (see xtensa_coproc.h).  If the lazy co-processor state restore
-   * logic is selected, that would be the empty set.
-   */
-
-#ifdef CONFIG_XTENSA_CP_LAZY
-  xcp->cpstate.cpenable = 0;  /* No co-processors are enabled */
-#else
-  xcp->cpstate.cpenable = (CONFIG_XTENSA_CP_INITSET & XTENSA_CP_ALLSET);
-#endif
-  xcp->cpstate.cpstored = 0;  /* No co-processors haved state saved */
-#endif
 }

arch/xtensa/src/common/xtensa_irqdispatch.c

@@ -49,11 +49,6 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs)
   PANIC();
 
 #else
-#if XCHAL_CP_NUM > 0
-  /* Save the TCB of in case we need to save co-processor state */
-
-  struct tcb_s *tcb = this_task();
-#endif
 
   board_autoled_on(LED_INIRQ);
 
@@ -76,35 +71,13 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs)
 
   irq_dispatch(irq, regs);
 
-#if XCHAL_CP_NUM > 0 || defined(CONFIG_ARCH_ADDRENV)
+#if defined(CONFIG_ARCH_ADDRENV)
   /* Check for a context switch.  If a context switch occurred, then
    * CURRENT_REGS will have a different value than it did on entry.
    */
 
   if (regs != CURRENT_REGS)
     {
-#if XCHAL_CP_NUM > 0
-      /* If an interrupt level context switch has occurred, then save the
-       * co-processor state in in the suspended thread's co-processor save
-       * area.
-       *
-       * NOTE 1. The state of the co-processor has not been altered and
-       *         still represents the to-be-suspended thread.
-       * NOTE 2. We saved a reference  TCB of the original thread on entry.
-       */
-
-      xtensa_coproc_savestate(&tcb->xcp.cpstate);
-
-      /* Then set up the co-processor state for the to-be-started thread.
-       *
-       * NOTE: The current thread for this CPU is the to-be-started
-       * thread.
-       */
-
-      tcb = this_task();
-      xtensa_coproc_restorestate(&tcb->xcp.cpstate);
-#endif
-
 #ifdef CONFIG_ARCH_ADDRENV
       /* Make sure that the address environment for the previously
        * running task is closed down gracefully (data caches dump,

arch/xtensa/src/common/xtensa_swint.c

@@ -51,13 +51,6 @@ int xtensa_swint(int irq, void *context, void *arg)
 {
   uint32_t *regs = (uint32_t *)context;
   uint32_t cmd;
-#if XCHAL_CP_NUM > 0
-  uintptr_t cpstate;
-  uint32_t cpstate_off;
-
-  cpstate_off = offsetof(struct xcptcontext, cpstate) -
-                offsetof(struct xcptcontext, regs);
-#endif
 
   DEBUGASSERT(regs && regs == CURRENT_REGS);
   cmd = regs[REG_A2];
@@ -104,10 +97,6 @@ int xtensa_swint(int irq, void *context, void *arg)
         {
           DEBUGASSERT(regs[REG_A3] != 0);
           memcpy(*(uint32_t **)regs[REG_A3], regs, XCPTCONTEXT_SIZE);
-#if XCHAL_CP_NUM > 0
-          cpstate = (uintptr_t)regs[REG_A3] + cpstate_off;
-          xtensa_coproc_savestate((struct xtensa_cpstate_s *)cpstate);
-#endif
         }
 
         break;
@@ -133,10 +122,6 @@ int xtensa_swint(int irq, void *context, void *arg)
         {
           DEBUGASSERT(regs[REG_A3] != 0);
           CURRENT_REGS = *(uint32_t **)regs[REG_A3];
-#if XCHAL_CP_NUM > 0
-          cpstate = (uintptr_t)regs[REG_A3] + cpstate_off;
-          xtensa_coproc_restorestate((struct xtensa_cpstate_s *)cpstate);
-#endif
         }
 
         break;