xtensa: move fpu register to XCPTCONTEXT_REGS
1 move fpu register to XCP_REGS 2 move save & restore fpu register to context_save/restore Consistency with other archs. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit is contained in:
zhuyanlin
Abdelatif Guettouche
parent
323d8d9547
commit
1dc39689ff
@ -118,12 +118,25 @@
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/* Storage for overlay state */
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# error Overlays not supported
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# define XCPTCONTEXT_REGS _REG_OVLY_START
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# define _REG_CP_START _REG_OVLY_START
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#else
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# define XCPTCONTEXT_REGS _REG_OVLY_START
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# define _REG_CP_START _REG_OVLY_START
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#endif
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#if XCHAL_CP_NUM > 0
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# if (XCHAL_TOTAL_SA_ALIGN == 8) && ((_REG_CP_START & 1) == 1)
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/* Fpu first address must align to cp align size. */
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# define REG_CP_DUMMY (_REG_CP_START + 0)
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# define XCPTCONTEXT_REGS (_REG_CP_START + 1)
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# else
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# define XCPTCONTEXT_REGS _REG_CP_START
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# endif
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# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + XTENSA_CP_SA_SIZE + 0x20)
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#else
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# define XCPTCONTEXT_REGS _REG_CP_START
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# define XCPTCONTEXT_SIZE ((4 * XCPTCONTEXT_REGS) + 0x20)
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#endif
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/****************************************************************************
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* Public Types
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@ -155,12 +168,6 @@ struct xcptcontext
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uint32_t *regs;
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#if XCHAL_CP_NUM > 0
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/* Co-processor save area */
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struct xtensa_cpstate_s cpstate;
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#endif
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#ifdef CONFIG_LIB_SYSCALL
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/* The following array holds the return address and the exc_return value
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* needed to return from each nested system call.
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@ -285,11 +285,6 @@ int xtensa_intercpu_interrupt(int tocpu, int intcode);
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void xtensa_pause_handler(void);
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#endif
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#if XCHAL_CP_NUM > 0
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void xtensa_coproc_savestate(struct xtensa_cpstate_s *cpstate);
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void xtensa_coproc_restorestate(struct xtensa_cpstate_s *cpstate);
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#endif
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/* Signals */
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void _xtensa_sig_trampoline(void);
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@ -200,6 +200,15 @@ _xtensa_context_save:
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#endif
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#if XCHAL_CP_NUM > 0
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s32i a0, sp, (4 * REG_TMP0) /* Save return address */
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mov a2, sp
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call0 _xtensa_coproc_savestate
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l32i a0, sp, (4 * REG_TMP0) /* Restore return address */
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#endif
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ret
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.size _xtensa_context_save, . - _xtensa_context_save
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@ -239,6 +248,14 @@ _xtensa_context_save:
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_xtensa_context_restore:
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#if XCHAL_CP_NUM > 0
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s32i a0, a2, (4 * REG_TMP0) /* Save return address */
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call0 _xtensa_coproc_restorestate
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l32i a0, a2, (4 * REG_TMP0) /* Restore return address */
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#endif
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#if XCHAL_HAVE_LOOPS != 0
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l32i a3, a2, (4 * REG_LBEG)
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l32i a4, a2, (4 * REG_LEND)
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@ -39,6 +39,7 @@
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/xtensa/core.h>
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#include <arch/xtensa/xtensa_abi.h>
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#include <arch/xtensa/xtensa_coproc.h>
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@ -88,9 +89,7 @@ _xtensa_coproc_saoffsets:
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* around the assembly language call to _xtensa_coproc_savestate.
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*
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* Entry Conditions:
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* - A2 holds the address of the co-processor state save area
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* - The thread being switched out is still the current thread.
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* - CPENABLE state reflects which coprocessors are active.
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* - A2 holds the address of current interrupt stack pointer.
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* - Registers have been saved/spilled already.
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*
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* Exit conditions:
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@ -112,21 +111,31 @@ _xtensa_coproc_savestate:
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/* Move the address of the thread state save area to R15 */
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mov a15, a2 /* A15 is now the address of the save area */
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mov a3, a2 /* A3 is now the address of the save area */
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/* The stack when interrupt happened (the register a2)
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* ----------------------------------------------------
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* | Reserve area (0x20) |
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* ----------------------------------------------------
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* | Coproc context |
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* ----------------------------------------------------
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* | Xtensa common regs |
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* ---------------------------------------------------| <- SP
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*/
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addi a3, a3, (4 * XCPTCONTEXT_REGS)
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/* CPENABLE should show which CPs are enabled. */
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rsr a2, CPENABLE /* a2 = which CPs are enabled */
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beqz a2, .Ldone1 /* Quick exit if none */
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s16i a2, a15, XTENSA_CPSTORED /* Save mask of CPs being stored */
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movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */
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addi a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */
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#if XCHAL_CP0_SA_SIZE > 0
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bbci.l a2, 0, 2f /* CP 0 not enabled */
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l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
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add a3, a14, a15 /* a3 = save area for CP 0 */
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add a3, a14, a3 /* a3 = save area for CP 0 */
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xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -134,7 +143,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP1_SA_SIZE > 0
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bbci.l a2, 1, 2f /* CP 1 not enabled */
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l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */
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add a3, a14, a15 /* a3 = save area for CP 1 */
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add a3, a14, a3 /* a3 = save area for CP 1 */
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xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -142,7 +151,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP2_SA_SIZE > 0
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bbci.l a2, 2, 2f
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l32i a14, a13, 8
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -150,7 +159,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP3_SA_SIZE > 0
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bbci.l a2, 3, 2f
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l32i a14, a13, 12
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -158,7 +167,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP4_SA_SIZE > 0
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bbci.l a2, 4, 2f
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l32i a14, a13, 16
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -166,7 +175,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP5_SA_SIZE > 0
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bbci.l a2, 5, 2f
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l32i a14, a13, 20
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -174,7 +183,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP6_SA_SIZE > 0
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bbci.l a2, 6, 2f
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l32i a14, a13, 24
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -182,7 +191,7 @@ _xtensa_coproc_savestate:
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#if XCHAL_CP7_SA_SIZE > 0
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bbci.l a2, 7, 2f
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l32i a14, a13, 28
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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@ -192,83 +201,6 @@ _xtensa_coproc_savestate:
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.size _xtensa_coproc_savestate, . - _xtensa_coproc_savestate
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/****************************************************************************
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* Name: xtensa_coproc_savestate
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*
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* Description:
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* If there is a current thread and it has a coprocessor state save area,
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* then save all callee-saved state into this area. xtensa_coproc_savestate()
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* is simply a C wrapper around the assembly language call to
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* _xtensa_coproc_savestate.
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*
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* Input Parameters:
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* A2 - Address of co-processor save area
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* Called with interrupts disabled.
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*
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****************************************************************************/
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.global xtensa_coproc_savestate
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.type xtensa_coproc_savestate, @function
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.align 4
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.literal_position
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.align 4
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xtensa_coproc_savestate:
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#ifdef __XTENSA_CALL0_ABI__
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/* Need to preserve a8-11. _xtensa_coproc_savestate modifies a2-a7,
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* a13-a15. a12-a15 are callee saved registers so a13-a14 must be
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* preserved.
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*/
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ENTRY(16)
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s32i a13, sp, LOCAL_OFFSET(1) /* Save clobbered registers */
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s32i a14, sp, LOCAL_OFFSET(2)
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s32i a15, sp, LOCAL_OFFSET(3)
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/* Call _xtensa_coproc_savestate() with A2=address of co-processor
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* save area.
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*/
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call0 _xtensa_coproc_savestate
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/* Restore a13-15 and return */
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l32i a13, sp, LOCAL_OFFSET(1) /* Restore clobbered registers */
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l32i a14, sp, LOCAL_OFFSET(2)
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l32i a15, sp, LOCAL_OFFSET(3)
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RET(16)
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#else
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/* Allocate the stack frame. This function needs to allocate the usual 16
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* byte for the base save area + space for one variable.
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* NOTE: entry works in multiples of 8 bytes.
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*/
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ENTRY(24)
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s32i a0, sp, LOCAL_OFFSET(0) /* Save return address */
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/* Call _xtensa_coproc_savestate() with A2=address of co-processor
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* save area.
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*/
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call0 _xtensa_coproc_savestate
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/* Restore a0 and return */
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l32i a0, sp, LOCAL_OFFSET(0) /* Recover return address */
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RET(24)
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#endif
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.size xtensa_coproc_savestate, . - xtensa_coproc_savestate
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/****************************************************************************
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* Name: _xtensa_coproc_restorestate
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*
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@ -284,12 +216,10 @@ xtensa_coproc_savestate:
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* around the assembly language call to _xtensa_coproc_restorestate.
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*
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* Entry Conditions:
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* - A2 holds the address of the co-processor state save area
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* - The incoming thread is set as the current thread.
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* - A2 holds the address of the current interrupt stack pointer.
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*
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* Exit conditions:
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* - All necessary CP callee-saved state has been restored.
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* - CPENABLE - Set up correctly for the current thread.
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* - Registers a2-a7, a13-a15 have been trashed.
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*
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* Must be called from assembly code only, using CALL0.
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@ -307,81 +237,85 @@ _xtensa_coproc_restorestate:
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/* Move the address of the thread state save area to R15 */
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mov a15, a2 /* A15 is now the address of the save area */
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mov a3, a2 /* A3 is now the address of the save area */
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#ifdef CONFIG_XTENSA_CP_LAZY
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movi a2, 0 /* a2 = Will disable all coprocessors */
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#else
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l16ui a2, a15, XTENSA_CPENABLE /* a2 = Which CPs have been enable for this thread? */
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#endif
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wsr a2, CPENABLE /* Set CPENABLE correctly for this thread */
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l16ui a2, a15, XTENSA_CPSTORED /* a2 = Which CPs have been saved for this thread? */
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movi a3, 0 /* Clear the ones being restored (all of them) */
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s16i a3, a15, XTENSA_CPSTORED /* Clear saved CP mask */
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/* The stack when interrupt happened (the register A2)
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* ----------------------------------------------------
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* | Reserve area (0x20) |
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* ----------------------------------------------------
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* | Coproc context |
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* ----------------------------------------------------
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* | Xtensa common regs |
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* ---------------------------------------------------| <- SP
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*/
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addi a3, a3, (4 * XCPTCONTEXT_REGS)
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rsr a8, CPENABLE /* Set CPENABLE correctly for this thread */
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beqz a8, .Ldone1 /* Quick exit if none */
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movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */
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addi a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */
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#if XCHAL_CP0_SA_SIZE
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bbci.l a2, 0, 2f /* CP 0 not enabled */
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bbci.l a8, 0, 2f /* CP 0 not enabled */
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l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
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add a3, a14, a15 /* a3 = save area for CP 0 */
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add a3, a14, a3 /* a3 = save area for CP 0 */
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xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP1_SA_SIZE
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bbci.l a2, 1, 2f /* CP 1 not enabled */
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bbci.l a8, 1, 2f /* CP 1 not enabled */
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l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */
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add a3, a14, a15 /* a3 = save area for CP 1 */
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add a3, a14, a3 /* a3 = save area for CP 1 */
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xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP2_SA_SIZE
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bbci.l a2, 2, 2f
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bbci.l a8, 2, 2f
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l32i a14, a13, 8
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP3_SA_SIZE
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bbci.l a2, 3, 2f
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bbci.l a8, 3, 2f
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l32i a14, a13, 12
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP4_SA_SIZE
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bbci.l a2, 4, 2f
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bbci.l a8, 4, 2f
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l32i a14, a13, 16
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP5_SA_SIZE
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bbci.l a2, 5, 2f
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bbci.l a8, 5, 2f
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l32i a14, a13, 20
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add a3, a14, a15
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add a3, a14, a3
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xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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#endif
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#if XCHAL_CP6_SA_SIZE
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bbci.l a2, 6, 2f
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bbci.l a8, 6, 2f
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l32i a14, a13, 24
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add a3, a14, a15
|
||||
add a3, a14, a3
|
||||
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP7_SA_SIZE
|
||||
bbci.l a2, 7, 2f
|
||||
bbci.l a8, 7, 2f
|
||||
l32i a14, a13, 28
|
||||
add a3, a14, a15
|
||||
add a3, a14, a3
|
||||
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
|
||||
2:
|
||||
#endif
|
||||
@ -392,80 +326,4 @@ _xtensa_coproc_restorestate:
|
||||
|
||||
.size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate
|
||||
|
||||
/****************************************************************************
|
||||
* Name: xtensa_coproc_restorestate
|
||||
*
|
||||
* Description:
|
||||
* Restore any callee-saved coprocessor state for the incoming thread.
|
||||
* xtensa_coproc_restorestate() is simply a C wrapper around the assembly
|
||||
* language call to _xtensa_coproc_restorestate.
|
||||
*
|
||||
* Input Parameters:
|
||||
* - A2 holds the address of the threads state save area
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* Called with interrupts disabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.global xtensa_coproc_restorestate
|
||||
.type xtensa_coproc_restorestate, @function
|
||||
|
||||
.align 4
|
||||
.literal_position
|
||||
.align 4
|
||||
|
||||
xtensa_coproc_restorestate:
|
||||
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
/* Need to preserve a8-11. _xtensa_coproc_restorestate modifies a2-a7,
|
||||
* a13-a15. a12-a15 are callee saved registers so a13-a14 must be
|
||||
* preserved.
|
||||
*/
|
||||
|
||||
ENTRY(16)
|
||||
s32i a13, sp, LOCAL_OFFSET(1) /* Save clobbered values */
|
||||
s32i a14, sp, LOCAL_OFFSET(2)
|
||||
s32i a15, sp, LOCAL_OFFSET(3)
|
||||
|
||||
/* Call _xtensa_coproc_restorestate() with A2=address of co-processor
|
||||
* save area. Registers a0, a2-a7, a13-a15 have been trashed.
|
||||
*/
|
||||
|
||||
call0 _xtensa_coproc_restorestate
|
||||
|
||||
/* Restore a13-a15 and return */
|
||||
|
||||
l32i a13, sp, LOCAL_OFFSET(1) /* Restore clobbered registers */
|
||||
l32i a14, sp, LOCAL_OFFSET(2)
|
||||
l32i a15, sp, LOCAL_OFFSET(3)
|
||||
RET(16)
|
||||
|
||||
#else
|
||||
/* Allocate the stack frame. This function needs to allocate the usual 16
|
||||
* byte for the base save area + space for one variable.
|
||||
* NOTE: entry works in multiples of 8 bytes.
|
||||
*/
|
||||
|
||||
ENTRY(24)
|
||||
s32i a0, sp, LOCAL_OFFSET(0) /* Save return address */
|
||||
|
||||
/* Call _xtensa_coproc_restorestate() with A2=address of co-processor
|
||||
* save area. Registers a0, a2-a7, a13-a15 have been trashed.
|
||||
*/
|
||||
|
||||
call0 _xtensa_coproc_restorestate
|
||||
|
||||
/* Restore a0 and return */
|
||||
|
||||
l32i a0, sp, LOCAL_OFFSET(0) /* Recover return address */
|
||||
RET(24)
|
||||
|
||||
#endif
|
||||
|
||||
.size xtensa_coproc_restorestate, . - xtensa_coproc_restorestate
|
||||
|
||||
#endif /* XCHAL_CP_NUM > 0 */
|
||||
|
||||
@ -116,12 +116,6 @@ void up_exit(int status)
|
||||
|
||||
sinfo("TCB=%p exiting\n", tcb);
|
||||
|
||||
#if XCHAL_CP_NUM > 0
|
||||
/* Disable co-processor support for the task that is exit-ing. */
|
||||
|
||||
xtensa_coproc_disable(&tcb->xcp.cpstate, XTENSA_CP_ALLSET);
|
||||
#endif
|
||||
|
||||
/* Destroy the task at the head of the ready to run list. */
|
||||
|
||||
nxtask_exit();
|
||||
|
||||
@ -84,6 +84,10 @@ static inline void xtensa_color_intstack(void)
|
||||
|
||||
void up_initialize(void)
|
||||
{
|
||||
#if XCHAL_CP_NUM > 0
|
||||
xtensa_set_cpenable(CONFIG_XTENSA_CP_INITSET);
|
||||
#endif
|
||||
|
||||
xtensa_color_intstack();
|
||||
|
||||
/* Add any extra memory fragments to the memory manager */
|
||||
|
||||
@ -108,18 +108,4 @@ void up_initial_state(struct tcb_s *tcb)
|
||||
|
||||
xcp->regs[REG_PS] = PS_UM | PS_WOE | PS_CALLINC(1);
|
||||
#endif
|
||||
|
||||
#if XCHAL_CP_NUM > 0
|
||||
/* Set up the co-processors that will be enabled initially when the thread
|
||||
* starts (see xtensa_coproc.h). If the lazy co-processor state restore
|
||||
* logic is selected, that would be the empty set.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_XTENSA_CP_LAZY
|
||||
xcp->cpstate.cpenable = 0; /* No co-processors are enabled */
|
||||
#else
|
||||
xcp->cpstate.cpenable = (CONFIG_XTENSA_CP_INITSET & XTENSA_CP_ALLSET);
|
||||
#endif
|
||||
xcp->cpstate.cpstored = 0; /* No co-processors haved state saved */
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -49,11 +49,6 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs)
|
||||
PANIC();
|
||||
|
||||
#else
|
||||
#if XCHAL_CP_NUM > 0
|
||||
/* Save the TCB of in case we need to save co-processor state */
|
||||
|
||||
struct tcb_s *tcb = this_task();
|
||||
#endif
|
||||
|
||||
board_autoled_on(LED_INIRQ);
|
||||
|
||||
@ -76,35 +71,13 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs)
|
||||
|
||||
irq_dispatch(irq, regs);
|
||||
|
||||
#if XCHAL_CP_NUM > 0 || defined(CONFIG_ARCH_ADDRENV)
|
||||
#if defined(CONFIG_ARCH_ADDRENV)
|
||||
/* Check for a context switch. If a context switch occurred, then
|
||||
* CURRENT_REGS will have a different value than it did on entry.
|
||||
*/
|
||||
|
||||
if (regs != CURRENT_REGS)
|
||||
{
|
||||
#if XCHAL_CP_NUM > 0
|
||||
/* If an interrupt level context switch has occurred, then save the
|
||||
* co-processor state in in the suspended thread's co-processor save
|
||||
* area.
|
||||
*
|
||||
* NOTE 1. The state of the co-processor has not been altered and
|
||||
* still represents the to-be-suspended thread.
|
||||
* NOTE 2. We saved a reference TCB of the original thread on entry.
|
||||
*/
|
||||
|
||||
xtensa_coproc_savestate(&tcb->xcp.cpstate);
|
||||
|
||||
/* Then set up the co-processor state for the to-be-started thread.
|
||||
*
|
||||
* NOTE: The current thread for this CPU is the to-be-started
|
||||
* thread.
|
||||
*/
|
||||
|
||||
tcb = this_task();
|
||||
xtensa_coproc_restorestate(&tcb->xcp.cpstate);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_ADDRENV
|
||||
/* Make sure that the address environment for the previously
|
||||
* running task is closed down gracefully (data caches dump,
|
||||
|
||||
@ -51,13 +51,6 @@ int xtensa_swint(int irq, void *context, void *arg)
|
||||
{
|
||||
uint32_t *regs = (uint32_t *)context;
|
||||
uint32_t cmd;
|
||||
#if XCHAL_CP_NUM > 0
|
||||
uintptr_t cpstate;
|
||||
uint32_t cpstate_off;
|
||||
|
||||
cpstate_off = offsetof(struct xcptcontext, cpstate) -
|
||||
offsetof(struct xcptcontext, regs);
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(regs && regs == CURRENT_REGS);
|
||||
cmd = regs[REG_A2];
|
||||
@ -104,10 +97,6 @@ int xtensa_swint(int irq, void *context, void *arg)
|
||||
{
|
||||
DEBUGASSERT(regs[REG_A3] != 0);
|
||||
memcpy(*(uint32_t **)regs[REG_A3], regs, XCPTCONTEXT_SIZE);
|
||||
#if XCHAL_CP_NUM > 0
|
||||
cpstate = (uintptr_t)regs[REG_A3] + cpstate_off;
|
||||
xtensa_coproc_savestate((struct xtensa_cpstate_s *)cpstate);
|
||||
#endif
|
||||
}
|
||||
|
||||
break;
|
||||
@ -133,10 +122,6 @@ int xtensa_swint(int irq, void *context, void *arg)
|
||||
{
|
||||
DEBUGASSERT(regs[REG_A3] != 0);
|
||||
CURRENT_REGS = *(uint32_t **)regs[REG_A3];
|
||||
#if XCHAL_CP_NUM > 0
|
||||
cpstate = (uintptr_t)regs[REG_A3] + cpstate_off;
|
||||
xtensa_coproc_restorestate((struct xtensa_cpstate_s *)cpstate);
|
||||
#endif
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user