Tiva: Add framework to support the uniqueu TM4C Ethernet register definitions
This commit is contained in:
Gregory Nutt
parent
a0727124c2
commit
1dc66f3104
203
arch/arm/src/tiva/chip/lm3s_ethernet.h
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203
arch/arm/src/tiva/chip/lm3s_ethernet.h
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/************************************************************************************
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* arch/arm/src/tiva/chip/lm3s_ethernet.h
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*
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* Copyright (C) 2009-2010, 2012-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_CHIP_LM3S_ETHERNET_H
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#define __ARCH_ARM_SRC_TIVA_CHIP_LM3S_ETHERNET_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/net/mii.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Ethernet Controller Register Offsets *********************************************/
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/* Ethernet MAC Register Offsets */
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#define TIVA_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
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#define TIVA_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
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#define TIVA_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
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#define TIVA_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
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#define TIVA_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
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#define TIVA_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
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#define TIVA_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
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#define TIVA_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
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#define TIVA_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
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#define TIVA_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
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#define TIVA_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
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#define TIVA_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
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#define TIVA_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
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#define TIVA_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
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#define TIVA_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
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#ifdef TIVA_ETHTS
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# define TIVA_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
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#endif
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/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
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/* Ethernet Controller Register Addresses *******************************************/
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#define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET)
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#define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET)
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#define TIVA_MAC_IM (TIVA_ETHCON_BASE + TIVA_MAC_IM_OFFSET)
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#define TIVA_MAC_RCTL (TIVA_ETHCON_BASE + TIVA_MAC_RCTL_OFFSET)
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#define TIVA_MAC_TCTL (TIVA_ETHCON_BASE + TIVA_MAC_TCTL_OFFSET)
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#define TIVA_MAC_DATA (TIVA_ETHCON_BASE + TIVA_MAC_DATA_OFFSET)
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#define TIVA_MAC_IA0 (TIVA_ETHCON_BASE + TIVA_MAC_IA0_OFFSET)
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#define TIVA_MAC_IA1 (TIVA_ETHCON_BASE + TIVA_MAC_IA1_OFFSET)
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#define TIVA_MAC_THR (TIVA_ETHCON_BASE + TIVA_MAC_THR_OFFSET)
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#define TIVA_MAC_MCTL (TIVA_ETHCON_BASE + TIVA_MAC_MCTL_OFFSET)
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#define TIVA_MAC_MDV (TIVA_ETHCON_BASE + TIVA_MAC_MDV_OFFSET)
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#define TIVA_MAC_MTXD (TIVA_ETHCON_BASE + TIVA_MAC_MTXD_OFFSET)
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#define TIVA_MAC_MRXD (TIVA_ETHCON_BASE + TIVA_MAC_MRXD_OFFSET)
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#define TIVA_MAC_NP (TIVA_ETHCON_BASE + TIVA_MAC_NP_OFFSET)
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#define TIVA_MAC_TR (TIVA_ETHCON_BASE + TIVA_MAC_TR_OFFSET)
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#ifdef TIVA_ETHTS
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# define TIVA_MAC_TS (TIVA_ETHCON_BASE + TIVA_MAC_TS_OFFSET)
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#endif
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/* Memory Mapped MII Management Registers */
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#define MAC_MII_MCR (TIVA_ETHCON_BASE + MII_MCR)
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#define MAC_MII_MSR (TIVA_ETHCON_BASE + MII_MSR)
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#define MAC_MII_PHYID1 (TIVA_ETHCON_BASE + MII_PHYID1)
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#define MAC_MII_PHYID2 (TIVA_ETHCON_BASE + MII_PHYID2)
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#define MAC_MII_ADVERTISE (TIVA_ETHCON_BASE + MII_ADVERTISE)
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#define MAC_MII_LPA (TIVA_ETHCON_BASE + MII_LPA)
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#define MAC_MII_EXPANSION (TIVA_ETHCON_BASE + MII_EXPANSION)
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#define MAC_MII_VSPECIFIC (TIVA_ETHCON_BASE + MII_TIVA_VSPECIFIC)
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#define MAC_MII_INTCS (TIVA_ETHCON_BASE + MII_TIVA_INTCS)
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#define MAC_MII_DIAGNOSTIC (TIVA_ETHCON_BASE + MII_TIVA_DIAGNOSTIC)
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#define MAC_MII_XCVRCONTROL (TIVA_ETHCON_BASE + MII_TIVA_XCVRCONTROL)
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#define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG)
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#define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL)
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/* Ethernet Controller Register Bit Definitions *************************************/
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/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
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#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */
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#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */
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#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */
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#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */
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#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */
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#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */
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#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */
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#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */
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#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */
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#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */
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#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */
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#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */
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#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */
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#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */
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/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
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#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */
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#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */
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#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */
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#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */
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#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */
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#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */
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#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */
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#define MAC_IM_ALLINTS 0x7f
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/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
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#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */
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#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */
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#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */
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#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */
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#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */
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/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
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#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */
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#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */
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#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */
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#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */
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/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
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#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */
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/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
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#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */
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#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */
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#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */
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#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT)
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/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
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#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */
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/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
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#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */
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/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
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#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */
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/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
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#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */
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/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
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#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_TIVA_CHIP_LM3S_ETHERNET_H */
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@ -41,163 +41,13 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/net/mii.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Ethernet Controller Register Offsets *********************************************/
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/* Ethernet MAC Register Offsets */
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#define TIVA_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
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#define TIVA_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
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#define TIVA_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
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#define TIVA_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
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#define TIVA_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
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#define TIVA_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
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#define TIVA_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
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#define TIVA_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
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#define TIVA_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
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#define TIVA_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
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#define TIVA_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
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#define TIVA_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
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#define TIVA_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
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#define TIVA_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
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#define TIVA_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
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#ifdef TIVA_ETHTS
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# define TIVA_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# include "chip/tm4c_ethernet.h"
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#elif defined(CONFIG_ARCH_CHIP_LM3S)
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# include "chip/lm3s_ethernet.h"
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#else
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# error Ethernet register definitions unknown for this chip
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#endif
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/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
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/* Ethernet Controller Register Addresses *******************************************/
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#define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET)
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#define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET)
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#define TIVA_MAC_IM (TIVA_ETHCON_BASE + TIVA_MAC_IM_OFFSET)
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#define TIVA_MAC_RCTL (TIVA_ETHCON_BASE + TIVA_MAC_RCTL_OFFSET)
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#define TIVA_MAC_TCTL (TIVA_ETHCON_BASE + TIVA_MAC_TCTL_OFFSET)
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#define TIVA_MAC_DATA (TIVA_ETHCON_BASE + TIVA_MAC_DATA_OFFSET)
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#define TIVA_MAC_IA0 (TIVA_ETHCON_BASE + TIVA_MAC_IA0_OFFSET)
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#define TIVA_MAC_IA1 (TIVA_ETHCON_BASE + TIVA_MAC_IA1_OFFSET)
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#define TIVA_MAC_THR (TIVA_ETHCON_BASE + TIVA_MAC_THR_OFFSET)
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#define TIVA_MAC_MCTL (TIVA_ETHCON_BASE + TIVA_MAC_MCTL_OFFSET)
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#define TIVA_MAC_MDV (TIVA_ETHCON_BASE + TIVA_MAC_MDV_OFFSET)
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#define TIVA_MAC_MTXD (TIVA_ETHCON_BASE + TIVA_MAC_MTXD_OFFSET)
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#define TIVA_MAC_MRXD (TIVA_ETHCON_BASE + TIVA_MAC_MRXD_OFFSET)
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#define TIVA_MAC_NP (TIVA_ETHCON_BASE + TIVA_MAC_NP_OFFSET)
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#define TIVA_MAC_TR (TIVA_ETHCON_BASE + TIVA_MAC_TR_OFFSET)
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#ifdef TIVA_ETHTS
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# define TIVA_MAC_TS (TIVA_ETHCON_BASE + TIVA_MAC_TS_OFFSET)
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#endif
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/* Memory Mapped MII Management Registers */
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#define MAC_MII_MCR (TIVA_ETHCON_BASE + MII_MCR)
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#define MAC_MII_MSR (TIVA_ETHCON_BASE + MII_MSR)
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#define MAC_MII_PHYID1 (TIVA_ETHCON_BASE + MII_PHYID1)
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#define MAC_MII_PHYID2 (TIVA_ETHCON_BASE + MII_PHYID2)
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#define MAC_MII_ADVERTISE (TIVA_ETHCON_BASE + MII_ADVERTISE)
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#define MAC_MII_LPA (TIVA_ETHCON_BASE + MII_LPA)
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#define MAC_MII_EXPANSION (TIVA_ETHCON_BASE + MII_EXPANSION)
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#define MAC_MII_VSPECIFIC (TIVA_ETHCON_BASE + MII_TIVA_VSPECIFIC)
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#define MAC_MII_INTCS (TIVA_ETHCON_BASE + MII_TIVA_INTCS)
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#define MAC_MII_DIAGNOSTIC (TIVA_ETHCON_BASE + MII_TIVA_DIAGNOSTIC)
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#define MAC_MII_XCVRCONTROL (TIVA_ETHCON_BASE + MII_TIVA_XCVRCONTROL)
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#define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG)
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#define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL)
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/* Ethernet Controller Register Bit Definitions *************************************/
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/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
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#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */
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#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */
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#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */
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#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */
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#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */
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#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */
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#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */
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#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */
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#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */
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#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */
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#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */
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#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */
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#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */
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#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */
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/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */
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#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */
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#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */
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#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */
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#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */
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#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */
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#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */
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#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */
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#define MAC_IM_ALLINTS 0x7f
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/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */
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#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */
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#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */
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#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */
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#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */
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#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */
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/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */
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#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */
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#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */
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#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */
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#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */
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/* Ethernet MAC Threshold (MACTHR), offset 0x01c */
|
||||
|
||||
#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */
|
||||
|
||||
/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */
|
||||
|
||||
#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */
|
||||
#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */
|
||||
#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */
|
||||
#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT)
|
||||
|
||||
/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */
|
||||
|
||||
#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */
|
||||
|
||||
/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */
|
||||
|
||||
#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */
|
||||
|
||||
/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */
|
||||
|
||||
#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */
|
||||
|
||||
/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */
|
||||
|
||||
#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */
|
||||
|
||||
/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */
|
||||
|
||||
#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_ETHERNET_H */
|
||||
|
||||
76
arch/arm/src/tiva/chip/tm4c_ethernet.h
Normal file
76
arch/arm/src/tiva/chip/tm4c_ethernet.h
Normal file
@ -0,0 +1,76 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/tiva/chip/tm4c_ethernet.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TM4C_ETHERNET_H
|
||||
#define __ARCH_ARM_SRC_TIVA_CHIP_TM4C_ETHERNET_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Ethernet Controller Register Offsets *********************************************/
|
||||
|
||||
/* Ethernet MAC Register Offsets */
|
||||
|
||||
|
||||
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
|
||||
|
||||
/* Ethernet Controller Register Addresses *******************************************/
|
||||
|
||||
/* Memory Mapped MII Management Registers */
|
||||
|
||||
/* Ethernet Controller Register Bit Definitions *************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TM4C_ETHERNET_H */
|
||||
Loading…
Reference in New Issue
Block a user