TMS570: Add peripheral initialization logic
This commit is contained in:
Gregory Nutt
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3a6aa75d15
commit
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381
arch/arm/src/tms570/chip/tms570_pcr.h
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arch/arm/src/tms570/chip/tms570_pcr.h
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/****************************************************************************************************
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* arch/arm/src/tms570/chip/tms570_pcr.h
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* Peripheral Control Register (PCR) Definitions
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
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* Instruments, Literature Number: SPNU517A, September 2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
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#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/tms570_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define TMS570_PCR_PMPROTSET0_OFFSET 0x0000 /* Peripheral Memory Protection Set Register 0 */
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#define TMS570_PCR_PMPROTSET1_OFFSET 0x0004 /* Peripheral Memory Protection Set Register 1 */
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#define TMS570_PCR_PMPROTCLR0_OFFSET 0x0010 /* Peripheral Memory Protection Clear Register 0 */
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#define TMS570_PCR_PMPROTCLR1_OFFSET 0x0014 /* Peripheral Memory Protection Clear Register 1 */
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#define TMS570_PCR_PPROTSET0_OFFSET 0x0020 /* Peripheral Protection Set Register 0 */
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#define TMS570_PCR_PPROTSET1_OFFSET 0x0024 /* Peripheral Protection Set Register 1 */
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#define TMS570_PCR_PPROTSET2_OFFSET 0x0028 /* Peripheral Protection Set Register 2 */
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#define TMS570_PCR_PPROTSET3_OFFSET 0x002c /* Peripheral Protection Set Register 3 */
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#define TMS570_PCR_PPROTCLR0_OFFSET 0x0040 /* Peripheral Protection Clear Register 0 */
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#define TMS570_PCR_PPROTCLR1_OFFSET 0x0044 /* Peripheral Protection Clear Register 1 */
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#define TMS570_PCR_PPROTCLR2_OFFSET 0x0048 /* Peripheral Protection Clear Register 2 */
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#define TMS570_PCR_PPROTCLR3_OFFSET 0x004c /* Peripheral Protection Clear Register 3 */
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#define TMS570_PCR_PCSPWRDWNSET0_OFFSET 0x0060 /* Peripheral Memory Power-Down Set Register 0 */
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#define TMS570_PCR_PCSPWRDWNSET1_OFFSET 0x0064 /* Peripheral Memory Power-Down Set Register 1 */
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#define TMS570_PCR_PCSPWRDWNCLR0_OFFSET 0x0070 /* Peripheral Memory Power-Down Clear Register 0 */
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#define TMS570_PCR_PCSPWRDWNCLR1_OFFSET 0x0074 /* Peripheral Memory Power-Down Clear Register 1 */
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#define TMS570_PCR_PSPWRDWNSET0_OFFSET 0x0080 /* Peripheral Power-Down Set Register 0 */
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#define TMS570_PCR_PSPWRDWNSET1_OFFSET 0x0084 /* Peripheral Power-Down Set Register 1 */
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#define TMS570_PCR_PSPWRDWNSET2_OFFSET 0x0088 /* Peripheral Power-Down Set Register 2 */
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#define TMS570_PCR_PSPWRDWNSET3_OFFSET 0x008c /* Peripheral Power-Down Set Register 3 */
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#define TMS570_PCR_PSPWRDWNCLR0_OFFSET 0x00a0 /* Peripheral Power-Down Clear Register 0 */
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#define TMS570_PCR_PSPWRDWNCLR1_OFFSET 0x00a4 /* Peripheral Power-Down Clear Register 1 */
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#define TMS570_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 /* Peripheral Power-Down Clear Register 2 */
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#define TMS570_PCR_PSPWRDWNCLR3_OFFSET 0x00ac /* Peripheral Power-Down Clear Register 3 */
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/* Register Addresses *******************************************************************************/
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#define TMS570_PCR_PMPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET0_OFFSET)
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#define TMS570_PCR_PMPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET1_OFFSET)
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#define TMS570_PCR_PMPROTCLR0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTCLR0_OFFSET)
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#define TMS570_PCR_PMPROTCLR1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTCLR1_OFFSET)
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#define TMS570_PCR_PPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET0_OFFSET)
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#define TMS570_PCR_PPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET1_OFFSET)
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#define TMS570_PCR_PPROTSET2 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET2_OFFSET)
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#define TMS570_PCR_PPROTSET3 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET3_OFFSET)
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#define TMS570_PCR_PPROTCLR0 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR0_OFFSET)
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#define TMS570_PCR_PPROTCLR1 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR1_OFFSET)
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#define TMS570_PCR_PPROTCLR2 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR2_OFFSET)
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#define TMS570_PCR_PPROTCLR3 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR3_OFFSET)
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#define TMS570_PCR_PCSPWRDWNSET0 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNSET0_OFFSET)
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#define TMS570_PCR_PCSPWRDWNSET1 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNSET1_OFFSET)
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#define TMS570_PCR_PCSPWRDWNCLR0 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNCLR0_OFFSET)
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#define TMS570_PCR_PCSPWRDWNCLR1 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNCLR1_OFFSET)
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#define TMS570_PCR_PSPWRDWNSET0 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET0_OFFSET)
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#define TMS570_PCR_PSPWRDWNSET1 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET1_OFFSET)
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#define TMS570_PCR_PSPWRDWNSET2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET2_OFFSET)
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#define TMS570_PCR_PSPWRDWNSET3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET3_OFFSET)
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#define TMS570_PCR_PSPWRDWNCLR0 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR0_OFFSET)
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#define TMS570_PCR_PSPWRDWNCLR1 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR1_OFFSET)
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#define TMS570_PCR_PSPWRDWNCLR2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR2_OFFSET)
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#define TMS570_PCR_PSPWRDWNCLR3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR3_OFFSET)
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/* Register Bit-Field Definitions *******************************************************************/
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/* Peripheral Memory Protection Set Register 0 */
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#define PCR_PMPROTSET0_
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/* Peripheral Memory Protection Set Register 1 */
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#define PCR_PMPROTSET1_
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/* Peripheral Memory Protection Clear Register 0 */
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#define PCR_PMPROTCLR0_
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/* Peripheral Memory Protection Clear Register 1 */
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#define PCR_PMPROTCLR1_
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/* Peripheral Protection Set Register 0 */
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#define PCR_PPROTSET0_
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/* Peripheral Protection Set Register 1 */
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#define PCR_PPROTSET1_
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/* Peripheral Protection Set Register 2 */
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#define PCR_PPROTSET2_
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/* Peripheral Protection Set Register 3 */
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#define PCR_PPROTSET3_
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/* Peripheral Protection Clear Register 0 */
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#define PCR_PPROTCLR0_
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/* Peripheral Protection Clear Register 1 */
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#define PCR_PPROTCLR1_
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/* Peripheral Protection Clear Register 2 */
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#define PCR_PPROTCLR2_
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/* Peripheral Protection Clear Register 3 */
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#define PCR_PPROTCLR3_
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/* Peripheral Memory Power-Down Set Register 0 */
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#define PCR_PCSPWRDWNSET0_
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/* Peripheral Memory Power-Down Set Register 1 */
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#define PCR_PCSPWRDWNSET1_
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/* Peripheral Memory Power-Down Clear Register 0 */
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#define PCR_PCSPWRDWNCLR0_
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/* Peripheral Memory Power-Down Clear Register 1 */
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#define PCR_PCSPWRDWNCLR1_
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/* Peripheral Power-Down Set Register 0 and Peripheral Power-Down Clear Register 0 */
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#define PCR_PSPWERDWN0_PS0_SHIFT (0) /* Bits 0-3: Quadrants for PS0 */
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#define PCR_PSPWERDWN0_PS0_MASK (15 << PCR_PSPWERDWN0_PS0_SHIFT)
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# define PCR_PSPWERDWN0_PS0_Q1 (1 << PCR_PSPWERDWN0_PS0_SHIFT)
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# define PCR_PSPWERDWN0_PS0_Q2 (2 << PCR_PSPWERDWN0_PS0_SHIFT)
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# define PCR_PSPWERDWN0_PS0_Q3 (4 << PCR_PSPWERDWN0_PS0_SHIFT)
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# define PCR_PSPWERDWN0_PS0_Q4 (8 << PCR_PSPWERDWN0_PS0_SHIFT)
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# define PCR_PSPWERDWN0_PS0_QALL (15 << PCR_PSPWERDWN0_PS0_SHIFT)
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#define PCR_PSPWERDWN0_PS1_SHIFT (4) /* Bits 4-7: Quadrants for PS1 */
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#define PCR_PSPWERDWN0_PS1_MASK (15 << PCR_PSPWERDWN0_PS1_SHIFT)
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# define PCR_PSPWERDWN0_PS1_Q1 (1 << PCR_PSPWERDWN0_PS1_SHIFT)
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# define PCR_PSPWERDWN0_PS1_Q2 (2 << PCR_PSPWERDWN0_PS1_SHIFT)
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# define PCR_PSPWERDWN0_PS1_Q3 (4 << PCR_PSPWERDWN0_PS1_SHIFT)
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# define PCR_PSPWERDWN0_PS1_Q4 (8 << PCR_PSPWERDWN0_PS1_SHIFT)
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# define PCR_PSPWERDWN0_PS1_QALL (15 << PCR_PSPWERDWN0_PS1_SHIFT)
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#define PCR_PSPWERDWN0_PS2_SHIFT (8) /* Bits 8-11: Quadrants for PS2 */
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#define PCR_PSPWERDWN0_PS2_MASK (15 << PCR_PSPWERDWN0_PS2_SHIFT)
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# define PCR_PSPWERDWN0_PS2_Q1 (1 << PCR_PSPWERDWN0_PS2_SHIFT)
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# define PCR_PSPWERDWN0_PS2_Q2 (2 << PCR_PSPWERDWN0_PS2_SHIFT)
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# define PCR_PSPWERDWN0_PS2_Q3 (4 << PCR_PSPWERDWN0_PS2_SHIFT)
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# define PCR_PSPWERDWN0_PS2_Q4 (8 << PCR_PSPWERDWN0_PS2_SHIFT)
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# define PCR_PSPWERDWN0_PS2_QALL (15 << PCR_PSPWERDWN0_PS2_SHIFT)
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#define PCR_PSPWERDWN0_PS3_SHIFT (12) /* Bits 12-15: Quadrants for PS3 */
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#define PCR_PSPWERDWN0_PS3_MASK (15 << PCR_PSPWERDWN0_PS3_SHIFT)
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# define PCR_PSPWERDWN0_PS3_Q1 (1 << PCR_PSPWERDWN0_PS3_SHIFT)
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# define PCR_PSPWERDWN0_PS3_Q2 (2 << PCR_PSPWERDWN0_PS3_SHIFT)
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# define PCR_PSPWERDWN0_PS3_Q3 (4 << PCR_PSPWERDWN0_PS3_SHIFT)
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# define PCR_PSPWERDWN0_PS3_Q4 (8 << PCR_PSPWERDWN0_PS3_SHIFT)
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# define PCR_PSPWERDWN0_PS3_QALL (15 << PCR_PSPWERDWN0_PS3_SHIFT)
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#define PCR_PSPWERDWN0_PS4_SHIFT (16) /* Bits 16-19: Quadrants for PS4 */
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#define PCR_PSPWERDWN0_PS4_MASK (15 << PCR_PSPWERDWN0_PS4_SHIFT)
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# define PCR_PSPWERDWN0_PS4_Q1 (1 << PCR_PSPWERDWN0_PS4_SHIFT)
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# define PCR_PSPWERDWN0_PS4_Q2 (2 << PCR_PSPWERDWN0_PS4_SHIFT)
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# define PCR_PSPWERDWN0_PS4_Q3 (4 << PCR_PSPWERDWN0_PS4_SHIFT)
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# define PCR_PSPWERDWN0_PS4_Q4 (8 << PCR_PSPWERDWN0_PS4_SHIFT)
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# define PCR_PSPWERDWN0_PS4_QALL (15 << PCR_PSPWERDWN0_PS4_SHIFT)
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#define PCR_PSPWERDWN0_PS5_SHIFT (20) /* Bits 20-23: Quadrants for PS5 */
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#define PCR_PSPWERDWN0_PS5_MASK (15 << PCR_PSPWERDWN0_PS5_SHIFT)
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# define PCR_PSPWERDWN0_PS5_Q1 (1 << PCR_PSPWERDWN0_PS5_SHIFT)
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# define PCR_PSPWERDWN0_PS5_Q2 (2 << PCR_PSPWERDWN0_PS5_SHIFT)
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# define PCR_PSPWERDWN0_PS5_Q3 (4 << PCR_PSPWERDWN0_PS5_SHIFT)
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# define PCR_PSPWERDWN0_PS5_Q4 (8 << PCR_PSPWERDWN0_PS5_SHIFT)
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# define PCR_PSPWERDWN0_PS5_QALL (15 << PCR_PSPWERDWN0_PS5_SHIFT)
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#define PCR_PSPWERDWN0_PS6_SHIFT (24) /* Bits 24-27: Quadrants for PS6 */
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#define PCR_PSPWERDWN0_PS6_MASK (15 << PCR_PSPWERDWN0_PS6_SHIFT)
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# define PCR_PSPWERDWN0_PS6_Q1 (1 << PCR_PSPWERDWN0_PS6_SHIFT)
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# define PCR_PSPWERDWN0_PS6_Q2 (2 << PCR_PSPWERDWN0_PS6_SHIFT)
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# define PCR_PSPWERDWN0_PS6_Q3 (4 << PCR_PSPWERDWN0_PS6_SHIFT)
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# define PCR_PSPWERDWN0_PS6_Q4 (8 << PCR_PSPWERDWN0_PS6_SHIFT)
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# define PCR_PSPWERDWN0_PS6_QALL (15 << PCR_PSPWERDWN0_PS6_SHIFT)
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#define PCR_PSPWERDWN0_PS7_SHIFT (28) /* Bits 28-31: Quadrants for PS7 */
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#define PCR_PSPWERDWN0_PS7_MASK (15 << PCR_PSPWERDWN0_PS7_SHIFT)
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# define PCR_PSPWERDWN0_PS7_Q1 (1 << PCR_PSPWERDWN0_PS7_SHIFT)
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# define PCR_PSPWERDWN0_PS7_Q2 (2 << PCR_PSPWERDWN0_PS7_SHIFT)
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# define PCR_PSPWERDWN0_PS7_Q3 (4 << PCR_PSPWERDWN0_PS7_SHIFT)
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# define PCR_PSPWERDWN0_PS7_Q4 (8 << PCR_PSPWERDWN0_PS7_SHIFT)
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# define PCR_PSPWERDWN0_PS7_QALL (15 << PCR_PSPWERDWN0_PS7_SHIFT)
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/* Peripheral Power-Down Set Register 1 and Peripheral Power-Down Clear Register 1 */
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#define PCR_PSPWERDWN1_PS8_SHIFT (0) /* Bits 0-3: Quadrants for PS8 */
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#define PCR_PSPWERDWN1_PS8_MASK (15 << PCR_PSPWERDWN1_PS8_SHIFT)
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# define PCR_PSPWERDWN1_PS8_Q1 (1 << PCR_PSPWERDWN1_PS8_SHIFT)
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# define PCR_PSPWERDWN1_PS8_Q2 (2 << PCR_PSPWERDWN1_PS8_SHIFT)
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# define PCR_PSPWERDWN1_PS8_Q3 (4 << PCR_PSPWERDWN1_PS8_SHIFT)
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# define PCR_PSPWERDWN1_PS8_Q4 (8 << PCR_PSPWERDWN1_PS8_SHIFT)
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# define PCR_PSPWERDWN1_PS8_QALL (15 << PCR_PSPWERDWN1_PS8_SHIFT)
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#define PCR_PSPWERDWN1_PS9_SHIFT (4) /* Bits 4-7: Quadrants for PS9 */
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#define PCR_PSPWERDWN1_PS9_MASK (15 << PCR_PSPWERDWN1_PS9_SHIFT)
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# define PCR_PSPWERDWN1_PS9_Q1 (1 << PCR_PSPWERDWN1_PS9_SHIFT)
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# define PCR_PSPWERDWN1_PS9_Q2 (2 << PCR_PSPWERDWN1_PS9_SHIFT)
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# define PCR_PSPWERDWN1_PS9_Q3 (4 << PCR_PSPWERDWN1_PS9_SHIFT)
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# define PCR_PSPWERDWN1_PS9_Q4 (8 << PCR_PSPWERDWN1_PS9_SHIFT)
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# define PCR_PSPWERDWN1_PS9_QALL (15 << PCR_PSPWERDWN1_PS9_SHIFT)
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#define PCR_PSPWERDWN1_PS10_SHIFT (8) /* Bits 8-11: Quadrants for PS10 */
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#define PCR_PSPWERDWN1_PS10_MASK (15 << PCR_PSPWERDWN1_PS10_SHIFT)
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# define PCR_PSPWERDWN1_PS10_Q1 (1 << PCR_PSPWERDWN1_PS10_SHIFT)
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# define PCR_PSPWERDWN1_PS10_Q2 (2 << PCR_PSPWERDWN1_PS10_SHIFT)
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# define PCR_PSPWERDWN1_PS10_Q3 (4 << PCR_PSPWERDWN1_PS10_SHIFT)
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# define PCR_PSPWERDWN1_PS10_Q4 (8 << PCR_PSPWERDWN1_PS10_SHIFT)
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# define PCR_PSPWERDWN1_PS10_QALL (15 << PCR_PSPWERDWN1_PS10_SHIFT)
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#define PCR_PSPWERDWN1_PS11_SHIFT (12) /* Bits 12-15: Quadrants for PS11 */
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#define PCR_PSPWERDWN1_PS11_MASK (15 << PCR_PSPWERDWN1_PS11_SHIFT)
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# define PCR_PSPWERDWN1_PS11_Q1 (1 << PCR_PSPWERDWN1_PS11_SHIFT)
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# define PCR_PSPWERDWN1_PS11_Q2 (2 << PCR_PSPWERDWN1_PS11_SHIFT)
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# define PCR_PSPWERDWN1_PS11_Q3 (4 << PCR_PSPWERDWN1_PS11_SHIFT)
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# define PCR_PSPWERDWN1_PS11_Q4 (8 << PCR_PSPWERDWN1_PS11_SHIFT)
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# define PCR_PSPWERDWN1_PS11_QALL (15 << PCR_PSPWERDWN1_PS11_SHIFT)
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#define PCR_PSPWERDWN1_PS12_SHIFT (16) /* Bits 16-19: Quadrants for PS12 */
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#define PCR_PSPWERDWN1_PS12_MASK (15 << PCR_PSPWERDWN1_PS12_SHIFT)
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# define PCR_PSPWERDWN1_PS12_Q1 (1 << PCR_PSPWERDWN1_PS12_SHIFT)
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# define PCR_PSPWERDWN1_PS12_Q2 (2 << PCR_PSPWERDWN1_PS12_SHIFT)
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# define PCR_PSPWERDWN1_PS12_Q3 (4 << PCR_PSPWERDWN1_PS12_SHIFT)
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# define PCR_PSPWERDWN1_PS12_Q4 (8 << PCR_PSPWERDWN1_PS12_SHIFT)
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# define PCR_PSPWERDWN1_PS12_QALL (15 << PCR_PSPWERDWN1_PS12_SHIFT)
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#define PCR_PSPWERDWN1_PS13_SHIFT (20) /* Bits 20-23: Quadrants for PS13 */
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#define PCR_PSPWERDWN1_PS13_MASK (15 << PCR_PSPWERDWN1_PS13_SHIFT)
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# define PCR_PSPWERDWN1_PS13_Q1 (1 << PCR_PSPWERDWN1_PS13_SHIFT)
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# define PCR_PSPWERDWN1_PS13_Q2 (2 << PCR_PSPWERDWN1_PS13_SHIFT)
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# define PCR_PSPWERDWN1_PS13_Q3 (4 << PCR_PSPWERDWN1_PS13_SHIFT)
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# define PCR_PSPWERDWN1_PS13_Q4 (8 << PCR_PSPWERDWN1_PS13_SHIFT)
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# define PCR_PSPWERDWN1_PS13_QALL (15 << PCR_PSPWERDWN1_PS13_SHIFT)
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#define PCR_PSPWERDWN1_PS14_SHIFT (24) /* Bits 24-27: Quadrants for PS14 */
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#define PCR_PSPWERDWN1_PS14_MASK (15 << PCR_PSPWERDWN1_PS14_SHIFT)
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# define PCR_PSPWERDWN1_PS14_Q1 (1 << PCR_PSPWERDWN1_PS14_SHIFT)
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# define PCR_PSPWERDWN1_PS14_Q2 (2 << PCR_PSPWERDWN1_PS14_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS14_Q3 (4 << PCR_PSPWERDWN1_PS14_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS14_Q4 (8 << PCR_PSPWERDWN1_PS14_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS14_QALL (15 << PCR_PSPWERDWN1_PS14_SHIFT)
|
||||
#define PCR_PSPWERDWN1_PS15_SHIFT (28) /* Bits 28-31: Quadrants for PS15 */
|
||||
#define PCR_PSPWERDWN1_PS15_MASK (15 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS15_Q1 (1 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS15_Q2 (2 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS15_Q3 (4 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS15_Q4 (8 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
# define PCR_PSPWERDWN1_PS15_QALL (15 << PCR_PSPWERDWN1_PS15_SHIFT)
|
||||
|
||||
/* Peripheral Power-Down Set Register 2 and Peripheral Power-Down Clear Register 2*/
|
||||
|
||||
#define PCR_PSPWERDWN2_PS16_SHIFT (0) /* Bits 0-3: Quadrants for PS16 */
|
||||
#define PCR_PSPWERDWN2_PS16_MASK (15 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS16_Q1 (1 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS16_Q2 (2 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS16_Q3 (4 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS16_Q4 (8 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS16_QALL (15 << PCR_PSPWERDWN2_PS16_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS17_SHIFT (4) /* Bits 4-7: Quadrants for PS17 */
|
||||
#define PCR_PSPWERDWN2_PS17_MASK (15 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS17_Q1 (1 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS17_Q2 (2 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS17_Q3 (4 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS17_Q4 (8 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS17_QALL (15 << PCR_PSPWERDWN2_PS17_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS18_SHIFT (8) /* Bits 8-11: Quadrants for PS18 */
|
||||
#define PCR_PSPWERDWN2_PS18_MASK (15 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS18_Q1 (1 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS18_Q2 (2 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS18_Q3 (4 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS18_Q4 (8 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS18_QALL (15 << PCR_PSPWERDWN2_PS18_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS19_SHIFT (12) /* Bits 12-15: Quadrants for PS19 */
|
||||
#define PCR_PSPWERDWN2_PS19_MASK (15 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS19_Q1 (1 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS19_Q2 (2 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS19_Q3 (4 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS19_Q4 (8 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS19_QALL (15 << PCR_PSPWERDWN2_PS19_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS20_SHIFT (16) /* Bits 16-19: Quadrants for PS20 */
|
||||
#define PCR_PSPWERDWN2_PS20_MASK (15 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS20_Q1 (1 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS20_Q2 (2 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS20_Q3 (4 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS20_Q4 (8 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS20_QALL (15 << PCR_PSPWERDWN2_PS20_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS21_SHIFT (20) /* Bits 20-23: Quadrants for PS21 */
|
||||
#define PCR_PSPWERDWN2_PS21_MASK (15 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS21_Q1 (1 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS21_Q2 (2 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS21_Q3 (4 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS21_Q4 (8 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS21_QALL (15 << PCR_PSPWERDWN2_PS21_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS22_SHIFT (24) /* Bits 24-27: Quadrants for PS22 */
|
||||
#define PCR_PSPWERDWN2_PS22_MASK (15 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS22_Q1 (1 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS22_Q2 (2 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS22_Q3 (4 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS22_Q4 (8 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS22_QALL (15 << PCR_PSPWERDWN2_PS22_SHIFT)
|
||||
#define PCR_PSPWERDWN2_PS23_SHIFT (28) /* Bits 28-31: Quadrants for PS23 */
|
||||
#define PCR_PSPWERDWN2_PS23_MASK (15 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS23_Q1 (1 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS23_Q2 (2 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS23_Q3 (4 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS23_Q4 (8 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
# define PCR_PSPWERDWN2_PS23_QALL (15 << PCR_PSPWERDWN2_PS23_SHIFT)
|
||||
|
||||
/* Peripheral Power-Down Set Register 3 and Peripheral Power-Down Clear Register 3 */
|
||||
|
||||
#define PCR_PSPWERDWN3_PS24_SHIFT (0) /* Bits 0-3: Quadrants for PS24 */
|
||||
#define PCR_PSPWERDWN3_PS24_MASK (15 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS24_Q1 (1 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS24_Q2 (2 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS24_Q3 (4 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS24_Q4 (8 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS24_QALL (15 << PCR_PSPWERDWN3_PS24_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS25_SHIFT (4) /* Bits 4-7: Quadrants for PS25 */
|
||||
#define PCR_PSPWERDWN3_PS25_MASK (15 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS25_Q1 (1 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS25_Q2 (2 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS25_Q3 (4 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS25_Q4 (8 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS25_QALL (15 << PCR_PSPWERDWN3_PS25_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS26_SHIFT (8) /* Bits 8-11: Quadrants for PS26 */
|
||||
#define PCR_PSPWERDWN3_PS26_MASK (15 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS26_Q1 (1 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS26_Q2 (2 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS26_Q3 (4 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS26_Q4 (8 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS26_QALL (15 << PCR_PSPWERDWN3_PS26_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS27_SHIFT (12) /* Bits 12-15: Quadrants for PS27 */
|
||||
#define PCR_PSPWERDWN3_PS27_MASK (15 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS27_Q1 (1 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS27_Q2 (2 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS27_Q3 (4 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS27_Q4 (8 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS27_QALL (15 << PCR_PSPWERDWN3_PS27_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS28_SHIFT (16) /* Bits 16-19: Quadrants for PS28 */
|
||||
#define PCR_PSPWERDWN3_PS28_MASK (15 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS28_Q1 (1 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS28_Q2 (2 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS28_Q3 (4 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS28_Q4 (8 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS28_QALL (15 << PCR_PSPWERDWN3_PS28_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS29_SHIFT (20) /* Bits 20-23: Quadrants for PS29 */
|
||||
#define PCR_PSPWERDWN3_PS29_MASK (15 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS29_Q1 (1 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS29_Q2 (2 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS29_Q3 (4 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS29_Q4 (8 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS29_QALL (15 << PCR_PSPWERDWN3_PS29_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS30_SHIFT (24) /* Bits 24-27: Quadrants for PS30 */
|
||||
#define PCR_PSPWERDWN3_PS30_MASK (15 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS30_Q1 (1 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS30_Q2 (2 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS30_Q3 (4 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS30_Q4 (8 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS30_QALL (15 << PCR_PSPWERDWN3_PS30_SHIFT)
|
||||
#define PCR_PSPWERDWN3_PS31_SHIFT (28) /* Bits 28-31: Quadrants for PS31 */
|
||||
#define PCR_PSPWERDWN3_PS31_MASK (15 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS31_Q1 (1 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS31_Q2 (2 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS31_Q3 (4 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS31_Q4 (8 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
# define PCR_PSPWERDWN3_PS31_QALL (15 << PCR_PSPWERDWN3_PS31_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H */
|
||||
@ -1,161 +0,0 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/tms570/chip/tms570_sys.h
|
||||
* Peripheral Control Register Definitions
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
*
|
||||
* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
|
||||
* Instruments, Literature Number: SPNU517A, September 2013
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
|
||||
#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/tms570_memorymap.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define TMS570_PCR_PMPROTSET0_OFFSET 0x0000 /* Peripheral Memory Protection Set Register 0 */
|
||||
#define TMS570_PCR_PMPROTSET1_OFFSET 0x0004 /* Peripheral Memory Protection Set Register 1 */
|
||||
#define TMS570_PCR_PMPROTCLR0_OFFSET 0x0010 /* Peripheral Memory Protection Clear Register 0 */
|
||||
#define TMS570_PCR_PMPROTCLR1_OFFSET 0x0014 /* Peripheral Memory Protection Clear Register 1 */
|
||||
#define TMS570_PCR_PPROTSET0_OFFSET 0x0020 /* Peripheral Protection Set Register 0 */
|
||||
#define TMS570_PCR_PPROTSET1_OFFSET 0x0024 /* Peripheral Protection Set Register 1 */
|
||||
#define TMS570_PCR_PPROTSET2_OFFSET 0x0028 /* Peripheral Protection Set Register 2 */
|
||||
#define TMS570_PCR_PPROTSET3_OFFSET 0x002c /* Peripheral Protection Set Register 3 */
|
||||
#define TMS570_PCR_PPROTCLR0_OFFSET 0x0040 /* Peripheral Protection Clear Register 0 */
|
||||
#define TMS570_PCR_PPROTCLR1_OFFSET 0x0044 /* Peripheral Protection Clear Register 1 */
|
||||
#define TMS570_PCR_PPROTCLR2_OFFSET 0x0048 /* Peripheral Protection Clear Register 2 */
|
||||
#define TMS570_PCR_PPROTCLR3_OFFSET 0x004c /* Peripheral Protection Clear Register 3 */
|
||||
#define TMS570_PCR_PCSPWRDWNSET0_OFFSET 0x0060 /* Peripheral Memory Power-Down Set Register 0 */
|
||||
#define TMS570_PCR_PCSPWRDWNSET1_OFFSET 0x0064 /* Peripheral Memory Power-Down Set Register 1 */
|
||||
#define TMS570_PCR_PCSPWRDWNCLR0_OFFSET 0x0070 /* Peripheral Memory Power-Down Clear Register 0 */
|
||||
#define TMS570_PCR_PCSPWRDWNCLR1_OFFSET 0x0074 /* Peripheral Memory Power-Down Clear Register 1 */
|
||||
#define TMS570_PCR_PSPWRDWNSET0_OFFSET 0x0080 /* Peripheral Power-Down Set Register 0 */
|
||||
#define TMS570_PCR_PSPWRDWNSET1_OFFSET 0x0084 /* Peripheral Power-Down Set Register 1 */
|
||||
#define TMS570_PCR_PSPWRDWNSET2_OFFSET 0x0088 /* Peripheral Power-Down Set Register 2 */
|
||||
#define TMS570_PCR_PSPWRDWNSET3_OFFSET 0x008c /* Peripheral Power-Down Set Register 3 */
|
||||
#define TMS570_PCR_PSPWRDWNCLR0_OFFSET 0x00a0 /* Peripheral Power-Down Clear Register 0 */
|
||||
#define TMS570_PCR_PSPWRDWNCLR1_OFFSET 0x00a4 /* Peripheral Power-Down Clear Register 1 */
|
||||
#define TMS570_PCR_PSPWRDWNCLR2_OFFSET 0x00a8 /* Peripheral Power-Down Clear Register 2 */
|
||||
#define TMS570_PCR_PSPWRDWNCLR3_OFFSET 0x00ac /* Peripheral Power-Down Clear Register 3 */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define TMS570_PCR_PMPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET0_OFFSET)
|
||||
#define TMS570_PCR_PMPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTSET1_OFFSET)
|
||||
#define TMS570_PCR_PMPROTCLR0 (TMS570_PCR_BASE+TMS570_PCR_PMPROTCLR0_OFFSET)
|
||||
#define TMS570_PCR_PMPROTCLR1 (TMS570_PCR_BASE+TMS570_PCR_PMPROTCLR1_OFFSET)
|
||||
#define TMS570_PCR_PPROTSET0 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET0_OFFSET)
|
||||
#define TMS570_PCR_PPROTSET1 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET1_OFFSET)
|
||||
#define TMS570_PCR_PPROTSET2 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET2_OFFSET)
|
||||
#define TMS570_PCR_PPROTSET3 (TMS570_PCR_BASE+TMS570_PCR_PPROTSET3_OFFSET)
|
||||
#define TMS570_PCR_PPROTCLR0 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR0_OFFSET)
|
||||
#define TMS570_PCR_PPROTCLR1 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR1_OFFSET)
|
||||
#define TMS570_PCR_PPROTCLR2 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR2_OFFSET)
|
||||
#define TMS570_PCR_PPROTCLR3 (TMS570_PCR_BASE+TMS570_PCR_PPROTCLR3_OFFSET)
|
||||
#define TMS570_PCR_PCSPWRDWNSET0 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNSET0_OFFSET)
|
||||
#define TMS570_PCR_PCSPWRDWNSET1 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNSET1_OFFSET)
|
||||
#define TMS570_PCR_PCSPWRDWNCLR0 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNCLR0_OFFSET)
|
||||
#define TMS570_PCR_PCSPWRDWNCLR1 (TMS570_PCR_BASE+TMS570_PCR_PCSPWRDWNCLR1_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNSET0 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET0_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNSET1 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET1_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNSET2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET2_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNSET3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNSET3_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNCLR0 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR0_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNCLR1 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR1_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNCLR2 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR2_OFFSET)
|
||||
#define TMS570_PCR_PSPWRDWNCLR3 (TMS570_PCR_BASE+TMS570_PCR_PSPWRDWNCLR3_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions *******************************************************************/
|
||||
|
||||
/* Peripheral Memory Protection Set Register 0 */
|
||||
#define PCR_PMPROTSET0_
|
||||
/* Peripheral Memory Protection Set Register 1 */
|
||||
#define PCR_PMPROTSET1_
|
||||
/* Peripheral Memory Protection Clear Register 0 */
|
||||
#define PCR_PMPROTCLR0_
|
||||
/* Peripheral Memory Protection Clear Register 1 */
|
||||
#define PCR_PMPROTCLR1_
|
||||
/* Peripheral Protection Set Register 0 */
|
||||
#define PCR_PPROTSET0_
|
||||
/* Peripheral Protection Set Register 1 */
|
||||
#define PCR_PPROTSET1_
|
||||
/* Peripheral Protection Set Register 2 */
|
||||
#define PCR_PPROTSET2_
|
||||
/* Peripheral Protection Set Register 3 */
|
||||
#define PCR_PPROTSET3_
|
||||
/* Peripheral Protection Clear Register 0 */
|
||||
#define PCR_PPROTCLR0_
|
||||
/* Peripheral Protection Clear Register 1 */
|
||||
#define PCR_PPROTCLR1_
|
||||
/* Peripheral Protection Clear Register 2 */
|
||||
#define PCR_PPROTCLR2_
|
||||
/* Peripheral Protection Clear Register 3 */
|
||||
#define PCR_PPROTCLR3_
|
||||
/* Peripheral Memory Power-Down Set Register 0 */
|
||||
#define PCR_PCSPWRDWNSET0_
|
||||
/* Peripheral Memory Power-Down Set Register 1 */
|
||||
#define PCR_PCSPWRDWNSET1_
|
||||
/* Peripheral Memory Power-Down Clear Register 0 */
|
||||
#define PCR_PCSPWRDWNCLR0_
|
||||
/* Peripheral Memory Power-Down Clear Register 1 */
|
||||
#define PCR_PCSPWRDWNCLR1_
|
||||
/* Peripheral Power-Down Set Register 0 */
|
||||
#define PCR_PSPWRDWNSET0_
|
||||
/* Peripheral Power-Down Set Register 1 */
|
||||
#define PCR_PSPWRDWNSET1_
|
||||
/* Peripheral Power-Down Set Register 2 */
|
||||
#define PCR_PSPWRDWNSET2_
|
||||
/* Peripheral Power-Down Set Register 3 */
|
||||
#define PCR_PSPWRDWNSET3_
|
||||
/* Peripheral Power-Down Clear Register 0 */
|
||||
#define PCR_PSPWRDWNCLR0_
|
||||
/* Peripheral Power-Down Clear Register 1 */
|
||||
#define PCR_PSPWRDWNCLR1_
|
||||
/* Peripheral Power-Down Clear Register 2 */
|
||||
#define PCR_PSPWRDWNCLR2_
|
||||
/* Peripheral Power-Down Clear Register 3 */
|
||||
#define PCR_PSPWRDWNCLR3_
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H */
|
||||
@ -330,7 +330,17 @@
|
||||
/* CPU Reset Control Register */
|
||||
#define SYS_CPURSTCR_
|
||||
/* Clock Control Register */
|
||||
#define SYS_CLKCNTL_
|
||||
|
||||
#define SYS_CLKCNTL_PENA (1 << 8) /* Bit 8: Peripheral enable bit */
|
||||
#define SYS_CLKCNTL_VCLKR_SHIFT (16) /* Bits 16-19: VBUS clock ratio */
|
||||
#define SYS_CLKCNTL_VCLKR_MASK (15 << SYS_CLKCNTL_VCLKR_SHIFT)
|
||||
# define SYS_CLKCNTL_VCLKR_DIV1 (0 << SYS_CLKCNTL_VCLKR_SHIFT)
|
||||
# define SYS_CLKCNTL_VCLKR_DIV2 (1 << SYS_CLKCNTL_VCLKR_SHIFT)
|
||||
#define SYS_CLKCNTL_VCLKR2_SHIFT (24) /* Bits 24-27: VBUS clock2 ratio */
|
||||
#define SYS_CLKCNTL_VCLKR2_MASK (15 << SYS_CLKCNTL_VCLKR2_SHIFT)
|
||||
# define SYS_CLKCNTL_VCLKR2_DIV1 (0 << SYS_CLKCNTL_VCLKR2_SHIFT)
|
||||
# define SYS_CLKCNTL_VCLKR2_DIV2 (1 << SYS_CLKCNTL_VCLKR2_SHIFT)
|
||||
|
||||
/* ECP Control Register */
|
||||
#define SYS_ECPCNTL_
|
||||
/* DEV Parity Control Register 1 */
|
||||
@ -339,15 +349,15 @@
|
||||
#define SYS_ECR_
|
||||
/* System Exception Status Register */
|
||||
|
||||
#define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */
|
||||
#define SYS_ESR_EXTRST (1 << 3) /* Bit 3: External reset flag */
|
||||
#define SYS_ESR_SWRST (1 << 4) /* Bit 4: Software reset flag */
|
||||
#define SYS_ESR_CPURST (1 << 5) /* Bit 5: CPU reset flag */
|
||||
#define SYS_ESR_WDRST (1 << 13) /* Bit 13: Watchdog reset flag */
|
||||
#define SYS_ESR_OSCRST (1 << 14) /* Bit 14: Reset caused by an oscillator failure or PLL cycle slip */
|
||||
#define SYS_ESR_PORST (1 << 15) /* Bit 15: Power-up reset */
|
||||
#define SYS_ESR_MPMODE (1 << 0) /* Bit 0: Current memory protection unit (MPU) mode */
|
||||
#define SYS_ESR_EXTRST (1 << 3) /* Bit 3: External reset flag */
|
||||
#define SYS_ESR_SWRST (1 << 4) /* Bit 4: Software reset flag */
|
||||
#define SYS_ESR_CPURST (1 << 5) /* Bit 5: CPU reset flag */
|
||||
#define SYS_ESR_WDRST (1 << 13) /* Bit 13: Watchdog reset flag */
|
||||
#define SYS_ESR_OSCRST (1 << 14) /* Bit 14: Reset caused by an oscillator failure or PLL cycle slip */
|
||||
#define SYS_ESR_PORST (1 << 15) /* Bit 15: Power-up reset */
|
||||
|
||||
#define SYS_ESR_RSTALL (0x0000e038)
|
||||
#define SYS_ESR_RSTALL (0x0000e038)
|
||||
|
||||
/* System Test Abort Status Register */
|
||||
#define SYS_TASR_
|
||||
|
||||
@ -4,9 +4,8 @@
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* This is primarily original code. However, some logic in this file was
|
||||
* inspired/leveraged from TI's Project0 which has a compatible BSD license
|
||||
* and credit should be given in any case:
|
||||
* Some logic in this file was inspired/leveraged from TI's Project0 which
|
||||
* has a compatible BSD license:
|
||||
*
|
||||
* Copyright (c) 2012, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
@ -53,12 +52,24 @@
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip/tms570_sys.h"
|
||||
#include "chip/tms570_pcr.h"
|
||||
#include "tms570_clockconfig.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_pll_setup
|
||||
*
|
||||
* Description:
|
||||
* Configure PLL control registers. The PLL takes (127 + 1024 NR)
|
||||
* oscillator cycles to acquire lock. This initialization sequence
|
||||
* performs all the actions that are not required to be done at full
|
||||
* application speed while the PLL locks.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void tms570_pll_setup(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -105,10 +116,10 @@ static void tms570_pll_setup(void)
|
||||
*
|
||||
* Then:
|
||||
*
|
||||
* Fintclk = 16 MHz / 6 = 2.667 MHz
|
||||
* Fintclk = 16 MHz / 6 = 2.667 MHz
|
||||
* Foutputclock = 2.667 MHz * 120 = 320 MHz
|
||||
* Fpostodclock = 320 MHz / 2
|
||||
* Fpllclock = 160 MHz / 2 = 80 MHz
|
||||
* Fpostodclock = 320 MHz / 2 = 160 MHz
|
||||
* Fpllclock = 160 MHz / 2 = 80 MHz
|
||||
*
|
||||
* NOTE: That R is temporary set to the maximum (32) here.
|
||||
*/
|
||||
@ -130,7 +141,7 @@ static void tms570_pll_setup(void)
|
||||
/* Enable PLL(s) to start up or Lock.
|
||||
*
|
||||
* On wakeup, only clock sources 0, 4, and 5 are enabled: Oscillator, Low
|
||||
* and hight Frequency LPO. Clear bit 1 to enable the PLL. Only the
|
||||
* and high Frequency LPO. Clear bit 1 to enable the PLL. Only the
|
||||
* external clock remains disabled.
|
||||
*/
|
||||
|
||||
@ -138,6 +149,67 @@ static void tms570_pll_setup(void)
|
||||
putreg32(regval, TMS570_SYS_CSDIS);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_pll_setup
|
||||
*
|
||||
* Description:
|
||||
* Configure PLL control registers. The PLL takes (127 + 1024 NR)
|
||||
* oscillator cycles to acquire lock. This initialization sequence
|
||||
* performs all the actions that are not required to be done at full
|
||||
* application speed while the PLL locks.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void tms570_peripheral_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t clkcntl;
|
||||
|
||||
/* Disable Peripherals by clearing the PENA bit in the CLKCNTRL register
|
||||
* before peripheral powerup
|
||||
*/
|
||||
|
||||
clkcntl = getreg32(TMS570_SYS_CLKCNTL);
|
||||
clkcntl &= ~SYS_CLKCNTL_PENA;
|
||||
putreg32(clkcntl, TMS570_SYS_CLKCNTL);
|
||||
|
||||
/* Release peripherals from reset and enable clocks to all peripherals.
|
||||
* Power-up all peripherals by clearing the power down bit for each
|
||||
* quadrant of each peripheral.
|
||||
*
|
||||
* REVISIT: Should we only enable peripherals that are configured?
|
||||
*/
|
||||
|
||||
regval = PCR_PSPWERDWN0_PS0_QALL | PCR_PSPWERDWN0_PS1_QALL |
|
||||
PCR_PSPWERDWN0_PS2_QALL | PCR_PSPWERDWN0_PS3_QALL |
|
||||
PCR_PSPWERDWN0_PS4_QALL | PCR_PSPWERDWN0_PS5_QALL |
|
||||
PCR_PSPWERDWN0_PS6_QALL | PCR_PSPWERDWN0_PS7_QALL;
|
||||
putreg32(regval, TMS570_PCR_PSPWRDWNCLR0);
|
||||
|
||||
regval = PCR_PSPWERDWN1_PS8_QALL | PCR_PSPWERDWN1_PS9_QALL |
|
||||
PCR_PSPWERDWN1_PS10_QALL | PCR_PSPWERDWN1_PS11_QALL |
|
||||
PCR_PSPWERDWN1_PS12_QALL | PCR_PSPWERDWN1_PS13_QALL |
|
||||
PCR_PSPWERDWN1_PS14_QALL | PCR_PSPWERDWN1_PS15_QALL;
|
||||
putreg32(regval, TMS570_PCR_PSPWRDWNCLR1);
|
||||
|
||||
regval = PCR_PSPWERDWN2_PS16_QALL | PCR_PSPWERDWN2_PS17_QALL |
|
||||
PCR_PSPWERDWN2_PS18_QALL | PCR_PSPWERDWN2_PS19_QALL |
|
||||
PCR_PSPWERDWN2_PS20_QALL | PCR_PSPWERDWN2_PS21_QALL |
|
||||
PCR_PSPWERDWN2_PS22_QALL | PCR_PSPWERDWN2_PS23_QALL;
|
||||
putreg32(regval, TMS570_PCR_PSPWRDWNCLR2);
|
||||
|
||||
regval = PCR_PSPWERDWN3_PS24_QALL | PCR_PSPWERDWN3_PS25_QALL |
|
||||
PCR_PSPWERDWN3_PS26_QALL | PCR_PSPWERDWN3_PS27_QALL |
|
||||
PCR_PSPWERDWN3_PS28_QALL | PCR_PSPWERDWN3_PS29_QALL |
|
||||
PCR_PSPWERDWN3_PS30_QALL | PCR_PSPWERDWN3_PS31_QALL;
|
||||
putreg32(regval, TMS570_PCR_PSPWRDWNCLR3);
|
||||
|
||||
/* Enable Peripherals */
|
||||
|
||||
clkcntl |= SYS_CLKCNTL_PENA;
|
||||
putreg32(clkcntl, TMS570_SYS_CLKCNTL);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -155,11 +227,7 @@ static void tms570_pll_setup(void)
|
||||
|
||||
void tms570_clockconfig(void)
|
||||
{
|
||||
/* Configure PLL control registers and enable PLLs. The PLL takes (127 +
|
||||
* 1024 NR) oscillator cycles to acquire lock. This initialization
|
||||
* sequence performs all the tasks that are not required to be done at
|
||||
* full application speed while the PLL locks.
|
||||
*/
|
||||
/* Configure PLL control registers and enable PLLs. */
|
||||
|
||||
tms570_pll_setup();
|
||||
|
||||
@ -173,7 +241,8 @@ void tms570_clockconfig(void)
|
||||
#endif /* CONFIG_TMS570_SELFTEST */
|
||||
|
||||
/* Enable clocks to peripherals and release peripheral reset */
|
||||
# warning Missing Logic
|
||||
|
||||
tms570_peripheral_initialize();
|
||||
|
||||
/* Configure device-level multiplexing and I/O multiplexing */
|
||||
# warning Missing Logic
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user