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Add STM32L152X RCC PLL and FLASH support. Now compiles errorfree.

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This commit is contained in:
Gregory Nutt 2013-05-19 14:35:30 -06:00
parent 106a985667
commit 1e03232e9e
4 changed files with 37 additions and 29 deletions
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37
configs/stm32ldiscovery/include/board.h
View File

@ -85,23 +85,38 @@
/* PLL Configuration
*
* - PLL source is HSE/1 -> 8MHz input
* - PLL multipler is 8 -> 64MHz PLL output
* - PLL output divider 2 -> 32MHz divided PLL output
* - PLL multipler is 8 -> 64MHz PLL VCO clock output
* - PLL output divider 2 -> 32MHz divided down PLL VCO clock output
*
* PLL frequency is 8MHz (XTAL) x 8 / 2 = 32MHz
* Resulting SYSCLK frequency is 8MHz (XTAL) x 8 / 2 = 32MHz
*
* USB/SDIO:
* If the USB or SDIO interface is used in the application, the PLL VCO
* clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96
* MHz frequency. This is required to provide a 48 MHz clock to the USB or
* SDIO (SDIOCLK or USBCLK = PLLVCO/2).
* SYSCLK
* The system clock is derived from the PLL VCO divided by the output division factor.
* Limitations:
* 96 MHz as PLLVCO when the product is in range 1 (1.8V),
* 48 MHz as PLLVCO when the product is in range 2 (1.5V),
* 24 MHz when the product is in range 3 (1.2V).
* Output division to avoid exceeding 32 MHz as SYSCLK.
* The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
*/
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8
#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2
#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL/2)
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* Source is 8MHz HSE */
#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 /* PLLMUL = 8 */
#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */
#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) /* PLL VCO Frequency is 64MHz */
/* Use the PLL and set the SYSCLK source to be the PLL */
/* Use the PLL and set the SYSCLK source to be the diveded down PLL VCO output
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */
/* AHB clock (HCLK) is SYSCLK (32MHz) */

10
configs/stm32ldiscovery/scripts/ld.script
View File

@ -1,5 +1,5 @@
/****************************************************************************
* configs/stm32f3discovery/scripts/ld.script
* configs/stm32fldiscovery/scripts/ld.script
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -33,8 +33,8 @@
*
****************************************************************************/
/* The STM32F303VCT has 256Kb of FLASH beginning at address 0x0800:0000 and
* 40Kb of SRAM.
/* The STM32L152RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and
* 16Kb of SRAM at address 0x20000000.
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
@ -43,8 +43,8 @@
MEMORY
{
flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K
flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
OUTPUT_ARCH(arm)

2
configs/stm32ldiscovery/src/stm32_userleds.c
View File

@ -106,7 +106,7 @@ void stm32_ledinit(void)
void stm32_setled(int led, bool ledon)
{
uint16_t ledcfg;
uint32_t ledcfg;
if (led == BOARD_LED1)
{

17
configs/stm32ldiscovery/src/stm32ldiscovery.h
View File

@ -79,10 +79,10 @@
*
*/
#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
/* Button definitions *******************************************************************************/
/* The STM32L-Discovery supports two buttons; only one button is controllable by
@ -98,14 +98,7 @@
#define MAX_IRQBUTTON BUTTON_USER
#define NUM_IRQBUTTONS 1
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
/* SPI - There is a ST MEMS L3GD20 device on SPI1 using these pins: */
#define GPIO_MEMS_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
#define GPIO_MEMS_INT1 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0)
#define GPIO_MEMS_INT2 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN1)
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTA | GPIO_PIN0)
/****************************************************************************************************
* Public Types