From 1e212981b9d4a3eab9399f8c111fd26f3ca0fb95 Mon Sep 17 00:00:00 2001 From: p-szafonimateusz Date: Thu, 12 Sep 2024 12:31:22 +0200 Subject: [PATCH] drivers/net: add support for Intel I225 network card add support for Intel I225 network card Signed-off-by: p-szafonimateusz --- drivers/net/CMakeLists.txt | 4 + drivers/net/Kconfig | 19 + drivers/net/Make.defs | 4 + drivers/net/igc.c | 1336 ++++++++++++++++++++++++++++++++++++ drivers/net/igc.h | 517 ++++++++++++++ drivers/pci/pci_drivers.c | 11 + include/nuttx/net/igc.h | 57 ++ 7 files changed, 1948 insertions(+) create mode 100644 drivers/net/igc.c create mode 100644 drivers/net/igc.h create mode 100644 include/nuttx/net/igc.h diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt index 438b12ee00..0a8c2b174b 100644 --- a/drivers/net/CMakeLists.txt +++ b/drivers/net/CMakeLists.txt @@ -83,6 +83,10 @@ if(CONFIG_NET) list(APPEND SRCS e1000.c) endif() + if(CONFIG_NET_IGC) + list(APPEND SRCS igc.c) + endif() + if(CONFIG_ARCH_PHY_INTERRUPT) list(APPEND SRCS phy_notify.c) endif() diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f5146c457d..6cc7e5fcea 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -801,4 +801,23 @@ config NET_E1000_82574L endif # NET_E1000 +menuconfig NET_IGC + bool "Intel IGC support" + default n + depends on PCI && PCI_MSIX + ---help--- + Enable IGC PCI Ethernet driver. + +if NET_IGC + +config NET_IGC_RXSPARE + int "Intel IGC spare RX buffers" + default 8 + +config NET_IGC_I225LM + bool "Intel I225LM" + default n + +endif # NET_IGC + endif # NETDEVICES diff --git a/drivers/net/Make.defs b/drivers/net/Make.defs index 900c95adb3..d0b3b01065 100644 --- a/drivers/net/Make.defs +++ b/drivers/net/Make.defs @@ -101,6 +101,10 @@ ifeq ($(CONFIG_DRIVERS_WIFI_SIM),y) CSRCS += wifi_sim.c endif +ifeq ($(CONFIG_NET_IGC),y) + CSRCS += igc.c +endif + # Include network build support DEPPATH += --dep-path net diff --git a/drivers/net/igc.c b/drivers/net/igc.c new file mode 100644 index 0000000000..86df007952 --- /dev/null +++ b/drivers/net/igc.c @@ -0,0 +1,1336 @@ +/***************************************************************************** + * drivers/net/igc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "igc.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Packet buffer size */ + +#define IGC_PKTBUF_SIZE 2048 +#define IGC_RCTL_BSIZE IGC_RCTL_BSIZE_2048 + +/* TX and RX descriptors */ + +#define IGC_TX_DESC 256 +#define IGC_RX_DESC 256 + +/* After RX packet is done, we provide free netpkt to the RX descriptor ring. + * The upper-half network logic is responsible for freeing the RX packets + * so we need some additional spare netpkt buffers to assure that it's + * allways possible to allocate the new RX packet in the recevier logic. + * It's hard to tell how many spare buffers is needed, for now it's set to 8. + */ + +#define IGC_TX_QUOTA IGC_TX_DESC +#define IGC_RX_QUOTA (IGC_RX_DESC + CONFIG_NET_IGC_RXSPARE) + +/* NOTE: CONFIG_IOB_ALIGNMENT must match system D-CACHE line size */ + +#if CONFIG_IOB_NBUFFERS < IGC_RX_QUOTA + IGC_TX_QUOTA +# error CONFIG_IOB_NBUFFERS must be > (IGC_RX_QUOTA + IGC_TX_QUOTA) +#endif + +#if CONFIG_IOB_BUFSIZE < IGC_PKTBUF_SIZE +# error CONFIG_IOB_BUFSIZE must be > IGC_PKTBUF_SIZE +#endif + +/* PCI BARs */ + +#define IGC_MMIO_BAR 0 +#define IGC_FLASH_BAR 1 +#define IGC_IO_BAR 2 +#define IGC_MSIX_BAR 3 + +/* Minimum Inter-interrupt Interval in 1 us increments */ + +#define IGC_INTERRUPT_INTERVAL 100 + +/* For MSI-X we allocate all interrupts to MSI-X vector 0 */ + +#define IGC_GPIE_MSIX_SINGLE (IGC_GPIE_NSICR | IGC_GPIE_EIAME | \ + IGC_GPIE_PBASUPPORT) +#define IGC_MSIX_IMS (IGC_IC_TXDW | IGC_IC_LSC | \ + IGC_IC_RXMISS | IGC_IC_RXDW) +#define IGC_MSIX_EIMS (IGC_EIMS_NOMSIX_OTHER | \ + IGC_EIMS_NOMSIX_RXTX0) +#define IGC_MSIX_IVAR0 (IGC_IVAR0_RXQ0_VAL | IGC_IVAR0_TXQ0_VAL) +#define IGC_MSIX_IVARMSC (IGC_IVARMSC_OTHER_VAL) + +/***************************************************************************** + * Private Types + *****************************************************************************/ + +/* Extend default PCI devie type */ + +struct igc_type_s +{ + uint32_t desc_align; /* Descriptor alignment */ + uint32_t mta_regs; /* MTA registers */ +}; + +/* IGC private data */ + +struct igc_driver_s +{ + /* This holds the information visible to the NuttX network */ + + struct netdev_lowerhalf_s dev; + + /* Driver state */ + + bool bifup; + + /* Packets list */ + + FAR netpkt_t **tx_pkt; + FAR netpkt_t **rx_pkt; + + /* Descriptors */ + + FAR struct igc_tx_leg_s *tx; + FAR struct igc_rx_leg_s *rx; + + size_t tx_now; + size_t tx_done; + size_t rx_now; + + /* PCI data */ + + FAR struct pci_device_s *pcidev; + FAR const struct igc_type_s *type; + int irq; + uint64_t base; + +#ifdef CONFIG_NET_MCASTGROUP + /* MTA shadow */ + + FAR uint32_t *mta; +#endif +}; + +/***************************************************************************** + * Private Functions Definitions + *****************************************************************************/ + +/* Helpers */ + +static uint32_t igc_getreg_mem(FAR struct igc_driver_s *priv, + unsigned int offset); +static void igc_putreg_mem(FAR struct igc_driver_s *priv, + unsigned int offset, + uint32_t value); +#ifdef CONFIG_DEBUG_NET_INFO +static void igc_dump_reg(FAR struct igc_driver_s *priv, + FAR const char *msg, unsigned int offset); +static void igc_dump_mem(FAR struct igc_driver_s *priv, FAR const char *msg); +#endif + +/* Common TX logic */ + +static int igc_transmit(FAR struct netdev_lowerhalf_s *dev, + FAR netpkt_t *pkt); + +/* Interrupt handling */ + +static FAR netpkt_t *igc_receive(FAR struct netdev_lowerhalf_s *dev); +static void igc_txdone(FAR struct netdev_lowerhalf_s *dev); + +static void igc_msix_interrupt(FAR struct igc_driver_s *priv); +static int igc_interrupt(int irq, FAR void *context, FAR void *arg); + +/* NuttX callback functions */ + +static int igc_ifup(FAR struct netdev_lowerhalf_s *dev); +static int igc_ifdown(FAR struct netdev_lowerhalf_s *dev); + +#ifdef CONFIG_NET_MCASTGROUP +static uint32_t igc_hashmta(FAR struct igc_driver_s *priv, + FAR const uint8_t *mac); +static int igc_addmac(FAR struct netdev_lowerhalf_s *dev, + FAR const uint8_t *mac); +static int igc_rmmac(FAR struct netdev_lowerhalf_s *dev, + FAR const uint8_t *mac); +#endif + +/* Initialization */ + +static void igc_disable(FAR struct igc_driver_s *priv); +static void igc_enable(FAR struct igc_driver_s *priv); +static int igc_initialize(FAR struct igc_driver_s *priv); +static int igc_probe(FAR struct pci_device_s *dev); + +/***************************************************************************** + * Private Data + *****************************************************************************/ + +#ifdef CONFIG_NET_IGC_I225LM +/* Intel I225LM */ + +static const struct igc_type_s g_igc_i225lm = +{ + .desc_align = 128, + .mta_regs = 128 +}; +#endif + +static const struct pci_device_id_s g_igc_id_table[] = +{ +#ifdef CONFIG_NET_IGC_I225LM + { + PCI_DEVICE(0x8086, 0x15f2), + .driver_data = (uintptr_t)&g_igc_i225lm + }, +#endif + { } +}; + +static struct pci_driver_s g_pci_igc_drv = +{ + .id_table = g_igc_id_table, + .probe = igc_probe, +}; + +static const struct netdev_ops_s g_igc_ops = +{ + .ifup = igc_ifup, + .ifdown = igc_ifdown, + .transmit = igc_transmit, + .receive = igc_receive, +#ifdef CONFIG_NET_MCASTGROUP + .addmac = igc_addmac, + .rmmac = igc_rmmac, +#endif +}; + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: igc_getreg_mem + *****************************************************************************/ + +static uint32_t igc_getreg_mem(FAR struct igc_driver_s *priv, + unsigned int offset) +{ + uintptr_t addr = priv->base + offset; + return *((FAR volatile uint32_t *)addr); +} + +/***************************************************************************** + * Name: igc_putreg_mem + *****************************************************************************/ + +static void igc_putreg_mem(FAR struct igc_driver_s *priv, + unsigned int offset, + uint32_t value) +{ + uintptr_t addr = priv->base + offset; + *((FAR volatile uint32_t *)addr) = value; +} + +#ifdef CONFIG_DEBUG_NET_INFO +/***************************************************************************** + * Name: igc_dump_reg + *****************************************************************************/ + +static void igc_dump_reg(FAR struct igc_driver_s *priv, + FAR const char *msg, unsigned int offset) +{ + ninfo("\t%s:\t\t0x%" PRIx32 "\n", msg, igc_getreg_mem(priv, offset)); +} + +/***************************************************************************** + * Name: igc_dump_mem + *****************************************************************************/ + +static void igc_dump_mem(FAR struct igc_driver_s *priv, FAR const char *msg) +{ + ninfo("Dump: %s\n", msg); + + ninfo("General registers:\n"); + igc_dump_reg(priv, "CTRL", IGC_CTRL); + igc_dump_reg(priv, "STATUS", IGC_STATUS); + igc_dump_reg(priv, "CTRLEXT", IGC_CTRLEXT); + igc_dump_reg(priv, "IPCNFG", IGC_IPCNFG); + igc_dump_reg(priv, "PHMP", IGC_PHMP); + + ninfo("Interrupt registers:\n"); + igc_dump_reg(priv, "ICS", IGC_ICS); + igc_dump_reg(priv, "IMS", IGC_IMS); + igc_dump_reg(priv, "IAM", IGC_IAM); + igc_dump_reg(priv, "EICS", IGC_EICS); + igc_dump_reg(priv, "EIMS", IGC_EIMS); + igc_dump_reg(priv, "EIAM", IGC_EIAM); + igc_dump_reg(priv, "EIAC", IGC_EIAC); + igc_dump_reg(priv, "IVAR0", IGC_IVAR0); + igc_dump_reg(priv, "IVARMSC", IGC_IVARMSC); + igc_dump_reg(priv, "GPIE", IGC_GPIE); + igc_dump_reg(priv, "PICAUSE", IGC_PICAUSE); + igc_dump_reg(priv, "PIENA", IGC_PIENA); + igc_dump_reg(priv, "PBACL", IGC_PBACL); + igc_dump_reg(priv, "EITR0", IGC_EITR0); + + ninfo("Receive registers:\n"); + igc_dump_reg(priv, "RCTL", IGC_RCTL); + igc_dump_reg(priv, "PSRCTL", IGC_PSRCTL); + igc_dump_reg(priv, "FCRTL0", IGC_FCRTL0); + igc_dump_reg(priv, "FCRTH0", IGC_FCRTH0); + igc_dump_reg(priv, "RXPBSIZE", IGC_RXPBSIZE); + igc_dump_reg(priv, "FCRTV", IGC_FCRTV); + igc_dump_reg(priv, "RDBAL0", IGC_RDBAL0); + igc_dump_reg(priv, "RDBAH0", IGC_RDBAH0); + igc_dump_reg(priv, "RDLEN0", IGC_RDLEN0); + igc_dump_reg(priv, "SRRCTL0", IGC_SRRCTL0); + igc_dump_reg(priv, "RDH0", IGC_RDH0); + igc_dump_reg(priv, "RDT0", IGC_RDT0); + igc_dump_reg(priv, "RXDCTL0", IGC_RXDCTL0); + igc_dump_reg(priv, "RXCTL0", IGC_RXCTL0); + igc_dump_reg(priv, "RXCSUM", IGC_RXCSUM); + igc_dump_reg(priv, "RLPML", IGC_RLPML); + igc_dump_reg(priv, "RFCTL", IGC_RFCTL); + igc_dump_reg(priv, "MTA", IGC_MTA); + igc_dump_reg(priv, "RAL", IGC_RAL); + igc_dump_reg(priv, "RAH", IGC_RAH); + + ninfo("Transmit registers:\n"); + igc_dump_reg(priv, "TCTL", IGC_TCTL); + igc_dump_reg(priv, "TCTLEXT", IGC_TCTLEXT); + igc_dump_reg(priv, "TIPG", IGC_TIPG); + igc_dump_reg(priv, "RETXCTL", IGC_RETXCTL); + igc_dump_reg(priv, "TXPBSIZE", IGC_TXPBSIZE); + igc_dump_reg(priv, "DTXCTL", IGC_DTXCTL); + igc_dump_reg(priv, "TDBAL0", IGC_TDBAL0); + igc_dump_reg(priv, "TDBAH0", IGC_TDBAH0); + igc_dump_reg(priv, "TDLEN0", IGC_TDLEN0); + igc_dump_reg(priv, "TDH0", IGC_TDH0); + igc_dump_reg(priv, "TDT0", IGC_TDT0); + igc_dump_reg(priv, "TXDCTL0", IGC_TXDCTL0); + igc_dump_reg(priv, "TXCTL0", IGC_TXCTL0); + igc_dump_reg(priv, "TDWBAL0", IGC_TDWBAL0); + igc_dump_reg(priv, "TDWBAH0", IGC_TDWBAH0); + + ninfo("Statistic registers:\n"); + igc_dump_reg(priv, "CRCERRS", IGC_CRCERRS); + igc_dump_reg(priv, "ALGNERRC", IGC_ALGNERRC); + igc_dump_reg(priv, "RXERRC", IGC_RXERRC); + igc_dump_reg(priv, "MPC", IGC_MPC); + igc_dump_reg(priv, "SCC", IGC_SCC); + igc_dump_reg(priv, "ECOL", IGC_ECOL); + igc_dump_reg(priv, "MCC", IGC_MCC); + igc_dump_reg(priv, "LATECOL", IGC_LATECOL); + igc_dump_reg(priv, "COLC", IGC_COLC); + igc_dump_reg(priv, "DC", IGC_DC); + igc_dump_reg(priv, "TNCRS", IGC_TNCRS); + igc_dump_reg(priv, "CEXTERR", IGC_CEXTERR); + igc_dump_reg(priv, "RLEC", IGC_RLEC); + igc_dump_reg(priv, "XONRXC", IGC_XONRXC); + igc_dump_reg(priv, "XONTXC", IGC_XONTXC); + igc_dump_reg(priv, "XOFFRXC", IGC_XOFFRXC); + igc_dump_reg(priv, "XOFFTXC", IGC_XOFFTXC); + igc_dump_reg(priv, "FCRUC", IGC_FCRUC); + igc_dump_reg(priv, "PRC64", IGC_PRC64); + igc_dump_reg(priv, "PRC127", IGC_PRC127); + igc_dump_reg(priv, "PRC255", IGC_PRC255); + igc_dump_reg(priv, "PRC511", IGC_PRC511); + igc_dump_reg(priv, "PRC1023", IGC_PRC1023); + igc_dump_reg(priv, "PRC1522", IGC_PRC1522); + igc_dump_reg(priv, "GPRC", IGC_GPRC); + igc_dump_reg(priv, "BPRC", IGC_BPRC); + igc_dump_reg(priv, "MPRC", IGC_MPRC); + igc_dump_reg(priv, "GPTC", IGC_GPTC); + igc_dump_reg(priv, "GORCL", IGC_GORCL); + igc_dump_reg(priv, "GORCH", IGC_GORCH); + igc_dump_reg(priv, "GOTCL", IGC_GOTCL); + igc_dump_reg(priv, "GOTCH", IGC_GOTCH); + igc_dump_reg(priv, "RNBC", IGC_RNBC); + igc_dump_reg(priv, "RUC", IGC_RUC); + igc_dump_reg(priv, "RFC", IGC_RFC); + igc_dump_reg(priv, "ROC", IGC_ROC); + igc_dump_reg(priv, "RJC", IGC_RJC); + igc_dump_reg(priv, "MNGPRC", IGC_MNGPRC); + igc_dump_reg(priv, "MPDC", IGC_MPDC); + igc_dump_reg(priv, "MPTC", IGC_MPTC); + igc_dump_reg(priv, "TORL", IGC_TORL); + igc_dump_reg(priv, "TORH", IGC_TORH); + igc_dump_reg(priv, "TOT", IGC_TOT); + igc_dump_reg(priv, "TPR", IGC_TPR); + igc_dump_reg(priv, "TPT", IGC_TPT); + igc_dump_reg(priv, "PTC64", IGC_PTC64); + igc_dump_reg(priv, "PTC127", IGC_PTC127); + igc_dump_reg(priv, "PTC255", IGC_PTC255); + igc_dump_reg(priv, "PTC511", IGC_PTC511); + igc_dump_reg(priv, "PTC1023", IGC_PTC1023); + igc_dump_reg(priv, "PTC1522", IGC_PTC1522); + igc_dump_reg(priv, "MPTC", IGC_MPTC); + igc_dump_reg(priv, "BPTC", IGC_BPTC); + igc_dump_reg(priv, "TSCTC", IGC_TSCTC); + igc_dump_reg(priv, "TSCTFC", IGC_TSCTFC); + igc_dump_reg(priv, "IAC", IGC_IAC); +} +#endif + +/***************************************************************************** + * Name: igc_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + *****************************************************************************/ + +static int igc_transmit(FAR struct netdev_lowerhalf_s *dev, + FAR netpkt_t *pkt) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + uint64_t pa = 0; + int desc = priv->tx_now; + size_t len = netpkt_getdatalen(dev, pkt); + + ninfo("transmit\n"); + + /* Check the send length */ + + if (len > IGC_PKTBUF_SIZE) + { + nerr("net transmit buffer too large\n"); + return -EINVAL; + } + + /* Store TX packet reference */ + + priv->tx_pkt[priv->tx_now] = pkt; + + /* Prepare next TX descriptor */ + + priv->tx_now = (priv->tx_now + 1) % IGC_TX_DESC; + + /* Setup TX descriptor */ + + pa = up_addrenv_va_to_pa(netpkt_getdata(dev, pkt)); + + priv->tx[desc].addr = pa; + priv->tx[desc].len = len; + priv->tx[desc].cmd = (IGC_TDESC_CMD_EOP | IGC_TDESC_CMD_IFCS | + IGC_TDESC_CMD_RS); + priv->tx[desc].cso = 0; + priv->tx[desc].status = 0; + + SP_DSB(); + + /* Update TX tail */ + + igc_putreg_mem(priv, IGC_TDT0, priv->tx_now); + + ninfodumpbuffer("Transmitted:", netpkt_getdata(dev, pkt), len); + + return OK; +} + +/***************************************************************************** + * Name: igc_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + *****************************************************************************/ + +static FAR netpkt_t * igc_receive(FAR struct netdev_lowerhalf_s *dev) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + FAR netpkt_t *pkt = NULL; + FAR struct igc_rx_leg_s *rx = NULL; + int desc = 0; + + desc = priv->rx_now; + + /* Get RX descriptor and RX packet */ + + rx = &priv->rx[desc]; + pkt = priv->rx_pkt[desc]; + + /* Check if descriptor done */ + + if (!(rx->status & IGC_RDESC_STATUS_DD)) + { + return NULL; + } + + /* Next descriptor */ + + priv->rx_now = (priv->rx_now + 1) % IGC_RX_DESC; + + /* Allocate new rx packet */ + + priv->rx_pkt[desc] = netpkt_alloc(dev, NETPKT_RX); + if (priv->rx_pkt[desc] == NULL) + { + nerr("alloc pkt_new failed\n"); + PANIC(); + } + + /* Set packet length */ + + netpkt_setdatalen(dev, pkt, rx->len); + + /* Store new packet in RX descriptor ring */ + + rx->addr = up_addrenv_va_to_pa( + netpkt_getdata(dev, priv->rx_pkt[desc])); + rx->len = 0; + rx->status = 0; + + /* Update RX tail */ + + igc_putreg_mem(priv, IGC_RDT0, desc); + + /* Handle errros */ + + if (rx->errors) + { + nerr("RX error reported (%"PRIu8")\n", rx->errors); + NETDEV_RXERRORS(&priv->dev); + netpkt_free(dev, pkt, NETPKT_RX); + return NULL; + } + + return pkt; +} + +/***************************************************************************** + * Name: igc_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + *****************************************************************************/ + +static void igc_txdone(FAR struct netdev_lowerhalf_s *dev) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + + while (priv->tx_now != priv->tx_done) + { + if (priv->tx[priv->tx_done].status == 0) + { + break; + } + + if (!(priv->tx[priv->tx_done].status & IGC_TDESC_STATUS_DD)) + { + nerr("tx failed: 0x%" PRIx32 "\n", priv->tx[priv->tx_done].status); + NETDEV_TXERRORS(priv->dev); + } + + /* Free net packet */ + + netpkt_free(dev, priv->tx_pkt[priv->tx_done], NETPKT_TX); + + /* Next descriptor */ + + priv->tx_done = (priv->tx_done + 1) % IGC_TX_DESC; + } + + netdev_lower_txdone(dev); +} + +/***************************************************************************** + * Name: igc_misx_interrupt + * + * Description: + * Perform MSI-X interrupt work + * + * Input Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Runs on a worker thread. + * + *****************************************************************************/ + +static void igc_msix_interrupt(FAR struct igc_driver_s *priv) +{ + uint32_t icr = 0; + uint32_t eicr = 0; + uint32_t tmp = 0; + + /* Get interrupts */ + + icr = igc_getreg_mem(priv, IGC_ICR); + eicr = igc_getreg_mem(priv, IGC_EICR); + + ninfo("eicr = 0x%" PRIx32 " icr = 0x%" PRIx32 "\n", eicr, icr); + + if (icr == 0) + { + /* Ignore spurious interrupts */ + + return; + } + + /* Receiver Descriptor Write Back */ + + if (icr & IGC_IC_RXDW) + { + netdev_lower_rxready(&priv->dev); + } + + /* Link Status Change */ + + if (icr & IGC_IC_LSC) + { + tmp = igc_getreg_mem(priv, IGC_STATUS); + if (tmp & IGC_STATUS_LU) + { + ninfo("Link up, status = 0x%x\n", tmp); + netdev_lower_carrier_on(&priv->dev); + } + else + { + ninfo("Link down\n"); + netdev_lower_carrier_off(&priv->dev); + } + } + + /* Receiver Miss */ + + if (icr & IGC_IC_RXMISS) + { + nerr("Receiver Miss\n"); + netdev_lower_rxready(&priv->dev); + } + + /* Transmit Descriptor Written Back */ + + if (icr & IGC_IC_TXDW) + { + igc_txdone(&priv->dev); + } +} + +/***************************************************************************** + * Name: igc_interrupt + * + * Description: + * Hardware interrupt handler + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * Runs in the context of a the Ethernet interrupt handler. Local + * interrupts are disabled by the interrupt logic. + * + *****************************************************************************/ + +static int igc_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)arg; + + DEBUGASSERT(priv != NULL); + + ninfo("interrupt!\n"); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + igc_msix_interrupt(priv); + + return OK; +} + +/***************************************************************************** + * Name: igc_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + *****************************************************************************/ + +static int igc_ifup(FAR struct netdev_lowerhalf_s *dev) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + irqstate_t flags; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %u.%u.%u.%u\n", + ip4_addr1(dev->netdev.d_ipaddr), ip4_addr2(dev->netdev.d_ipaddr), + ip4_addr3(dev->netdev.d_ipaddr), ip4_addr4(dev->netdev.d_ipaddr)); +#endif + +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->netdev.d_ipv6addr[0], dev->netdev.d_ipv6addr[1], + dev->netdev.d_ipv6addr[2], dev->netdev.d_ipv6addr[3], + dev->netdev.d_ipv6addr[4], dev->netdev.d_ipv6addr[5], + dev->netdev.d_ipv6addr[6], dev->netdev.d_ipv6addr[7]); +#endif + + /* Enable the Ethernet */ + + flags = enter_critical_section(); + igc_enable(priv); + priv->bifup = true; + leave_critical_section(flags); + + return OK; +} + +/***************************************************************************** + * Name: igc_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + *****************************************************************************/ + +static int igc_ifdown(FAR struct netdev_lowerhalf_s *dev) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Put the EMAC in its reset, non-operational state. This should be + * a known configuration that will guarantee the igc_ifup() always + * successfully brings the interface back up. + */ + + igc_disable(priv); + + /* Mark the device "down" */ + + priv->bifup = false; + leave_critical_section(flags); + return OK; +} + +#ifdef CONFIG_NET_MCASTGROUP +/***************************************************************************** + * Name: igc_hashmta + * + * Note: This logic is based on freeBSD igc implementation + * + *****************************************************************************/ + +static uint32_t igc_hashmta(FAR struct igc_driver_s *priv, + FAR const uint8_t *mac) +{ + uint32_t hash_mask = 0; + uint8_t bit_shift = 0; + + /* Register count multiplied by bits per register */ + + hash_mask = (priv->type->mta_regs * 32) - 1; + +/* For a mc_filter_type of 0, bit_shift is the number of left-shifts + * where 0xFF would still fall within the hash mask. + */ + + while (hash_mask >> bit_shift != 0xff) + { + bit_shift++; + } + + /* bit_shift += 0 because we have MO set to 0 */ + + return hash_mask & ((mac[4] >> (8 - bit_shift)) | (mac[5] << bit_shift)); +} + +/***************************************************************************** + * Name: igc_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + *****************************************************************************/ + +static int igc_addmac(FAR struct netdev_lowerhalf_s *dev, + FAR const uint8_t *mac) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + uint16_t hash = 0; + uint8_t row = 0; + uint8_t bit = 0; + int i = 0; + + hash = igc_hashmta(priv, mac); + bit = hash & 31; + row = (hash >> 5) & (priv->type->mta_regs - 1); + + /* Bits 4:0 indicate bit in row word */ + + priv->mta[row] |= (1 << bit); + + /* Replace the entire MTA */ + + for (i = priv->type->mta_regs - 1; i >= 0; i--) + { + igc_putreg_mem(priv, IGC_MTA + (i << 2), priv->mta[i]); + } + + return OK; +} + +/***************************************************************************** + * Name: igc_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + *****************************************************************************/ + +static int igc_rmmac(FAR struct netdev_lowerhalf_s *dev, + FAR const uint8_t *mac) +{ + FAR struct igc_driver_s *priv = (FAR struct igc_driver_s *)dev; + uint16_t hash = 0; + uint8_t row = 0; + uint8_t bit = 0; + int i = 0; + + hash = igc_hashmta(priv, mac); + bit = hash & 31; + row = (hash >> 5) & (priv->type->mta_regs - 1); + + /* Bits 4:0 indicate bit in row word */ + + priv->mta[row] &= ~(1 << bit); + + /* Replace the entire MTA */ + + for (i = priv->type->mta_regs - 1; i >= 0; i--) + { + igc_putreg_mem(priv, IGC_MTA + (i << 2), priv->mta[i]); + } + + return OK; +} +#endif /* CONFIG_NET_MCASTGROUP */ + +/***************************************************************************** + * Name: igc_disable + * + * Description: + * Reset device to known state. + * + *****************************************************************************/ + +static void igc_disable(FAR struct igc_driver_s *priv) +{ + int i = 0; + + /* Reset Tx tail */ + + igc_putreg_mem(priv, IGC_TDH0, 0); + igc_putreg_mem(priv, IGC_TDT0, 0); + + /* Reset Rx tail */ + + igc_putreg_mem(priv, IGC_RDH0, 0); + igc_putreg_mem(priv, IGC_RDT0, 0); + + /* Disable interrupts */ + + igc_putreg_mem(priv, IGC_EIMC, IGC_MSIX_EIMS); + igc_putreg_mem(priv, IGC_IMC, IGC_MSIX_IMS); + up_disable_irq(priv->irq); + + /* Disable Transmiter */ + + igc_putreg_mem(priv, IGC_TCTL, 0); + + /* Disable Receiver */ + + igc_putreg_mem(priv, IGC_RCTL, 0); + + /* Free RX packets */ + + for (i = 0; i < IGC_RX_DESC; i += 1) + { + netpkt_free(&priv->dev, priv->rx_pkt[i], NETPKT_RX); + } +} + +/***************************************************************************** + * Name: igc_phy_reset + * + * Description: + * Reset PHY + * + *****************************************************************************/ + +static void igc_phy_reset(FAR struct igc_driver_s *priv) +{ + uint32_t regval = 0; + + regval = igc_getreg_mem(priv, IGC_CTRL); + igc_putreg_mem(priv, IGC_CTRL, regval | IGC_CTRL_PHYRST); + up_udelay(100); + igc_putreg_mem(priv, IGC_CTRL, regval); + up_udelay(100); +} + +/***************************************************************************** + * Name: igc_enable + * + * Description: + * Enable device. + * + *****************************************************************************/ + +static void igc_enable(FAR struct igc_driver_s *priv) +{ + FAR struct netdev_lowerhalf_s *dev = (FAR struct netdev_lowerhalf_s *)priv; + uint64_t pa = 0; + uint32_t regval = 0; + int i = 0; + + /* Reset PHY */ + + igc_phy_reset(priv); + + /* Reset Multicast Table Array */ + + for (i = 0; i < priv->type->mta_regs; i++) + { + igc_putreg_mem(priv, IGC_MTA + (i << 2), 0); + } + + /* Allocate RX packets */ + + for (i = 0; i < IGC_RX_DESC; i += 1) + { + priv->rx_pkt[i] = netpkt_alloc(dev, NETPKT_RX); + if (priv->rx_pkt[i] == NULL) + { + nerr("alloc rx_pkt failed\n"); + PANIC(); + } + + /* Configure RX descriptor */ + + priv->rx[i].addr = up_addrenv_va_to_pa( + netpkt_getdata(dev, priv->rx_pkt[i])); + priv->rx[i].len = 0; + priv->rx[i].status = 0; + } + + /* Setup TX descriptor */ + + /* The address passed to the NIC must be physical */ + + pa = up_addrenv_va_to_pa(priv->tx); + + regval = (uint32_t)pa; + igc_putreg_mem(priv, IGC_TDBAL0, regval); + regval = (uint32_t)(pa >> 32); + igc_putreg_mem(priv, IGC_TDBAH0, regval); + + regval = IGC_TX_DESC * sizeof(struct igc_tx_leg_s); + igc_putreg_mem(priv, IGC_TDLEN0, regval); + + priv->tx_now = 0; + + /* Reset TX tail */ + + igc_putreg_mem(priv, IGC_TDH0, 0); + igc_putreg_mem(priv, IGC_TDT0, 0); + + /* Setup RX descriptor */ + + /* The address passed to the NIC must be physical */ + + pa = up_addrenv_va_to_pa(priv->rx); + + regval = (uint32_t)pa; + igc_putreg_mem(priv, IGC_RDBAL0, regval); + regval = (uint32_t)(pa >> 32); + igc_putreg_mem(priv, IGC_RDBAH0, regval); + + regval = IGC_RX_DESC * sizeof(struct igc_rx_leg_s); + igc_putreg_mem(priv, IGC_RDLEN0, regval); + + priv->rx_now = 0; + + /* Enable interrupts */ + + igc_putreg_mem(priv, IGC_EIMS, IGC_MSIX_EIMS); + igc_putreg_mem(priv, IGC_IMS, IGC_MSIX_IMS); + up_enable_irq(priv->irq); + + /* Set link up */ + + igc_putreg_mem(priv, IGC_CTRL, IGC_CTRL_SLU); + + /* Setup and enable Transmiter */ + + regval = igc_getreg_mem(priv, IGC_TCTL); + regval |= IGC_TCTL_EN | IGC_TCTL_PSP; + igc_putreg_mem(priv, IGC_TCTL, regval); + + /* Setup and enable Receiver */ + + regval = (IGC_RCTL_EN | IGC_RCTL_MPE | + (IGC_RCTL_BSIZE << IGC_RCTL_BSIZE_SHIFT)); +#ifdef CONFIG_NET_PROMISCUOUS + regval |= IGC_RCTL_UPE | IGC_RCTL_MPE; +#endif + igc_putreg_mem(priv, IGC_RCTL, regval); + + /* Enable TX queeu */ + + regval = igc_getreg_mem(priv, IGC_TXDCTL0); + regval |= IGC_TXDCTL_ENABLE; + igc_putreg_mem(priv, IGC_TXDCTL0, regval); + + /* Enable RX queue */ + + regval = igc_getreg_mem(priv, IGC_RXDCTL0); + regval |= IGC_RXDCTL_ENABLE; + igc_putreg_mem(priv, IGC_RXDCTL0, regval); + + /* Reset RX tail - after queue is enabled */ + + igc_putreg_mem(priv, IGC_RDH0, 0); + igc_putreg_mem(priv, IGC_RDT0, IGC_RX_DESC); + +#ifdef CONFIG_DEBUG_NET_INFO + /* Dump memory */ + + igc_dump_mem(priv, "enabled"); +#endif +} + +/***************************************************************************** + * Name: igc_initialize + * + * Description: + * Initialize device + * + *****************************************************************************/ + +static int igc_initialize(FAR struct igc_driver_s *priv) +{ + uint32_t regval = 0; + uint64_t mac = 0; + int ret = OK; + + /* Allocate MSI */ + + ret = pci_alloc_irq(priv->pcidev, &priv->irq, 1); + if (ret != 1) + { + nerr("Failed to allocate MSI %d\n", ret); + return ret; + } + + /* Attach IRQ */ + + irq_attach(priv->irq, igc_interrupt, priv); + + /* Connect MSI */ + + ret = pci_connect_irq(priv->pcidev, &priv->irq, 1); + if (ret != OK) + { + nerr("Failed to connect MSI %d\n", ret); + pci_release_irq(priv->pcidev, &priv->irq, 1); + + return -ENOTSUP; + } + + /* Clear previous Extended Interrupt Mask */ + + igc_putreg_mem(priv, IGC_EIMC, 0xffffffff); + igc_putreg_mem(priv, IGC_IMC, 0xffffffff); + + /* Configure MSI-X */ + + igc_putreg_mem(priv, IGC_IVAR0, IGC_MSIX_IVAR0); + igc_putreg_mem(priv, IGC_IVARMSC, IGC_MSIX_IVARMSC); + + /* Enable MSI-X Single Vector */ + + igc_putreg_mem(priv, IGC_GPIE, IGC_GPIE_MSIX_SINGLE); + igc_putreg_mem(priv, IGC_EIMS, IGC_MSIX_EIMS); + + /* Configure Other causes */ + + igc_putreg_mem(priv, IGC_IMS, IGC_MSIX_IMS); + + /* Configure Interrupt Throttle */ + + igc_putreg_mem(priv, IGC_EITR0, (IGC_INTERRUPT_INTERVAL << 2)); + + /* Get MAC if valid */ + + regval = igc_getreg_mem(priv, IGC_RAH); + if (regval & IGC_RAH_AV) + { + mac = ((uint64_t)regval & IGC_RAH_RAH_MASK) << 32; + mac |= igc_getreg_mem(priv, IGC_RAL); + memcpy(&priv->dev.netdev.d_mac.ether, &mac, sizeof(struct ether_addr)); + } + else + { + nwarn("Receive Address not vaild!\n"); + } + + return OK; +} + +/***************************************************************************** + * Name: igc_probe + * + * Description: + * Initialize device + * + *****************************************************************************/ + +static int igc_probe(FAR struct pci_device_s *dev) +{ + FAR const struct igc_type_s *type = NULL; + FAR struct igc_driver_s *priv = NULL; + FAR struct netdev_lowerhalf_s *netdev = NULL; + int ret = -ENOMEM; + + /* Get type data associated with this PCI device card */ + + type = (FAR const struct igc_type_s *)dev->id->driver_data; + + /* Not found private data */ + + if (type == NULL) + { + return -ENODEV; + } + + /* Allocate the interface structure */ + + priv = kmm_zalloc(sizeof(*priv)); + if (priv == NULL) + { + return ret; + } + + priv->pcidev = dev; + + /* Allocate TX descriptors */ + + priv->tx = kmm_memalign(type->desc_align, + IGC_TX_DESC * sizeof(struct igc_tx_leg_s)); + if (priv->tx == NULL) + { + nerr("alloc tx failed %d\n", errno); + goto errout; + } + + /* Allocate RX descriptors */ + + priv->rx = kmm_memalign(type->desc_align, + IGC_RX_DESC * sizeof(struct igc_rx_leg_s)); + if (priv->rx == NULL) + { + nerr("alloc rx failed %d\n", errno); + goto errout; + } + + /* Allocate TX packet pointer array */ + + priv->tx_pkt = kmm_zalloc(IGC_TX_DESC * sizeof(netpkt_t *)); + if (priv->tx_pkt == NULL) + { + nerr("alloc tx_pkt failed\n"); + goto errout; + } + + /* Allocate RX packet pointer array */ + + priv->rx_pkt = kmm_zalloc(IGC_RX_DESC * sizeof(netpkt_t *)); + if (priv->rx_pkt == NULL) + { + nerr("alloc rx_pkt failed\n"); + goto errout; + } + +#ifdef CONFIG_NET_MCASTGROUP + /* Allocate MTA shadow */ + + priv->mta = kmm_zalloc(type->mta_regs); + if (priv->mta == NULL) + { + nerr("alloc mta failed\n"); + goto errout; + } +#endif + + /* Get devices */ + + netdev = &priv->dev; + priv->type = type; + + pci_set_master(dev); + pciinfo("Enabled bus mastering\n"); + pci_enable_device(dev); + pciinfo("Enabled memory resources\n"); + + /* If the BAR is MMIO then it must be mapped */ + + priv->base = (uintptr_t)pci_map_bar(dev, IGC_MMIO_BAR); + if (!priv->base) + { + pcierr("Not found MMIO control bar\n"); + goto errout; + } + + /* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */ + + ret = igc_initialize(priv); + if (ret != OK) + { + nerr("igc_initialize failed %d\n", ret); + return ret; + } + + /* Register the network device */ + + netdev->quota[NETPKT_TX] = IGC_TX_QUOTA; + netdev->quota[NETPKT_RX] = IGC_RX_QUOTA; + netdev->ops = &g_igc_ops; + + return netdev_lower_register(netdev, NET_LL_ETHERNET); + +errout: + kmm_free(priv->tx); + kmm_free(priv->rx); +#ifdef CONFIG_NET_MCASTGROUP + kmm_free(priv->mta); +#endif + kmm_free(priv); + return ret; +} + +/***************************************************************************** + * Public Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: pci_igc_init + * + * Description: + * Register a pci driver + * + *****************************************************************************/ + +int pci_igc_init(void) +{ + return pci_register_driver(&g_pci_igc_drv); +} diff --git a/drivers/net/igc.h b/drivers/net/igc.h new file mode 100644 index 0000000000..49dd237f49 --- /dev/null +++ b/drivers/net/igc.h @@ -0,0 +1,517 @@ +/***************************************************************************** + * drivers/net/igc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __DRIVERS_NET_IGC_H +#define __DRIVERS_NET_IGC_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* General registers */ + +#define IGC_CTRL (0x0000) /* Device Control Register */ +#define IGC_STATUS (0x0008) /* Device Status Register */ +#define IGC_CTRLEXT (0x0018) /* Extended Device Control Register */ +#define IGC_MDIC (0x0020) /* MDI Control Register */ +#define IGC_FCAL (0x0028) /* Flow Control Address Low */ +#define IGC_FCAH (0x002c) /* Flow Control Address High */ +#define IGC_FCT (0x0030) /* Flow Control Type */ +#define IGC_CONNSW (0x0034) /* Copper/Fiber Switch Control */ +#define IGC_VET (0x0038) /* VLAN Ether Type */ +#define IGC_FCTTV (0x0170) /* Flow Control Transmit Timer Value */ +#define IGC_LEDCTL (0x0e00) /* LED Control */ +#define IGC_MDICNFG (0x0e04) /* MDC/MDIO Configuration Register */ +#define IGC_I2CCM (0x1028) /* SFP I2C Command */ +#define IGC_I2CPARAMS (0x102c) /* SFP I2C Parameter */ +#define IGC_WDSTP (0x1040) /* Watchdog Setup Register */ +#define IGC_WDSWSTS (0x1044) /* Watchdog Software */ +#define IGC_FRTIMER (0x1048) /* Free Running Timer */ +#define IGC_TCPTIMER (0x104c) /* TCP Timer */ +#define IGC_SWSM (0x5b50) /* Software Semaphore Register */ +#define IGC_FWSM (0x5b54) /* Firmware Semaphore Register */ +#define IGC_SWFWSYNC (0x5b5c) /* Software-Firmware Synchronization */ +#define IGC_IPCNFG (0x0e38) /* Internal PHY Configuration */ +#define IGC_PHMP (0x0e14) /* PHY Power Management */ + +/* NVM-Security Registers */ + +#define IGC_EEC (0x12010) /* EEPROM/FLASH Control Register */ +#define IGC_EERD (0x12014) /* EEPROM Read Register */ +#define IGC_EEWR (0x12018) /* EEPROM-Mode Write Register */ +#define IGC_FLA (0x1201c) /* Flash Access Register */ +#define IGC_FLASECU (0x12114) /* Flash Security Register */ + +/* Interrupt registers */ + +#define IGC_ICR (0x1500) /* Interrupt Cause Read */ +#define IGC_ICS (0x1504) /* Interrupt Cause Set */ +#define IGC_IMS (0x1508) /* Interrupt Mask Set */ +#define IGC_IMC (0x150c) /* Interrupt Mask Clear */ +#define IGC_IAM (0x1510) /* Interrupt Acknowledge Auto–Mask */ +#define IGC_EICS (0x1520) /* Extended Interrupt Cause Set */ +#define IGC_EIMS (0x1524) /* Extended Interrupt Mask Set/Read */ +#define IGC_EIMC (0x1528) /* Extended Interrupt Mask Clear */ +#define IGC_EIAC (0x152c) /* Extended Interrupt Auto Clear */ +#define IGC_EIAM (0x1530) /* Extended Interrupt Auto Mask */ +#define IGC_EICR (0x1580) /* Extended Interrupt Cause Read */ +#define IGC_IVAR0 (0x1700) /* Interrupt Vector Allocation Registers */ +#define IGC_IVARMSC (0x1740) /* Interrupt Vector Allocation Registers - MISC */ +#define IGC_EITR0 (0x1680) /* Extended Interrupt Throttling Rate 0 - 24 */ +#define IGC_GPIE (0x1514) /* General Purpose Interrupt Enable */ +#define IGC_PBACL (0x5b68) /* MSI-X PBA Clear */ +#define IGC_PICAUSE (0x5b88) /* PCIe Interrupt Cause */ +#define IGC_PIENA (0x5b8c) /* PCIe Interrupt Enable */ + +/* Receive registers */ + +#define IGC_RCTL (0x0100) /* Receive Control */ +#define IGC_PSRCTL (0x2170) /* Packet Split Receive Control Register */ +#define IGC_FCRTL0 (0x2160) /* Flow Control Receive Threshold Low */ +#define IGC_FCRTH0 (0x2168) /* Flow Control Receive Threshold High */ +#define IGC_RXPBSIZE (0x2404) /* Rx Packet Buffer Size */ +#define IGC_FCRTV (0x2460) /* Flow Control Refresh Threshold Value */ +#define IGC_RDBAL0 (0xc000) /* Tx Descriptor Base Address Low */ +#define IGC_RDBAH0 (0xc004) /* Rx Descriptor Base Address High */ +#define IGC_RDLEN0 (0xc008) /* Rx Descriptor Length */ +#define IGC_SRRCTL0 (0xc00c) /* Split and Replication Receive Control Register Queue */ +#define IGC_RDH0 (0xc010) /* Rx Descriptor Head */ +#define IGC_RDT0 (0xc018) /* Rx Descriptor Tail */ +#define IGC_RXDCTL0 (0xc028) /* Receive Descriptor Control Queue */ +#define IGC_RXCTL0 (0xc014) /* Receive Queue DCA CTRL Register */ +#define IGC_RXCSUM (0x5000) /* Receive Checksum Control */ +#define IGC_RLPML (0x5004) /* Receive Long packet maximal length */ +#define IGC_RFCTL (0x5008) /* Receive Filter Control Register */ +#define IGC_MTA (0x5200) /* Multicast Table Array (n) */ +#define IGC_RAL (0x5400) /* Receive Address Low */ +#define IGC_RAH (0x5404) /* Receive Address Low */ +#define IGC_VLANPQF (0x55b0) /* VLAN Priority Queue Filter */ +#define IGC_PSRTYPE0 (0x5480) /* Packet Split Receive type (n) */ +#define IGC_VFTA0 (0x5600) /* VLAN Filter Table Array (n) */ +#define IGC_MRQC (0x5818) /* Multiple Receive Queues Command */ +#define IGC_RETA (0x5c00) /* Redirection Table */ +#define IGC_RSSRK (0x5c80) /* RSS Random Key Register */ + +/* Transmit registers */ + +#define IGC_TCTL (0x0400) /* Transmit Control */ +#define IGC_TCTLEXT (0x0404) /* Transmit Control Extended */ +#define IGC_TIPG (0x0410) /* Transmit IPG Register */ +#define IGC_RETXCTL (0x041c) /* Retry Buffer Control */ +#define IGC_TXPBSIZE (0x3404) /* Transmit Packet Buffer Size */ +#define IGC_DTXTCPFLGL (0x359c) /* DMA Tx TCP Flags Control Low */ +#define IGC_DTXTCPFLGH (0x35a0) /* DMA Tx TCP Flags Control High */ +#define IGC_DTXMXSZRQ (0x3540) /* DMA Tx Max Total Allow Size Requests */ +#define IGC_DTXMXPKTSZ (0x355c) /* DMA Tx Max Allowable Packet Size */ +#define IGC_DTXCTL (0x3590) /* DMA Tx Control */ +#define IGC_TDBAL0 (0xe000) /* Tx Descriptor Base Low */ +#define IGC_TDBAH0 (0xe004) /* Tx Descriptor Base High*/ +#define IGC_TDLEN0 (0xe008) /* Tx Descriptor Ring Length */ +#define IGC_TDH0 (0xe010) /* Tx Descriptor Head */ +#define IGC_TDT0 (0xe018) /* Tx Descriptor Tail */ +#define IGC_TXDCTL0 (0xe028) /* Transmit Descriptor Control Queue */ +#define IGC_TXCTL0 (0xe014) /* Tx DCA CTRL Register Queue */ +#define IGC_TDWBAL0 (0xe038) /* Transmit Descriptor WB Address Low Queue */ +#define IGC_TDWBAH0 (0xe03c) /* Transmit Descriptor WB Address High Queue */ + +/* Transmit Scheduling Registers */ + +#define IGC_TQAVHC (0x300c) /* Transmit Qav High Credits */ +#define IGC_TQAVCTRL (0x3570) /* Transmit Qav Control */ + +/* TODO: Filters */ + +/* TODO: Per Queue Statistics */ + +/* Statistic registers */ + +#define IGC_CRCERRS (0x04000) /* CRC Error Count */ +#define IGC_ALGNERRC (0x04004) /* Alignment Error Count */ +#define IGC_RXERRC (0x0400c) /* RX Error Count */ +#define IGC_MPC (0x04010) /* Missed Packets Count */ +#define IGC_SCC (0x04014) /* Single Collision Count */ +#define IGC_ECOL (0x04018) /* Excessive Collisions Count */ +#define IGC_MCC (0x0401c) /* Multiple Collision Count */ +#define IGC_LATECOL (0x04020) /* Late Collisions Count */ +#define IGC_COLC (0x04028) /* Collision Count */ +#define IGC_DC (0x04030) /* Defer Count */ +#define IGC_TNCRS (0x04034) /* Transmit with No CRS */ +#define IGC_CEXTERR (0x0403c) /* Carrier Extension Error Count */ +#define IGC_RLEC (0x04040) /* Receive Length Error Count */ +#define IGC_XONRXC (0x04048) /* XON Received Count */ +#define IGC_XONTXC (0x0404c) /* XON Transmitted Count */ +#define IGC_XOFFRXC (0x04050) /* XOFF Received Count */ +#define IGC_XOFFTXC (0x04054) /* XOFF Transmitted Count */ +#define IGC_FCRUC (0x04058) /* FC Received Unsupported Count */ +#define IGC_PRC64 (0x0405c) /* Packets Received [64 Bytes] Count */ +#define IGC_PRC127 (0x04060) /* Packets Received [65–127 Bytes] Count */ +#define IGC_PRC255 (0x04064) /* Packets Received [128–255 Bytes] */ +#define IGC_PRC511 (0x04068) /* Packets Received [256–511 Bytes] */ +#define IGC_PRC1023 (0x0406c) /* Packets Received [512–1023 Bytes] */ +#define IGC_PRC1522 (0x04070) /* Packets Received [1024 to Max Bytes] */ +#define IGC_GPRC (0x04074) /* Good Packets Received Count */ +#define IGC_BPRC (0x04078) /* Broadcast Packets Received Count */ +#define IGC_MPRC (0x0407c) /* Multicast Packets Received Count */ +#define IGC_GPTC (0x04080) /* Good Packets Transmitted Count */ +#define IGC_GORCL (0x04088) /* Good Octets Received Count Low */ +#define IGC_GORCH (0x0408c) /* Good Octets Received Count High */ +#define IGC_GOTCL (0x04090) /* Good Octets Transmitted Count Low */ +#define IGC_GOTCH (0x04094) /* Good Octets Transmitted Count High */ +#define IGC_RNBC (0x040a0) /* Receive No Buffers Count */ +#define IGC_RUC (0x040a4) /* Receive Undersize Count */ +#define IGC_RFC (0x040a8) /* Receive Fragment Count */ +#define IGC_ROC (0x040ac) /* Receive Oversize Count */ +#define IGC_RJC (0x040b0) /* Receive Jabber Count */ +#define IGC_MNGPRC (0x040B4) /* Management Packets Received Count */ +#define IGC_MPDC (0x040B8) /* Management Packets Dropped Count */ +#define IGC_MPTC (0x040BC) /* Management Packets Transmitted Count */ +#define IGC_TORL (0x040C0) /* Total Octets Received */ +#define IGC_TORH (0x040C4) /* Total Octets Received */ +#define IGC_TOT (0x040C8) /* Total Octets Transmitted */ +#define IGC_TPR (0x040D0) /* Total Packets Received */ +#define IGC_TPT (0x040D4) /* Total Packets Transmitted */ +#define IGC_PTC64 (0x040D8) /* Packets Transmitted [64 Bytes] Count */ +#define IGC_PTC127 (0x040DC) /* Packets Transmitted [65–127 Bytes] Count */ +#define IGC_PTC255 (0x040E0) /* Packets Transmitted [128–255 Bytes] Count */ +#define IGC_PTC511 (0x040E4) /* Packets Transmitted [256–511 Bytes] Count */ +#define IGC_PTC1023 (0x040E8) /* Packets Transmitted [512–1023 Bytes] Count */ +#define IGC_PTC1522 (0x040EC) /* Packets Transmitted [Greater than 1024 Bytes] Count */ +#define IGC_MCPTC (0x040F0) /* Multicast Packets Transmitted Count */ +#define IGC_BPTC (0x040F4) /* Broadcast Packets Transmitted Count */ +#define IGC_TSCTC (0x040F8) /* TCP Segmentation Context Transmitted Count */ +#define IGC_TSCTFC (0x040FC) /* TCP Segmentation Context Transmit Fail Count */ +#define IGC_IAC (0x04100) /* Interrupt Assertion Count */ +#define IGC_RPTHC (0x04104) /* Rx Packets to Host Count */ +#define IGC_TLPIC (0x04148) /* EEE Tx LPI Count */ +#define IGC_RLPIC (0x0414c) /* EEE Rx LPI Count */ +#define IGC_DBGC1 (0x04108) /* Debug counter 1 */ +#define IGC_DBGC2 (0x0410c) /* Debug counter 2 */ +#define IGC_DBGC3 (0x04110) /* Debug counter 3 */ +#define IGC_DBGC4 (0x0411c) /* Debug counter 4 */ +#define IGC_HGPTC (0x04118) /* Host Good Packets Transmitted Count */ +#define IGC_RXDMTC (0x04120) /* Rx Descriptor Minimum Threshold Count */ +#define IGC_HGORCL (0x04128) /* Host Good Octets Received Count (Lo) */ +#define IGC_HGORCH (0x0412c) /* Host Good Octets Received Count (Hi) */ +#define IGC_HGOTCL (0x04130) /* Host Good Octets Transmitted Count (Lo) */ +#define IGC_HGOTCH (0x04134) /* Host Good Octets Transmitted Count (Hi) */ +#define IGC_LENERRS (0x04138) /* Length Errors Count Register */ + +/* Wake Up and Proxying */ + +#define IGC_WUC (0x5800) /* Wake Up Control Register */ +#define IGC_WUFC (0x5808) /* Wake Up Filter Control Register */ +#define IGC_WUS (0x5810) /* Wake Up Status Register */ +#define IGC_MFUTP01 (0x5828) /* Management Flex UDP/TCP Ports 0/1 */ +#define IGC_MFUTP23 (0x5830) /* Management Flex UDP/TCP Port 2/3 */ +#define IGC_IPAV (0x5838) /* IP Address Valid */ + +/* Management Register */ + +#define IGC_MANC (0x5820) /* Management Control */ +#define IGC_MNGONLY (0x5864) /* Management Only Traffic Register */ + +/* TODO: Host Slave Interface */ + +/* TODO: PCIe */ + +/* TODO: Memory Error Detection */ + +/* TODO: Power Management Registers */ + +/* TODO: Time Sync */ + +/* TODO: Time Sync Interrupt Registers */ + +/* TODO: Time Sync QAV Statistics */ + +/* Device Control Register */ + +#define IGC_CTRL_FD (1 << 0) /* Bit 0: Full-Duplex */ + /* Bit 1: Reserved */ +#define IGC_CTRL_GIOMDIS (1 << 2) /* Bit 2: Link Reset */ + /* Bits 3-5: Reserved */ +#define IGC_CTRL_SLU (1 << 6) /* Bit 6: Set Link Up */ + /* Bits 7-15: Reserved */ +#define IGC_CTRL_SDP0GPIEN (1 << 16) /* Bit 16: General Purpose Interrupt Detection Enable for SDP0 */ +#define IGC_CTRL_SDP1GPIEN (1 << 17) /* Bit 17: General Purpose Interrupt Detection Enable for SDP1 */ +#define IGC_CTRL_SDP0DATA (1 << 18) /* Bit 18: SDP0 Data Value */ +#define IGC_CTRL_SDP1DATA (1 << 19) /* Bit 19: SDP1 Data Value */ + +#define IGC_CTRL_ADVD3WUC (1 << 20) /* Bit 20: D3Cold Wakeup Capability Advertisement Enable */ +#define IGC_CTRL_PWRMGMT (1 << 21) /* Bit 21: PHY Power-Management Enable */ +#define IGC_CTRL_SDP0_IODIR (1 << 22) /* Bit 22: SDP0 Pin Directionality */ +#define IGC_CTRL_SDP1_IODIR (1 << 23) /* Bit 23: SDP1 Pin Directionality */ + /* Bits 24-26: Reserved */ +#define IGC_CTRL_RFCE (1 << 27) /* Bit 27: Receive Flow Control Enable */ +#define IGC_CTRL_TFCE (1 << 28) /* Bit 28: Transmit Flow Control Enable */ +#define IGC_CTRL_DEVRST (1 << 29) /* Bit 29: Device Reset */ +#define IGC_CTRL_VME (1 << 30) /* Bit 30: VLAN Mode Enable */ +#define IGC_CTRL_PHYRST (1 << 31) /* Bit 31: PHY Reset */ + +/* Device Status Regiuster */ + +#define IGC_STATUS_FD (1 << 0) /* Bit 0: Full Duplex */ +#define IGC_STATUS_LU (1 << 1) /* Bit 1: Link Up */ + /* Bits 2-3: Reserved */ +#define IGC_STATUS_TXOFF (1 << 4) /* Bit 4: Transmission Paused */ + /* Bit 5: Reserved */ +#define IGC_STATUS_SPEED_SHFIT (5) /* Bits 6-7: Link speed setting */ + /* Bits 8-9: Reserved */ +#define IGC_STATUS_PHYRA (10) /* Bit 10: PHY Reset Asserted */ + /* Bits 11-18: Reserved */ +#define IGC_STATUS_GIOM (19) /* Bit 19: GIO Master Disable bit state */ +#define IGC_STATUS_DEVRSTSET (20) /* Bit 20: Device Reset Set */ +#define IGC_STATUS_RST_DONE (21) /* Bit 21: RST_DONE */ +#define IGC_STATUS_SPEED2P5 (22) /* Bit 22: Link Speed Indication for 2.5Gb/s */ + /* Bits 23-30: Reserved */ +#define IGC_STATUS_LPIIGNORE (31) /* Bit 31: Enable GTX clock out during LPI */ + /* Bit 31: Reserved */ + +/* Receive Address High */ + +#define IGC_RAH_RAH_MASK (0xffff) /* Bits 0-15: Receive address High */ +#define IGC_RAH_ASEL (16) /* Bits 16-17 Address Select */ +#define IGC_RAH_QSEL (18) /* Bits 18-19 Address Select */ + /* Bits 20-27: Reserved */ +#define IGC_RAH_QSELEN (1 << 28) /* Bit 28: Queue Select Enable */ + /* Bits 29-30: Reserved */ +#define IGC_RAH_AV (1 << 31) /* Bit 31: Address Valid */ + +/* Transmit Control */ + + /* Bit 0: Reserved */ +#define IGC_TCTL_EN (1 << 1) /* Bit 1: Transmit Enable */ + /* Bit 2: Reserved */ +#define IGC_TCTL_PSP (1 << 3) /* Bit 3: Pad Short Packets */ +#define IGC_TCTL_CT_SHIFT (4) /* Bits 4-11: Collision Threshold */ +#define IGC_TCTL_COLD_SHIFT (12) /* Bits 12-21: Collision Distance (BST) */ +#define IGC_TCTL_SWXOFF (1 << 22) /* Bit 22: Software XOFF Transmission */ + /* Bit 23: Reserved */ +#define IGC_TCTL_RTLC (1 << 24) /* Bit 24: Re-transmit on Late Collision */ + /* Bits 25-32: Reserved */ + +/* Transmit Descriptor Control */ + +#define IGC_TXDCTL_PTHRESH_SHIFT (0) /* Bits 0-5: Prefetch Threshold */ + /* Bits 6-7: Reserved */ +#define IGC_TXDCTL_HTHRESH_SHIFT (8) /* Bits 8-13: Host Threshold */ + /* Bits 14-15: Reserved */ +#define IGC_TXDCTL_WTHRESH_SHIFT (16) /* Bits 16-21: Write-Back Threshold */ + /* Bits 21-24: Reserved */ +#define IGC_TXDCTL_ENABLE (1 << 25) /* Bit 25: Transmit Queue Enable */ +#define IGC_TXDCTL_SWFLSH (1 << 26) /* Bit 26: Transmit Software Flush */ +#define IGC_TXDCTL_PRIORITY (1 << 27) /* Bit 27: Transmit Queue Priority */ +#define IGC_TXDCTL_HWBTHRESH (28) /* Bits 28-31: Transmit Head Write-back Threshold */ + +/* Tx Descriptor Ring Length */ + +/* Receive Control */ + + /* Bit 0: Reserved */ +#define IGC_RCTL_EN (1 << 1) /* Bit 1: Receiver Enable */ +#define IGC_RCTL_SBP (1 << 2) /* Bit 2: Store Bad Packets */ +#define IGC_RCTL_UPE (1 << 3) /* Bit 3: Unicast Promiscuous Enabled */ +#define IGC_RCTL_MPE (1 << 4) /* Bit 4: Multicast Promiscuous Enabled */ +#define IGC_RCTL_LPE (1 << 5) /* Bit 5: Long Packet Reception Enable */ +#define IGC_RCTL_LBM_SHIFT (6) /* Bits 6-7: Loopback mode */ +#define IGC_RCTL_HSEL_SHIFT (8) /* Bits 8-9: Hash Select for the Multicast Table Array (MTA) */ + /* Bits 10-11: Reserved */ +#define IGC_RCTL_MO_SHIFT (12) /* Bits 12-13: Multicast Offset */ + /* Bit 14: Reserved */ +#define IGC_RCTL_BAM (1 << 15) /* Bit 15: Broadcast Accept Mode */ +#define IGC_RCTL_BSIZE_SHIFT (16) /* Bits 16-17: Receive Buffer Size */ +# define IGC_RCTL_BSIZE_2048 (0 << 16) /* 00b: 2048 bytes */ +# define IGC_RCTL_BSIZE_1024 (1 << 16) /* 01b: 1024 bytes */ +# define IGC_RCTL_BSIZE_512 (2 << 16) /* 10b: 512 bytes */ +# define IGC_RCTL_BSIZE_256 (3 << 16) /* 11b: 256 bytes */ +#define IGC_RCTL_VFE (1 << 18) /* Bit 18: VLAN Filter Enable */ +#define IGC_RCTL_CFIEN (1 << 18) /* Bit 19: Canonical Form Indicator Enable */ +#define IGC_RCTL_CFI (1 << 20) /* Bit 20: Canonical Form Indicator bit value */ +#define IGC_RCTL_PSP (1 << 21) /* Bit 21: Pad Small Receive Packets */ +#define IGC_RCTL_DPF (1 << 22) /* Bit 22: Discard Pause Frames */ +#define IGC_RCTL_PMCF (1 << 23) /* Bit 23: Pass MAC Control Frames */ + /* Bits 24-25: Reserved */ +#define IGC_RCTL_SECRC (1 << 26) /* Bit 26: Strip Ethernet CRC from incoming packet */ + /* Bits 27-31: Reserved */ + +/* Receive Descriptor Control */ + +#define IGC_RXDCTL_PTHRESH_SHIFT (0) /* Bits 0-4: Prefetch Threshold */ + /* Bits 5-7: Reserved */ +#define IGC_RXDCTL_HTHRESH_SHIFT (8) /* Bits 8-12: Host Threshold */ + /* Bits 13-15: Reserved */ +#define IGC_RXDCTL_WTHRESH_SHIFT (16) /* Bits 16-20: Write-Back Threshold */ + /* Bits 21-24: Reserved */ +#define IGC_RXDCTL_ENABLE (1 << 25) /* Bit 25: Receive Queue Enable */ +#define IGC_RXDCTL_SWFLUSH (1 << 26) /* Bit 26: Receive Software Flush */ + /* Bits 27-31: Reserved */ + +/* Interrupt Cause */ + +#define IGC_IC_TXDW (1 << 0) /* Bit 0: Transmit Descriptor Written Back */ + /* Bit 1: Reserved */ +#define IGC_IC_LSC (1 << 2) /* Bit 2: Link Status Change */ + /* Bit 3: Reserved */ +#define IGC_IC_RXDMT0 (1 << 4) /* Bit 4: Receive Descriptor Minimum Threshold Reached */ + /* Bit 5: Reserved */ +#define IGC_IC_RXMISS (1 << 6) /* Bit 6: Receiver Miss Interrupt */ +#define IGC_IC_RXDW (1 << 7) /* Bit 7: Receiver Descriptor Write Back interrupt */ + /* Bit 8: Reserved */ +#define IGC_IC_MDAC (1 << 9) /* Bit 9: MDI/O Access Complete */ +#define IGC_IC_GPHY (1 << 10) /* Bit 10: Internal PHY interrupt */ + /* Bits 11-15: General Purpose Interrupts */ +#define IGC_IC_PTRAP (1 << 15) /* Bit 15: Probe trap interrupt */ + /* Bits 16-17: Reserved */ +#define IGC_IC_MNG (1 << 18) /* Bit 18: Management Event interrupt. */ +#define IGC_IC_TIMESYNC (1 << 19) /* Bit 19: Time_Sync interrupt */ + /* Bits 20-21: Reserved */ +#define IGC_IC_FER (1 << 22) /* Bit 22: Fatal Error interrupt */ + /* Bit 23: Reserved */ +#define IGC_IC_PCIEXCEPT (1 << 24) /* Bit 24: PCI Exception interrupt */ +#define IGC_IC_SCE (1 << 25) /* Bit 25: DMA Coalescing Clock Control Event */ +#define IGC_IC_SWD (1 << 26) /* Bit 26: Software Watchdog interrupt */ + /* Bit 27: Reserved */ +#define IGC_IC_MDDET (1 << 28) /* Bit 28: Detected Malicious driver behavior Interrupt */ +#define IGC_IC_TCPTIMER (1 << 29) /* Bit 29: TCP timer interrupt */ +#define IGC_IC_DRSTA (1 << 30) /* Bit 30: Device Reset Asserted interrupt */ + /* Bit 31: Reserved */ + +/* Extended Interrupt Mask for Non-MSI-X Mode */ + +#define IGC_EIMS_NOMSIX_RXTX0 (1 << 0) +#define IGC_EIMS_NOMSIX_RXTX1 (1 << 1) +#define IGC_EIMS_NOMSIX_RXTX2 (1 << 2) +#define IGC_EIMS_NOMSIX_RXTX3 (1 << 3) +#define IGC_EIMS_NOMSIX_TCPTIM (1 << 30) +#define IGC_EIMS_NOMSIX_OTHER (1 << 31) + +/* Extended Interrupt Mask for MSI-X Mode */ + +#define IGC_EIMS_MSIX_0 (1 << 0) +#define IGC_EIMS_MSIX_1 (1 << 1) +#define IGC_EIMS_MSIX_2 (1 << 2) +#define IGC_EIMS_MSIX_3 (1 << 3) +#define IGC_EIMS_MSIX_4 (1 << 4) + +/* Interrupt Vector Allocation Registers */ + +#define IGC_IVAR0_RXQ0_SHIFT (0) /* Bits 0-4: MSI-X vector assigned to RxQ0 */ +#define IGC_IVAR0_RXQ0_VAL (1 << 7) /* Bit 7: Valid bit for RxQ0 */ +#define IGC_IVAR0_TXQ0_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to TxQ0 */ +#define IGC_IVAR0_TXQ0_VAL (1 << 7) /* Bit 7: Valid bit for TxQ0 */ + +/* Interrupt Vector Allocation Registers - Misc */ + +#define IGC_IVARMSC_TCPTIM (0) /* Bits 0-5: MSI-X vectorassigned to TCP timer interrupt */ + /* Bits 5-6: Reserved */ +#define IGC_IVARMSC_TCPTIM_VAL (1 << 7) /* Bit 7: Enable bit for TCP timer interrupt */ +#define IGC_IVARMSC_OTHER_SHIFT (8) /* Bits 8-12: MSI-X vector assigned to Ohter Cause */ + /* Bits 13-14: Reserved */ +#define IGC_IVARMSC_OTHER_VAL (1 << 15) /* Bit 15: Enable bit for Ohter Cause */ + /* Bits 20-30: Reserved */ + +/* General Purpose Interrupt Enable */ + +#define IGC_GPIE_NSICR (1 << 0) /* Bit 0: Non Selective Interrupt Clear on Read */ + /* Bits 1-3: Reserved */ +#define IGC_GPIE_MSIX (1 << 4) /* Bit 4: MSI-X mode */ + /* Bits 5-6: Reserved */ +#define IGC_GPIE_LLINTERVAL_SHIFT (7) /* Bits 7-11: Low Latency Credits Increment Rate */ + /* Bits 12-29: Reserved */ +#define IGC_GPIE_EIAME (1 << 30) /* Bit 30: Extended Interrupt Auto Mask Enable */ +#define IGC_GPIE_PBASUPPORT (1 << 31) /* Bit 31: PBA Support */ + +/* Transmit Descriptor Command Field */ + +#define IGC_TDESC_CMD_EOP (1 << 0) /* Bit 0: End Of Packet */ +#define IGC_TDESC_CMD_IFCS (1 << 1) /* Bit 1: Insert FCS */ +#define IGC_TDESC_CMD_IC (1 << 2) /* Bit 2: Insert Checksum */ +#define IGC_TDESC_CMD_RS (1 << 3) /* Bit 3: Report Status */ +#define IGC_TDESC_CMD_DEXT (1 << 5) /* Bit 5: Extension (0b for legacy mode) */ +#define IGC_TDESC_CMD_VLE (1 << 6) /* Bit 6: VLAN Packet Enable */ + +/* Transmit Descriptor Status Field */ + +#define IGC_TDESC_STATUS_DD (1 << 0) /* Bit 0: Descriptor Done */ + +/* Transmit Descriptor Special Field */ + +#define IGC_TDESC_SPEC_VLAN_SHIFT (0) /* Bits 0-11: VLAN Identifier */ +#define IGC_TDESC_SPEC_CFI (1 << 12) /* Bit 12: Canonical Form Indicator */ +#define IGC_TDESC_SPEC_PRI_SHIFT (13) /* Bits 13-15: User Priority */ + +/* Receive Descriptor Status Field */ + +#define IGC_RDESC_STATUS_DD (1 << 0) /* Bit 0: Descriptor Done */ +#define IGC_RDESC_STATUS_EOP (1 << 1) /* Bit 1: End of Packet */ +#define IGC_RDESC_STATUS_VP (1 << 3) /* Bit 3: Packet is 802.1Q (matched VET) */ +#define IGC_RDESC_STATUS_UDPCS (1 << 4) /* Bit 4: UDP checksum or IP payload checksum calculated on packet */ +#define IGC_RDESC_STATUS_L4CS (1 << 5) /* Bit 5: L4 (UDP or TCP) checksum calculated on packet */ +#define IGC_RDESC_STATUS_IPCS (1 << 6) /* Bit 6: IP Checksum Calculated on Packet */ +#define IGC_RDESC_STATUS_PIF (1 << 7) /* Bit 7: Passed in-exact filter */ + +/* Receive Descriptor Errors Field */ + +#define IGC_RDESC_ERRORS_L4E (1 << 5) /* Bit 5: TCP/UDP Checksum Error */ +#define IGC_RDESC_ERRORS_IPE (1 << 6) /* Bit 6: IP Checksum Error */ +#define IGC_RDESC_ERRORS_RXE (1 << 7) /* Bit 7: RX Data Error */ + +/* Receive Descriptor Special Field */ + +#define IGC_RDESC_SPEC_VLAN_SHIFT (0) /* Bits 0-11: VLAN Identifier */ +#define IGC_RDESC_SPEC_CFI (1 << 12) /* Bit 12: Canonical Form Indicator */ +#define IGC_RDESC_SPEC_PRI_SHIFT (13) /* Bits 13-15: User Priority */ + +/***************************************************************************** + * Public Types + *****************************************************************************/ + +/* Legacy TX descriptor */ + +begin_packed_struct struct igc_tx_leg_s +{ + uint64_t addr; + uint16_t len; + uint8_t cso; + uint8_t cmd; + uint8_t status; + uint8_t css; + uint16_t special; +} end_packed_struct; + +/* Legacy RX descriptor */ + +begin_packed_struct struct igc_rx_leg_s +{ + uint64_t addr; + uint16_t len; + uint16_t checksum; + uint8_t status; + uint8_t errors; + uint16_t special; +} end_packed_struct; + +#endif /* __DRIVERS_NET_IGC_H */ diff --git a/drivers/pci/pci_drivers.c b/drivers/pci/pci_drivers.c index e839515384..a7f56b8f92 100644 --- a/drivers/pci/pci_drivers.c +++ b/drivers/pci/pci_drivers.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "pci_drivers.h" @@ -125,6 +126,16 @@ int pci_register_drivers(void) } #endif + /* Initialization igc driver */ + +#ifdef CONFIG_NET_IGC + ret = pci_igc_init(); + if (ret < 0) + { + pcierr("pci_igc_init failed, ret=%d\n", ret); + } +#endif + UNUSED(ret); return ret; } diff --git a/include/nuttx/net/igc.h b/include/nuttx/net/igc.h new file mode 100644 index 0000000000..47f14cec8c --- /dev/null +++ b/include/nuttx/net/igc.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * include/nuttx/net/igc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_NET_IGC_H +#define __INCLUDE_NUTTX_NET_IGC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: pci_igc_init + * + * Description: + * Register a pci driver + * + ****************************************************************************/ + +int pci_igc_init(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_NET_IGC_H */