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Make stm32_pwr_enablebkp thread safe

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Max Neklyudov 2016-08-09 07:36:13 -06:00 committed by Gregory Nutt
parent 8499f42bf9
commit 1e3ccbac12
3 changed files with 32 additions and 32 deletions
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23
arch/arm/src/stm32/stm32_lse.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_lse.c
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* Redistribution and use in source and binary forms, with or without
@ -45,18 +45,6 @@
#include "stm32_rcc.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@ -74,14 +62,12 @@
void stm32_rcc_enablelse(void)
{
bool bkpenabled;
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
bkpenabled = stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@ -115,8 +101,5 @@ void stm32_rcc_enablelse(void)
/* Disable backup domain access if it was disabled on entry */
if (!bkpenabled)
{
(void)stm32_pwr_enablebkp(false);
}
stm32_pwr_enablebkp(false);
}

39
arch/arm/src/stm32/stm32_pwr.c
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@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
*
@ -40,21 +40,19 @@
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_arch.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32_PWR)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
@ -93,38 +91,57 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
*
************************************************************************************/
bool stm32_pwr_enablebkp(bool writable)
void stm32_pwr_enablebkp(bool writable)
{
static uint32_t writable_counter = 0;
irqstate_t flags;
uint16_t regval;
bool waswritable;
bool wait = false;
flags = enter_critical_section();
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
waswritable = ((regval & PWR_CR_DBP) != 0);
if (writable)
{
writable_counter++;
}
else if (writable_counter > 0)
{
writable_counter--;
}
/* Enable or disable the ability to write */
if (waswritable && !writable)
if (waswritable && writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
else if (!waswritable && writable)
else if (!waswritable && writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
wait = true;
}
leave_critical_section(flags);
if (wait)
{
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/************************************************************************************

2
arch/arm/src/stm32/stm32_pwr.h
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@ -81,7 +81,7 @@ extern "C"
*
************************************************************************************/
bool stm32_pwr_enablebkp(bool writable);
void stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg