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arch/arm/src/samd5e5: Correct some bad addresses in the memory map.

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This commit is contained in:
Gregory Nutt 2018-09-01 11:15:16 -06:00
parent e3d7fcf7ab
commit 1e4272a046
3 changed files with 20 additions and 17 deletions
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26
arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
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@ -68,12 +68,12 @@
/* NVM area */
#define SAM_NVM_CALIBAREA 0x00800080 /* NVM software calibration area */
#define SAM_NVM_USERPAGE 0x00804000 /* NVM user page (512b) */
#define SAM_NVM_SNWORD0 0x008061fc /* Serial number word 0 */
#define SAM_NVM_SNWORD1 0x00806010 /* Serial number word 1 */
#define SAM_NVM_SNWORD2 0x00806014 /* Serial number word 2 */
#define SAM_NVM_SNWORD3 0x00806018 /* Serial number word 3 */
#define SAM_NVM_CALIBAREA 0x00800080 /* NVM software calibration area */
#define SAM_NVM_USERPAGE 0x00804000 /* NVM user page (512b) */
#define SAM_NVM_SNWORD0 0x008061fc /* Serial number word 0 */
#define SAM_NVM_SNWORD1 0x00806010 /* Serial number word 1 */
#define SAM_NVM_SNWORD2 0x00806014 /* Serial number word 2 */
#define SAM_NVM_SNWORD3 0x00806018 /* Serial number word 3 */
/* AHB-APB Bridge A */
@ -106,14 +106,14 @@
/* Reserved */
#define SAM_EVSYS_BASE 0x4100e000 /* Event System */
/* Reserved */
#define SAM_SERCOM2_BASE 0x41001200 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x41001400 /* Serial Communication Interface 3 */
#define SAM_TCC0_BASE 0x41001600 /* Timer/Counter Control 0 */
#define SAM_TCC1_BASE 0x41001800 /* Timer/Counter Control 1 */
#define SAM_TC2_BASE 0x41001a00 /* Timer/Counter 2 */
#define SAM_TC3_BASE 0x41001c00 /* Timer/Counter 3 */
#define SAM_SERCOM2_BASE 0x41012000 /* Serial Communication Interface 2 */
#define SAM_SERCOM3_BASE 0x41014000 /* Serial Communication Interface 3 */
#define SAM_TCC0_BASE 0x41016000 /* Timer/Counter Control 0 */
#define SAM_TCC1_BASE 0x41018000 /* Timer/Counter Control 1 */
#define SAM_TC2_BASE 0x4101a000 /* Timer/Counter 2 */
#define SAM_TC3_BASE 0x4101c000 /* Timer/Counter 3 */
/* Reserved */
#define SAM_RAMECC_BASE 0x41002000 /* RAM Error Correction Code (RAMECC) */
#define SAM_RAMECC_BASE 0x41020000 /* RAM Error Correction Code (RAMECC) */
/* Reserved */
/* AHB-APB Bridge C */

2
arch/arm/src/samd5e5/sam_lowputc.c
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@ -240,6 +240,8 @@ sam_usart_configure(const struct sam_usart_config_s * const config)
sam_wait_synchronization(config);
ctrla |= USART_CTRLA_ENABLE;
putreg32(ctrla, config->base + SAM_USART_CTRLA_OFFSET);
return OK;
}
#endif

9
configs/metro-m4/README.txt
View File

@ -98,10 +98,11 @@ STATUS
-#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
+#define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
This gets past all clock and USART configuration, but then there is a
hang in sam_lowputc(). All of the USART3 registers are zero so the wait
for data register empty (DRE) causes the hang. It appears that the
SERCOM3 module is not properly enabled or not receiving clocking.
With that workaround, the port gets past all clock and USART
configuration and, in fact, completely through OS initialization and
aplication startup! The NSH shell runs and the NSH prompt is presented
on the serial console at the correct baud. Serial input, however, is
not received so there is still more to be done.
Unlocking FLASH
===============