diff --git a/arch/arm/src/armv7-a/arm_addrenv.c b/arch/arm/src/armv7-a/arm_addrenv.c
index 0fef2c3767..c10c67185d 100644
--- a/arch/arm/src/armv7-a/arm_addrenv.c
+++ b/arch/arm/src/armv7-a/arm_addrenv.c
@@ -714,7 +714,7 @@ int up_addrenv_coherent(const group_addrenv_t *addrenv)
 
   /* Invalidate I-Cache */
 
-  cp15_invalidate_icache();
+  up_invalidate_icache_all();
 
   /* Clean D-Cache in each region.
    * REVISIT:  Cause crashes when trying to clean unmapped memory.  In order
diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h
index 2ef9279fee..a69d456f1e 100644
--- a/arch/arm/src/armv7-a/cp15_cacheops.h
+++ b/arch/arm/src/armv7-a/cp15_cacheops.h
@@ -902,6 +902,23 @@ extern "C"
  * Public Function Prototypes
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: cp15_invalidate_icache
+ *
+ * Description:
+ *   Invalidate the instruction cache within the specified region.
+ *
+ * Input Parameters:
+ *   start - virtual start address of region
+ *   end   - virtual end address of region + 1
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cp15_invalidate_icache(uintptr_t start, uintptr_t end);
+
 /****************************************************************************
  * Name: cp15_dcache_op_level
  *
diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h
index 4130111803..adf58ac3b9 100644
--- a/arch/arm/src/armv7-r/cp15_cacheops.h
+++ b/arch/arm/src/armv7-r/cp15_cacheops.h
@@ -909,6 +909,23 @@ extern "C"
  * Public Function Prototypes
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: cp15_invalidate_icache
+ *
+ * Description:
+ *   Invalidate the instruction cache within the specified region.
+ *
+ * Input Parameters:
+ *   start - virtual start address of region
+ *   end   - virtual end address of region + 1
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cp15_invalidate_icache(uintptr_t start, uintptr_t end);
+
 /****************************************************************************
  * Name: cp15_dcache_op_level
  *
diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c
index 012ba68b80..430f13df22 100644
--- a/arch/arm/src/sama5/sam_irq.c
+++ b/arch/arm/src/sama5/sam_irq.c
@@ -504,7 +504,7 @@ void up_irqinitialize(void)
    */
 
   vectorsize = sam_vectorsize();
-  cp15_invalidate_icache();
+  cp15_invalidate_icache(0, vectorsize);
   cp15_invalidate_dcache(0, vectorsize);
   mmu_invalidate_region(0, vectorsize);
 
diff --git a/boards/arm/sama5/sama5d4-ek/src/dram_main.c b/boards/arm/sama5/sama5d4-ek/src/dram_main.c
index 1af64e2270..765dd711be 100644
--- a/boards/arm/sama5/sama5d4-ek/src/dram_main.c
+++ b/boards/arm/sama5/sama5d4-ek/src/dram_main.c
@@ -151,7 +151,7 @@ int dram_main(int argc, char *argv[])
 
   /* Invalidate caches and TLBs */
 
-  cp15_invalidate_icache();
+  cp15_invalidate_icache_all();
   cp15_invalidate_dcache_all();
   cp15_invalidate_tlbs();