arch/arm/src/imxrt/imxrt_flexcan.c: use SW control to check free MBs
CAN_ESR2 register was having problems of havng the correct values when the bus was busy (with 3 and more nods). The register bit fields were incorrectly indicating that there is no free MB and would not updated itself from this state which was causing the applications to freeze on write. This change relies only on a software control which should avoid the problems described above. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
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@ -470,9 +470,6 @@ static void imxrt_setfreeze(uint32_t base, uint32_t freeze);
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static uint32_t imxrt_waitmcr_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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static uint32_t imxrt_waitesr2_change(uint32_t base,
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uint32_t mask,
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uint32_t target_state);
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static struct mb_s *flexcan_get_mb(FAR struct imxrt_driver_s *priv,
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uint32_t mbi);
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@ -531,10 +528,10 @@ static void imxrt_reset(struct imxrt_driver_s *priv);
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static bool imxrt_txringfull(FAR struct imxrt_driver_s *priv)
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{
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uint32_t mbi = RXMBCOUNT;
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uint32_t mbi = RXMBCOUNT + 1;
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struct mb_s *mb;
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while (mbi < TXMBCOUNT)
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while (mbi < TOTALMBCOUNT)
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{
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mb = flexcan_get_mb(priv, mbi);
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if (mb->cs.code != CAN_TXMB_DATAORREMOTE)
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@ -583,18 +580,13 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
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int32_t timeout;
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#endif
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if ((getreg32(priv->base + IMXRT_CAN_ESR2_OFFSET) &
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(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
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(CAN_ESR2_IMB | CAN_ESR2_VPS))
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{
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mbi = ((getreg32(priv->base + IMXRT_CAN_ESR2_OFFSET) &
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CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT);
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}
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mbi = RXMBCOUNT + 1;
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mb_bit = 1 << mbi;
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while (mbi < TOTALMBCOUNT)
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{
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/* Check whether message buffer is not currently transmitting */
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struct mb_s *mb = flexcan_get_mb(priv, mbi);
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if (mb->cs.code != CAN_TXMB_DATAORREMOTE)
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{
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@ -771,11 +763,14 @@ static int imxrt_txpoll(struct net_driver_s *dev)
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{
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FAR struct imxrt_driver_s *priv =
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(FAR struct imxrt_driver_s *)dev->d_private;
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irqstate_t flags;
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/* If the polling resulted in data that should be sent out on the network,
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* the field d_len is set to a value > 0.
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*/
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flags = spin_lock_irqsave(NULL);
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if (priv->dev.d_len > 0)
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{
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if (!devif_loopback(&priv->dev))
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@ -790,15 +785,16 @@ static int imxrt_txpoll(struct net_driver_s *dev)
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* not, return a non-zero value to terminate the poll.
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*/
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if (!((getreg32(priv->base + IMXRT_CAN_ESR2_OFFSET) &
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(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
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(CAN_ESR2_IMB | CAN_ESR2_VPS)) || (imxrt_txringfull(priv)))
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{
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return -EBUSY;
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}
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if (imxrt_txringfull(priv))
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{
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spin_unlock_irqrestore(NULL, flags);
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return -EBUSY;
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}
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}
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}
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spin_unlock_irqrestore(NULL, flags);
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/* If zero is returned, the polling will continue until all connections
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* have been examined.
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*/
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@ -1268,26 +1264,6 @@ static uint32_t imxrt_waitfreezeack_change(uint32_t base,
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return imxrt_waitmcr_change(base, CAN_MCR_FRZACK, target_state);
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}
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static uint32_t imxrt_waitesr2_change(uint32_t base, uint32_t mask,
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uint32_t target_state)
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{
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const uint32_t timeout = 1000;
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uint32_t wait_ack;
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for (wait_ack = 0; wait_ack < timeout; wait_ack++)
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{
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uint32_t state = (getreg32(base + IMXRT_CAN_ESR2_OFFSET) & mask);
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if (state == target_state)
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{
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return true;
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}
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up_udelay(10);
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}
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return false;
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}
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static struct mb_s *flexcan_get_mb(FAR struct imxrt_driver_s *priv,
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uint32_t mbi)
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{
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@ -1401,9 +1377,7 @@ static void imxrt_txavail_work(FAR void *arg)
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* packet.
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*/
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if (imxrt_waitesr2_change(priv->base,
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(CAN_ESR2_IMB | CAN_ESR2_VPS),
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(CAN_ESR2_IMB | CAN_ESR2_VPS)))
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if (!imxrt_txringfull(priv))
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{
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/* No, there is space for another transfer. Poll the network for
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* new XMIT data.
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