From 1ecaa4e6723e1a12d1e2c9770329800e8a9f9571 Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Thu, 17 Nov 2022 17:10:59 -0300 Subject: [PATCH] xtensa/esp32s3: Configure the PMS peripheral for Protected Mode Signed-off-by: Gustavo Henrique Nihei --- arch/xtensa/Kconfig | 30 +- arch/xtensa/src/common/xtensa_macros.S | 4 +- arch/xtensa/src/common/xtensa_swint.c | 3 + arch/xtensa/src/common/xtensa_window_vector.S | 8 +- arch/xtensa/src/esp32/Kconfig | 3 +- arch/xtensa/src/esp32/Make.defs | 2 +- arch/xtensa/src/esp32/chip_macros.h | 4 +- arch/xtensa/src/esp32/esp32_window_hooks.S | 4 +- arch/xtensa/src/esp32s3/Kconfig | 6 + arch/xtensa/src/esp32s3/chip_macros.h | 185 +- .../xtensa/src/esp32s3/esp32s3_allocateheap.c | 12 +- arch/xtensa/src/esp32s3/esp32s3_irq.c | 7 +- arch/xtensa/src/esp32s3/esp32s3_userspace.c | 1629 +++- arch/xtensa/src/esp32s3/esp32s3_userspace.h | 20 + .../src/esp32s3/hardware/esp32s3_apb_ctrl.h | 1135 +++ .../src/esp32s3/hardware/esp32s3_sensitive.h | 8495 +++++++++++++++++ .../xtensa/src/esp32s3/hardware/esp32s3_soc.h | 10 + .../src/esp32s3/hardware/esp32s3_wcl_core.h | 1908 ++++ boards/xtensa/esp32s3/common/kernel/Makefile | 9 +- .../common/kernel/esp32s3_user_vectors.S | 304 + .../esp32s3/common/scripts/kernel-space.ld | 13 +- .../common/scripts/protected_memory.ld | 26 +- .../esp32s3/common/scripts/user-space.ld | 71 +- .../esp32s3-devkit/configs/knsh/defconfig | 5 +- 24 files changed, 13779 insertions(+), 114 deletions(-) create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h create mode 100644 boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index e288c01f8f..565b409fde 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -87,18 +87,18 @@ config ARCH_CHIP_ESP32S3 select ARCH_HAVE_BOOTLOADER select ARCH_HAVE_TESTSET select ARCH_VECNOTIRQ - select LIBC_ARCH_MEMCPY - select LIBC_ARCH_MEMCHR - select LIBC_ARCH_MEMCMP - select LIBC_ARCH_MEMMOVE - select LIBC_ARCH_MEMSET - select LIBC_ARCH_STRCHR - select LIBC_ARCH_STRCMP - select LIBC_ARCH_STRCPY - select LIBC_ARCH_STRLCPY - select LIBC_ARCH_STRNCPY - select LIBC_ARCH_STRLEN - select LIBC_ARCH_STRNLEN + select LIBC_ARCH_MEMCPY if BUILD_FLAT + select LIBC_ARCH_MEMCHR if BUILD_FLAT + select LIBC_ARCH_MEMCMP if BUILD_FLAT + select LIBC_ARCH_MEMMOVE if BUILD_FLAT + select LIBC_ARCH_MEMSET if BUILD_FLAT + select LIBC_ARCH_STRCHR if BUILD_FLAT + select LIBC_ARCH_STRCMP if BUILD_FLAT + select LIBC_ARCH_STRCPY if BUILD_FLAT + select LIBC_ARCH_STRLCPY if BUILD_FLAT + select LIBC_ARCH_STRNCPY if BUILD_FLAT + select LIBC_ARCH_STRLEN if BUILD_FLAT + select LIBC_ARCH_STRNLEN if BUILD_FLAT ---help--- ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz. Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz, @@ -129,7 +129,11 @@ config XTENSA_HAVE_DCACHE_LOCK bool default n -config XTENSA_HAVE_EXCEPTION_HOOKS +config XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS + bool + default n + +config XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS bool default n diff --git a/arch/xtensa/src/common/xtensa_macros.S b/arch/xtensa/src/common/xtensa_macros.S index 5519a60ad6..7b531dc131 100644 --- a/arch/xtensa/src/common/xtensa_macros.S +++ b/arch/xtensa/src/common/xtensa_macros.S @@ -179,7 +179,7 @@ rsr a0, EPC_1 + \level - 1 /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS /* Perform chip-specific exception entry operations */ exception_entry_hook \level sp a0 @@ -207,7 +207,7 @@ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_1 + \level - 1 -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS /* Perform chip-specific exception exit operations */ exception_exit_hook \level a2 a0 a1 diff --git a/arch/xtensa/src/common/xtensa_swint.c b/arch/xtensa/src/common/xtensa_swint.c index 90edfb5eed..1f56639ff6 100644 --- a/arch/xtensa/src/common/xtensa_swint.c +++ b/arch/xtensa/src/common/xtensa_swint.c @@ -54,6 +54,9 @@ static void xtensa_registerdump(const uintptr_t *regs) regs[REG_A8], regs[REG_A9], regs[REG_A10], regs[REG_A11], regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]); svcinfo(" PC: %08x PS: %08x\n", regs[REG_PC], regs[REG_PS]); +#ifdef CONFIG_BUILD_PROTECTED + svcinfo(" INT_CTX: %08x\n", regs[REG_INT_CTX]); +#endif } #endif diff --git a/arch/xtensa/src/common/xtensa_window_vector.S b/arch/xtensa/src/common/xtensa_window_vector.S index 997c203bea..ba43de5635 100644 --- a/arch/xtensa/src/common/xtensa_window_vector.S +++ b/arch/xtensa/src/common/xtensa_window_vector.S @@ -98,7 +98,7 @@ _window_overflow4: s32e a1, a5, -12 /* Save a1 to call[j+1]'s stack frame */ s32e a2, a5, -8 /* Save a2 to call[j+1]'s stack frame */ s32e a3, a5, -4 /* Save a3 to call[j+1]'s stack frame */ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS j _overflow4_exit_hook #else rfwo /* Rotates back to call[i] position */ @@ -125,7 +125,7 @@ _window_underflow4: l32e a1, a5, -12 /* Restore a1 from call[i+1]'s stack frame */ l32e a2, a5, -8 /* Restore a2 from call[i+1]'s stack frame */ l32e a3, a5, -4 /* Restore a3 from call[i+1]'s stack frame */ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS j _underflow4_exit_hook #else rfwu @@ -188,7 +188,7 @@ _window_overflow8: s32e a5, a0, -28 /* Save a5 to call[j]'s stack frame */ s32e a6, a0, -24 /* Save a6 to call[j]'s stack frame */ s32e a7, a0, -20 /* Save a7 to call[j]'s stack frame */ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS j _overflow8_exit_hook #else rfwo /* Rotates back to call[i] position */ @@ -221,7 +221,7 @@ _window_underflow8: l32e a5, a7, -28 /* Restore a5 from call[i]'s stack frame */ l32e a6, a7, -24 /* Restore a6 from call[i]'s stack frame */ l32e a7, a7, -20 /* Restore a7 from call[i]'s stack frame */ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS j _underflow8_exit_hook #else rfwu diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 8c3ac980d3..3abbc97d36 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -738,7 +738,8 @@ config ESP32_PID bool "PID Controller" default n select ARCH_USE_MPU - select XTENSA_HAVE_EXCEPTION_HOOKS if BUILD_PROTECTED + select XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS if BUILD_PROTECTED + select XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS if BUILD_PROTECTED depends on EXPERIMENTAL endmenu # ESP32 Peripheral Selection diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 776fbc0b49..67ac01c447 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -25,7 +25,7 @@ include common/Make.defs HEAD_CSRC = esp32_start.c esp32_wdt.c -ifeq ($(CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS),y) +ifeq ($(CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS),y) HEAD_ASRC += esp32_window_hooks.S endif diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h index b42c098121..2616070874 100644 --- a/arch/xtensa/src/esp32/chip_macros.h +++ b/arch/xtensa/src/esp32/chip_macros.h @@ -193,7 +193,7 @@ * ****************************************************************************/ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS .macro exception_entry_hook level reg_sp tmp /* Save PID information from interruptee when handling User (Level 1) and @@ -221,7 +221,7 @@ * ****************************************************************************/ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS .macro exception_exit_hook level reg_sp tmp1 tmp2 /* Configure the PID Controller for the new execution context before diff --git a/arch/xtensa/src/esp32/esp32_window_hooks.S b/arch/xtensa/src/esp32/esp32_window_hooks.S index bebb85cfe1..3e0f88b9d4 100644 --- a/arch/xtensa/src/esp32/esp32_window_hooks.S +++ b/arch/xtensa/src/esp32/esp32_window_hooks.S @@ -32,7 +32,7 @@ * Public Functions ****************************************************************************/ -#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS +#ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS /* PID Controller is configured to switch to PID 0 when the CPU fetches * instruction from the following window exception vectors: * - Window Overflow 4: mapped as Level 2 vector entry address @@ -131,4 +131,4 @@ _underflow8_exit_hook: rsr a1, misc1 rfwu -#endif /* CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS */ +#endif /* CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS */ diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index b604ab9e56..99c70d8ce9 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -400,6 +400,12 @@ config ESP32S3_RT_TIMER ---help--- Real-Time Timer is relying upon the Systimer 1. +config ESP32S3_WCL + bool "World Controller" + default n + select ARCH_USE_MPU + select XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS if BUILD_PROTECTED + endmenu # ESP32-S3 Peripheral Selection menu "SPI RAM Configuration" diff --git a/arch/xtensa/src/esp32s3/chip_macros.h b/arch/xtensa/src/esp32s3/chip_macros.h index 913f2e8476..cdba8246e2 100644 --- a/arch/xtensa/src/esp32s3/chip_macros.h +++ b/arch/xtensa/src/esp32s3/chip_macros.h @@ -33,6 +33,10 @@ #endif #endif +#if defined(CONFIG_ESP32S3_WCL) && defined(CONFIG_BUILD_PROTECTED) +#include "hardware/esp32s3_wcl_core.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -43,13 +47,20 @@ #define HANDLER_SECTION .iram1 -#if defined(CONFIG_BUILD_PROTECTED) +#if defined(CONFIG_ESP32S3_WCL) && defined(CONFIG_BUILD_PROTECTED) -#define xtensa_saveprivilege(regs,var) -#define xtensa_restoreprivilege(regs,var) +/* Definitions for the Worlds reserved for Kernel and Userspace */ -#define xtensa_lowerprivilege(regs) -#define xtensa_raiseprivilege(regs) +#define WCL_WORLD_KERNEL 0 /* Privileged */ +#define WCL_WORLD_USER 1 /* Non-privileged */ + +/* Macros for privilege handling with the World Controller peripheral */ + +#define xtensa_saveprivilege(regs,var) ((var) = (regs)[REG_INT_CTX]) +#define xtensa_restoreprivilege(regs,var) ((regs)[REG_INT_CTX] = (var)) + +#define xtensa_lowerprivilege(regs) ((regs)[REG_INT_CTX] = WCL_WORLD_USER) +#define xtensa_raiseprivilege(regs) ((regs)[REG_INT_CTX] = WCL_WORLD_KERNEL) #endif @@ -99,7 +110,169 @@ l32i a1, \tmp2, 0 /* a1 = *tmp2 */ .endm #endif -#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Name: clear_wcl_write_buffer + * + * Description: + * Clear World Controller write buffer upon World 0 entry. + * + * Entry Conditions: + * tmp - Temporary register + * + ****************************************************************************/ + + .macro clear_wcl_write_buffer tmp + /* Refer to ESP32-S3 Technical Reference Manual, section 16.4.3, for a + * detailed description of the write buffer clearing process. + */ + + wsr a2, DEPC + movi \tmp, SOC_RTC_DATA_LOW + movi a2, 0 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + addi a2, a2, 1 + s32i a2, \tmp, 0 + l32i \tmp, \tmp, 0 + memw + rsr a2, DEPC + .endm + +/**************************************************************************** + * Name: get_prev_world + * + * Description: + * Retrieve World information from interruptee. + * + * Entry Conditions: + * level - Interrupt level + * out - Temporary and output register + * + * Exit Conditions: + * World number to be returned will be written to "out" register. + * + ****************************************************************************/ + + .macro get_prev_world level out + .ifeq (\level - 1) * (\level - 3) + .ifeq (\level - 1) + movi \out, WCL_CORE_0_STATUSTABLE1_REG + .endif + .ifeq (\level - 3) + movi \out, WCL_CORE_0_STATUSTABLE2_REG + .endif + l32i \out, \out, 0 + extui \out, \out, 0, 1 + .endif + .endm + +/**************************************************************************** + * Name: set_next_world + * + * Description: + * Configure the World Controller for the new execution context. + * + * Entry Conditions: + * reg_sp - Stack pointer + * tmp1 - Temporary register 1 + * tmp2 - Temporary register 2 + * + ****************************************************************************/ + + .macro set_next_world reg_sp tmp1 tmp2 + movi \tmp1, BIT(1) + movi \tmp2, WCL_CORE_0_WORLD_PREPARE_REG + s32i \tmp1, \tmp2, 0 /* Prepare execution on World 1 */ + + l32i \tmp1, \reg_sp, (4 * REG_PC) + movi \tmp2, WCL_CORE_0_WORLD_TRIGGER_ADDR_REG + s32i \tmp1, \tmp2, 0 + + movi \tmp1, BIT(0) + movi \tmp2, WCL_CORE_0_WORLD_UPDATE_REG + s32i \tmp1, \tmp2, 0 + .endm + +/**************************************************************************** + * Name: exception_entry_hook + * + * Description: + * Perform chip-specific exception entry operations. + * + * Entry Conditions: + * level - Interrupt level + * reg_sp - Stack pointer + * tmp - Temporary register + * + ****************************************************************************/ + +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS + .macro exception_entry_hook level reg_sp tmp + .ifeq (\level - 1) * (\level - 3) + clear_wcl_write_buffer \tmp + + /* Save World information from interruptee when handling User Exceptions + * (Level 1) and Software-triggered interrupts (Level 3). + */ + + get_prev_world \level \tmp + s32i \tmp, \reg_sp, (4 * REG_INT_CTX) /* Save World into context */ + .endif + .endm +#endif + +/**************************************************************************** + * Name: exception_exit_hook + * + * Description: + * Perform chip-specific exception exit operations. + * + * Entry Conditions: + * level - Interrupt level + * reg_sp - Stack pointer + * tmp1 - Temporary register 1 + * tmp2 - Temporary register 2 + * + ****************************************************************************/ + +#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS + .macro exception_exit_hook level reg_sp tmp1 tmp2 + /* Configure the World Controller for the new execution context before + * returning from User Exceptions (Level 1) and Software-triggered + * interrupts (Level 3). + */ + + .ifeq (\level - 1) * (\level - 3) + movi \tmp1, 0x0 + .ifeq (\level - 1) + movi \tmp2, WCL_CORE_0_STATUSTABLE1_REG + .endif + .ifeq (\level - 3) + movi \tmp2, WCL_CORE_0_STATUSTABLE2_REG + .endif + s32i \tmp1, \tmp2, 0 /* Clear the table entry */ + + l32i \tmp1, \reg_sp, (4 * REG_INT_CTX) + beqz \tmp1, 1f + set_next_world \reg_sp \tmp1 \tmp2 + +1: + memw + .endif + .endm +#endif + +#endif /* __ASSEMBLY */ /**************************************************************************** * Public Data diff --git a/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c b/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c index 1ccac0a905..e0639a1fae 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c +++ b/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c @@ -43,6 +43,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef ALIGN_DOWN +# define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -66,7 +70,13 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) { #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) uintptr_t ubase = USERSPACE->us_dataend; - uintptr_t utop = ets_rom_layout_p->dram0_rtos_reserved_start; + + /* Align the heap top address to 256 bytes to match the PMS split address + * requirement. + */ + + uintptr_t utop = ALIGN_DOWN(ets_rom_layout_p->dram0_rtos_reserved_start, + 256); size_t usize = utop - ubase; minfo("Heap: start=%" PRIxPTR " end=%" PRIxPTR " size=%zu\n", diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c index ee6eea7fe1..3a7bfa9445 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.c +++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c @@ -43,6 +43,7 @@ #ifdef CONFIG_SMP #include "esp32s3_smp.h" #endif +#include "esp32s3_userspace.h" #include "hardware/esp32s3_interrupt_core0.h" #ifdef CONFIG_SMP #include "hardware/esp32s3_interrupt_core1.h" @@ -420,9 +421,7 @@ void up_irqinitialize(void) /* Hard code special cases. */ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32S3_CPUINT_SOFTWARE1); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32S3_CPUINT_SOFTWARE1); /* Initialize CPU interrupts */ @@ -439,6 +438,10 @@ void up_irqinitialize(void) esp32s3_gpioirqinitialize(); + /* Initialize interrupt handler for the PMS violation ISR */ + + esp32s3_pmsirqinitialize(); + #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts. Also clears PS.EXCM */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_userspace.c b/arch/xtensa/src/esp32s3/esp32s3_userspace.c index 04786a5c6c..fb52f186a8 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_userspace.c +++ b/arch/xtensa/src/esp32s3/esp32s3_userspace.c @@ -36,8 +36,15 @@ #include "chip.h" #include "xtensa.h" #include "xtensa_attr.h" +#include "esp32s3_irq.h" #include "esp32s3_userspace.h" +#include "hardware/esp32s3_apb_ctrl.h" #include "hardware/esp32s3_cache_memory.h" +#include "hardware/esp32s3_extmem.h" +#include "hardware/esp32s3_rom_layout.h" +#include "hardware/esp32s3_sensitive.h" +#include "hardware/esp32s3_soc.h" +#include "hardware/esp32s3_wcl_core.h" #ifdef CONFIG_BUILD_PROTECTED @@ -51,13 +58,67 @@ #define MMU_SIZE 0x3f0000 #define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) -/* Cache MMU block size */ - -#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ - /* Cache MMU address mask (MMU tables ignore bits which are zero) */ -#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) +#define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1)) + +/* Helper just for shortening */ + +#define VALUE_TO_PMS_FIELD(v, f) VALUE_TO_FIELD(v, SENSITIVE_CORE_X_ ## f) + +/* Total addressable space is 1GB for the External Memories */ + +#define EXTMEM_MAX_LENGTH 0x40000000 + +/* Maximum number of supported entry addresses */ + +#define WCL_ENTRY_MAX 13 + +/* Last value of the agreed sequence to be written to the address configured + * in WCL_CORE_0_MESSAGE_ADDR register. + */ + +#define WCL_SEQ_LAST_VAL 6 + +#define I_D_SRAM_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) +#define MAP_IRAM_TO_DRAM(addr) ((addr) - I_D_SRAM_OFFSET) + +/* Categories bits for split line configuration */ + +#define PMS_SRAM_CATEGORY_BELOW 0x0 +#define PMS_SRAM_CATEGORY_EQUAL 0x2 +#define PMS_SRAM_CATEGORY_ABOVE 0x3 + +/* Offsets for helping setting values to register fields */ + +#define ICACHE_PMS_W0_BASE 12 +#define ICACHE_PMS_W1_BASE 12 +#define ICACHE_PMS_S 3 +#define ICACHE_PMS_V 7 + +#define IRAM_PMS_W0_BASE 0 +#define IRAM_PMS_W1_BASE 0 +#define IRAM_PMS_S 3 +#define IRAM_PMS_V 7 + +#define DRAM_PMS_W0_BASE 0 +#define DRAM_PMS_W1_BASE 12 +#define DRAM_PMS_S 2 +#define DRAM_PMS_V 3 + +#define FLASH_CACHE_S 3 +#define FLASH_CACHE_V 7 + +#define PIF_PMS_MAX_REG_ENTRY 16 +#define PIF_PMS_V 3 + +#ifndef ALIGN_UP +# define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#endif + +#ifndef ALIGN_DOWN +# define ALIGN_DOWN(num, align) ((num) & ~((align) - 1)) +#endif /**************************************************************************** * Private Types @@ -68,11 +129,115 @@ struct user_image_load_header_s uintptr_t drom_vma; /* Destination address (VMA) for DROM region */ uintptr_t drom_lma; /* Flash offset (LMA) for start of DROM region */ uintptr_t drom_size; /* Size of DROM region */ + uintptr_t iram_vma; /* Destination address (VMA) for IRAM region */ + uintptr_t iram_lma; /* Flash offset (LMA) for start of IRAM region */ + uintptr_t iram_size; /* Size of IRAM region */ uintptr_t irom_vma; /* Destination address (VMA) for IROM region */ uintptr_t irom_lma; /* Flash offset (LMA) for start of IROM region */ uintptr_t irom_size; /* Size of IROM region */ }; +enum pms_world_e +{ + PMS_WORLD_0 = 0, + PMS_WORLD_1 +}; + +enum pms_split_line_e +{ + PMS_SPLIT_LINE_0 = 0, + PMS_SPLIT_LINE_1, + PMS_SPLIT_LINE_2, + PMS_SPLIT_LINE_3 +}; + +enum pms_area_e +{ + PMS_AREA_0 = 0, /* Area between BASE and split_line 0 */ + PMS_AREA_1, /* Area between split_line 0 and split_line 1 */ + PMS_AREA_2, /* Area between split_line 1 and END */ + PMS_AREA_3, + PMS_AREA_INVALID +}; + +enum pms_flags_e +{ + PMS_ACCESS_NONE = 0, + PMS_ACCESS_R = 1, + PMS_ACCESS_W = 2, + PMS_ACCESS_X = 4, + PMS_ACCESS_ALL = PMS_ACCESS_X | PMS_ACCESS_W | PMS_ACCESS_R +}; + +/* There are 55 peripherals, each having 2 bits for permission configuration. + * These are spread across 4 registers, each register having maximum of 16 + * peripheral entries. + * + * Enum defined as per the bit field position of the peripheral in the + * register: + * FIELD = 30 - 2 * (ENUM % 16) + */ + +enum pms_peripheral_e +{ + PMS_UART1 = 0, + PMS_I2S0, + PMS_I2C, + PMS_MISC, + PMS_HINF = 5, + PMS_IO_MUX = 7, + PMS_RTC, + PMS_FE = 10, + PMS_FE2 = 11, + PMS_GPIO, + PMS_G0SPI_0, + PMS_G0SPI_1, + PMS_UART, + PMS_SYSTIMER, + PMS_TIMERGROUP1, + PMS_TIMERGROUP, + PMS_PWM0, + PMS_BB, + PMS_BACKUP = 22, + PMS_LEDC, + PMS_SLC, + PMS_PCNT, + PMS_RMT, + PMS_SLCHOST, + PMS_UHCI0, + PMS_I2C_EXT0, + PMS_BT = 31, + PMS_PWR = 33, + PMS_WIFIMAC, + PMS_RWBT = 36, + PMS_UART2 = 39, + PMS_I2S1, + PMS_PWM1, + PMS_CAN, + PMS_SDIO_HOST, + PMS_I2C_EXT1, + PMS_APB_CTRL, + PMS_SPI_3, + PMS_SPI_2, + PMS_WORLD_CONTROLLER, + PMS_DIO, + PMS_AD, + PMS_CACHE_CONFIG, + PMS_DMA_COPY, + PMS_INTERRUPT, + PMS_SENSITIVE, + PMS_SYSTEM, + PMS_USB, + PMS_BT_PWR, + PMS_LCD_CAM, + PMS_APB_ADC, + PMS_CRYPTO_DMA, + PMS_CRYPTO_PERI, + PMS_USB_WRAP, + PMS_USB_DEVICE, + PMS_MAX +}; + /**************************************************************************** * ROM Function Prototypes ****************************************************************************/ @@ -80,6 +245,8 @@ struct user_image_load_header_s extern uint32_t cache_suspend_dcache(void); extern void cache_resume_dcache(uint32_t val); extern void cache_invalidate_dcache_all(void); +extern void cache_invalidate_icache_all(void); +extern void cache_writeback_all(void); extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); @@ -93,10 +260,79 @@ extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, static struct user_image_load_header_s g_header; +static const intptr_t g_sram_rg3_level_hlimits[] = +{ + 0x4037ffff, /* Block 2 (32KB) */ + 0x4038ffff, /* Block 3 (64KB) */ + 0x4039ffff, /* Block 4 (64KB) */ + 0x403affff, /* Block 5 (64KB) */ + 0x403bffff, /* Block 6 (64KB) */ + 0x403cffff, /* Block 7 (64KB) */ + 0x403dffff /* Block 8 (64KB) */ +}; + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: dcache_suspend + * + * Description: + * Helper function for suspending the data cache access for the CPU. + * + * Input Parameters: + * needs_wb - Flag indicating whether the CPU should perform the + * write-back of the data cache contents prior to + * invalidation. + * + * Returned Value: + * Current cache state. + * + ****************************************************************************/ + +static inline uint32_t dcache_suspend(bool needs_wb) +{ + uint32_t dcache_state = cache_suspend_dcache(); + + if (needs_wb) + { + cache_writeback_all(); + } + + cache_invalidate_dcache_all(); + + return dcache_state; +} + +/**************************************************************************** + * Name: dcache_resume + * + * Description: + * Helper function for resuming the data cache access for the CPU. + * + * Input Parameters: + * cache_state - Previously saved data cache state to be restored. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void dcache_resume(uint32_t cache_state) +{ + uint32_t regval; + + regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); + regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS; +#ifdef CONFIG_SMP + regval &= ~EXTMEM_DCACHE_SHUT_CORE1_BUS; +#endif + putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); + + cache_resume_dcache(cache_state); +} + /**************************************************************************** * Name: calc_mmu_pages * @@ -115,8 +351,8 @@ static struct user_image_load_header_s g_header; static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) { - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / - MMU_BLOCK_SIZE; + return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / + MMU_PAGE_SIZE; } /**************************************************************************** @@ -151,8 +387,7 @@ static noinline_function IRAM_ATTR void configure_flash_mmu(void) uint32_t app_irom_size = g_header.irom_size; uint32_t app_irom_vma = g_header.irom_vma; - uint32_t autoload = cache_suspend_dcache(); - cache_invalidate_dcache_all(); + uint32_t cache_state = dcache_suspend(false); drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; @@ -168,7 +403,7 @@ static noinline_function IRAM_ATTR void configure_flash_mmu(void) irom_lma_aligned, 64, (int)irom_page_count, 0) == 0); - cache_resume_dcache(autoload); + dcache_resume(cache_state); } /**************************************************************************** @@ -192,8 +427,7 @@ static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr, uint32_t src_addr_aligned; uint32_t page_count; - uint32_t autoload = cache_suspend_dcache(); - cache_invalidate_dcache_all(); + uint32_t cache_state = dcache_suspend(false); src_addr_aligned = src_addr & MMU_FLASH_MASK; page_count = calc_mmu_pages(size, src_addr); @@ -201,7 +435,7 @@ static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr, ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, src_addr_aligned, 64, (int)page_count, 0) == 0); - cache_resume_dcache(autoload); + dcache_resume(cache_state); return (void *)(MMU_BLOCK63_VADDR + (src_addr - src_addr_aligned)); } @@ -210,8 +444,9 @@ static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr, * Name: load_header * * Description: - * Load IROM and DROM information from image header to enable the correct - * configuration of the Flash MMU and Cache. + * Load metadata information from image header to enable the correct + * configuration of the Flash MMU and Cache and initialization of the + * code and data located in Internal RAM. * * Input Parameters: * None. @@ -233,7 +468,7 @@ static void load_header(void) } /**************************************************************************** - * Name: initialize_data + * Name: initialize_dram * * Description: * Initialize data sections of the userspace image. @@ -246,16 +481,36 @@ static void load_header(void) * ****************************************************************************/ -static void initialize_data(void) +static void initialize_dram(void) { uint8_t *dest; uint8_t *end; + + /* Clear all of userspace .bss */ + + ASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of userspace .data */ + + ASSERT(USERSPACE->us_datasource != 0 && USERSPACE->us_datastart != 0 && + USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + size_t length = USERSPACE->us_dataend - USERSPACE->us_datastart; const uint8_t *src = (const uint8_t *)map_flash(USER_IMAGE_OFFSET + USERSPACE->us_datasource, length); - DEBUGASSERT(src != NULL); + ASSERT(src != NULL); dest = (uint8_t *)USERSPACE->us_datastart; end = (uint8_t *)USERSPACE->us_dataend; @@ -266,6 +521,1238 @@ static void initialize_data(void) } } +/**************************************************************************** + * Name: initialize_iram + * + * Description: + * Initialize instruction sections of the userspace image. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void initialize_iram(void) +{ + uint32_t *dest; + uint32_t *end; + const uint32_t *src = + (const uint32_t *)map_flash(USER_IMAGE_OFFSET + g_header.iram_lma, + g_header.iram_size); + + ASSERT(src != NULL); + + /* This routine will initialize the IRAM region located in Internal SRAM0, + * which can be accessible using 32-bit loads and stores and if the source + * and destiny addresses and length are 32-bit aligned. + */ + + dest = (uint32_t *)g_header.iram_vma; + end = (uint32_t *)g_header.iram_vma + g_header.iram_size; + + while (dest != end) + { + *dest++ = *src++; + } +} + +/**************************************************************************** + * Name: wcl_set_vecbase + * + * Description: + * Override Vector Table base address via World Controller. + * + * Input Parameters: + * world - World to which the vector table base address will apply + * to. + * vecbase - Vector table base address to set. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void wcl_set_vecbase(enum pms_world_e world, uintptr_t vecbase) +{ + switch (world) + { + case PMS_WORLD_0: + { + modifyreg32(SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG, + SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M, + VALUE_TO_FIELD(vecbase >> 10, + SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE)); + } + break; + case PMS_WORLD_1: + { + modifyreg32(SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG, + SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M, + VALUE_TO_FIELD(vecbase >> 10, + SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE)); + } + break; + default: + { + PANIC(); + } + break; + } + + modifyreg32(SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG, + SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M, + VALUE_TO_FIELD(0x3, SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL)); + + modifyreg32(SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG, + SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M, 0); +} + +/**************************************************************************** + * Name: wcl_set_world0_entry + * + * Description: + * Configure the World Controller to switch to World 0 whenever the CPU + * performs an instruction fetch from a given address. + * + * Input Parameters: + * entry - Entry number. Up to 13 entry addresses are supported. + * Entry 0 is reserved and must be skipped. + * addr - Interrupt vector address that will trigger the change to + * World 0. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void wcl_set_world0_entry(uint32_t entry, uintptr_t addr) +{ + ASSERT(entry > 0 && entry <= WCL_ENTRY_MAX); + + /* Configure registers required for cleaning the World Controller write + * buffer upon World0 entry. + * + * Refer to ESP32-S3 Technical Reference Manual, section 16.4.3, for a + * detailed description of the write buffer clearing process. + */ + + putreg32(SOC_RTC_DATA_LOW, WCL_CORE_0_MESSAGE_ADDR_REG); + putreg32(WCL_SEQ_LAST_VAL, WCL_CORE_0_MESSAGE_MAX_REG); + + uint32_t reg = WCL_CORE_0_ENTRY_1_ADDR_REG + ((entry - 1) * 4); + + /* Write ENTRY address */ + + putreg32(addr, reg); + + /* Enable check for that particular address. When fetched, World will + * switch to World 0. + */ + + modifyreg32(WCL_CORE_0_ENTRY_CHECK_REG, 0, BIT(entry)); +} + +/**************************************************************************** + * Name: pms_violation_isr + * + * Description: + * This is the common PMS interrupt handler. It will be invoked the PMS + * detects an access violation. + * + * Parameters: + * cpuint - CPU interrupt index + * context - Context data from the ISR + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int IRAM_ATTR pms_violation_isr(int cpuint, void *context, void *arg) +{ + PANIC(); + + return OK; +} + +/**************************************************************************** + * Name: pms_enable_interrupts + * + * Description: + * Configure top level permission violation interrupts and set World + * Controller monitor registers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_enable_interrupts(void) +{ + /* We use two separate vector tables for WORLD0 and WORLD1, + * this allows us to handle Windowed exceptions in WORLD1 itself, thus + * saving CPU cycles. + * For other vectors, we jump to WORLD0 vector table from WORLD1 vector + * table. + * The vector table for WORLD1 is placed right at the start of WORLD1 IRAM. + */ + + wcl_set_vecbase(PMS_WORLD_0, VECTORS_START); + wcl_set_vecbase(PMS_WORLD_1, UIRAM_START); + + extern void _user_exception_vector(void); + wcl_set_world0_entry(1, (uintptr_t)_user_exception_vector); + extern void _xtensa_level3_vector(void); + wcl_set_world0_entry(2, (uintptr_t)_xtensa_level3_vector); + + /* Enable IRAM0 permission violation interrupt */ + + modifyreg32(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M, + SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN); + + /* Enable DRAM0 permission violation interrupt */ + + modifyreg32(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M, + SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN); + + /* Enable Flash Instruction Cache permission violation interrupt */ + + modifyreg32(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, + EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M, + 0); + modifyreg32(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, + EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M, + EXTMEM_CORE0_IBUS_REJECT_INT_ENA); + + /* Enable Flash Data Cache permission violation interrupt */ + + modifyreg32(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, + EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M, + 0); + modifyreg32(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, + EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M, + EXTMEM_CORE0_DBUS_REJECT_INT_ENA); + + /* Enable Flash Data Cache permission violation interrupt */ + + modifyreg32(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, + SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M, + SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); +} + +/**************************************************************************** + * Name: set_iram_split_line + * + * Description: + * Split the IRAM region into two sub regions. + * + * Input Parameters: + * addr - Address for the split line. + * sensitive_reg - Register to which the split line configuration will be + * applied. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void set_iram_split_line(uintptr_t addr, const uint32_t sensitive_reg) +{ + /* Set category bits for a given split line */ + + uint32_t cat[7] = + { + [0 ... 6] = PMS_SRAM_CATEGORY_ABOVE + }; + + for (size_t x = 0; x < 7; x++) + { + if (addr <= g_sram_rg3_level_hlimits[x]) + { + cat[x] = PMS_SRAM_CATEGORY_EQUAL; + break; + } + else + { + cat[x] = PMS_SRAM_CATEGORY_BELOW; + } + } + + /* Resolve split address' significant bits. + * Split address must be aligned to 256 bytes. + */ + + uint32_t regval = + VALUE_TO_PMS_FIELD((addr >> 8), IRAM0_DRAM0_DMA_SRAM_SPLITADDR) | + VALUE_TO_PMS_FIELD(cat[6], IRAM0_DRAM0_DMA_SRAM_CATEGORY_6) | + VALUE_TO_PMS_FIELD(cat[5], IRAM0_DRAM0_DMA_SRAM_CATEGORY_5) | + VALUE_TO_PMS_FIELD(cat[4], IRAM0_DRAM0_DMA_SRAM_CATEGORY_4) | + VALUE_TO_PMS_FIELD(cat[3], IRAM0_DRAM0_DMA_SRAM_CATEGORY_3) | + VALUE_TO_PMS_FIELD(cat[2], IRAM0_DRAM0_DMA_SRAM_CATEGORY_2) | + VALUE_TO_PMS_FIELD(cat[1], IRAM0_DRAM0_DMA_SRAM_CATEGORY_1) | + VALUE_TO_PMS_FIELD(cat[0], IRAM0_DRAM0_DMA_SRAM_CATEGORY_0); + + putreg32(regval, sensitive_reg); +} + +/**************************************************************************** + * Name: pms_set_sram_main_split_line + * + * Description: + * Configure the Internal SRAM1 Instruction and Data regions. + * + * Input Parameters: + * addr - Address for the split line. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void pms_set_sram_main_split_line(uintptr_t addr) +{ + set_iram_split_line(addr, + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); +} + +/**************************************************************************** + * Name: pms_set_iram_split_line + * + * Description: + * Helper function for setting the a split line into IRAM region. + * + * Input Parameters: + * line - Split line to be set. + * addr - Address for the split line. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void pms_set_iram_split_line(enum pms_split_line_e line, + uintptr_t addr) +{ + switch (line) + { + case PMS_SPLIT_LINE_0: + { + set_iram_split_line(addr, + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); + } + break; + case PMS_SPLIT_LINE_1: + { + set_iram_split_line(addr, + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); + } + break; + default: + { + PANIC(); + } + break; + } +} + +/**************************************************************************** + * Name: pms_configure_iram_split_region + * + * Description: + * Configure access permissions to a given split region in IRAM. + * + * Input Parameters: + * area - A given region created after setting a split line. + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed within the target area. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_iram_split_region(enum pms_area_e area, + enum pms_world_e world, + enum pms_flags_e flags) +{ + uint32_t reg; + uint32_t offset; + + if (world == PMS_WORLD_0) + { + reg = SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG; + offset = IRAM_PMS_W0_BASE; + } + else + { + reg = SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG; + offset = IRAM_PMS_W1_BASE; + } + + uint32_t shift = offset + (area * IRAM_PMS_S); + uint32_t mask = IRAM_PMS_V << shift; + uint32_t val = (flags & IRAM_PMS_V) << shift; + + modifyreg32(reg, mask, val); +} + +/**************************************************************************** + * Name: pms_configure_icache_permission + * + * Description: + * Configure access permissions to the Internal SRAM 0 blocks that won't be + * used as Instruction Cache. + * + * Input Parameters: + * area - Which of the two SRAM blocks used as Instruction Cache. + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed within the target area. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_icache_permission(enum pms_area_e area, + enum pms_world_e world, + enum pms_flags_e flags) +{ + uint32_t reg; + uint32_t offset; + + if (world == PMS_WORLD_0) + { + reg = SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG; + offset = ICACHE_PMS_W0_BASE; + } + else + { + reg = SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG; + offset = ICACHE_PMS_W1_BASE; + } + + uint32_t shift = offset + (area * ICACHE_PMS_S); + uint32_t mask = ICACHE_PMS_V << shift; + uint32_t val = (flags & ICACHE_PMS_V) << shift; + + modifyreg32(reg, mask, val); +} + +/**************************************************************************** + * Name: pms_configure_dcache_permission + * + * Description: + * Configure access permissions to the Internal SRAM 2 blocks that won't be + * used as Data Cache. + * + * Input Parameters: + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed within the target area. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_dcache_permission(enum pms_world_e world, + enum pms_flags_e flags) +{ + switch (world) + { + case PMS_WORLD_0: + { + modifyreg32(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M + | SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M, + VALUE_TO_PMS_FIELD(flags, + DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0) + | VALUE_TO_PMS_FIELD(flags, + DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1)); + } + break; + case PMS_WORLD_1: + { + modifyreg32(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M + | SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M, + VALUE_TO_PMS_FIELD(flags, + DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0) + | VALUE_TO_PMS_FIELD(flags, + DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1)); + } + break; + default: + { + PANIC(); + } + break; + } +} + +/**************************************************************************** + * Name: set_dram_split_line + * + * Description: + * Split the DRAM region into two sub regions. + * + * Input Parameters: + * addr - Address for the split line. + * sensitive_reg - Register to which the split line configuration will be + * applied. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void set_dram_split_line(uintptr_t addr, const uint32_t sensitive_reg) +{ + /* Set category bits for a given split line */ + + uint32_t cat[7] = + { + [0 ... 6] = PMS_SRAM_CATEGORY_ABOVE + }; + + for (size_t x = 0; x < 7; x++) + { + if (addr <= MAP_IRAM_TO_DRAM(g_sram_rg3_level_hlimits[x])) + { + cat[x] = PMS_SRAM_CATEGORY_EQUAL; + break; + } + else + { + cat[x] = PMS_SRAM_CATEGORY_BELOW; + } + } + + /* Resolve split address' significant bits. + * Split address must be aligned to 256 bytes. + */ + + uint32_t regval = + VALUE_TO_PMS_FIELD((addr >> 8), DRAM0_DMA_SRAM_LINE_0_SPLITADDR) | + VALUE_TO_PMS_FIELD(cat[6], DRAM0_DMA_SRAM_LINE_0_CATEGORY_6) | + VALUE_TO_PMS_FIELD(cat[5], DRAM0_DMA_SRAM_LINE_0_CATEGORY_5) | + VALUE_TO_PMS_FIELD(cat[4], DRAM0_DMA_SRAM_LINE_0_CATEGORY_4) | + VALUE_TO_PMS_FIELD(cat[3], DRAM0_DMA_SRAM_LINE_0_CATEGORY_3) | + VALUE_TO_PMS_FIELD(cat[2], DRAM0_DMA_SRAM_LINE_0_CATEGORY_2) | + VALUE_TO_PMS_FIELD(cat[1], DRAM0_DMA_SRAM_LINE_0_CATEGORY_1) | + VALUE_TO_PMS_FIELD(cat[0], DRAM0_DMA_SRAM_LINE_0_CATEGORY_0); + + putreg32(regval, sensitive_reg); +} + +/**************************************************************************** + * Name: pms_set_dram_split_line + * + * Description: + * Helper function for setting the a split line into DRAM region. + * + * Input Parameters: + * line - Split line to be set. + * addr - Address for the split line. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_set_dram_split_line(enum pms_split_line_e line, + uintptr_t addr) +{ + switch (line) + { + case PMS_SPLIT_LINE_0: + { + set_dram_split_line(addr, + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG); + } + break; + case PMS_SPLIT_LINE_1: + { + set_dram_split_line(addr, + SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG); + } + break; + default: + { + PANIC(); + } + break; + } +} + +/**************************************************************************** + * Name: pms_configure_dram_split_region + * + * Description: + * Configure access permissions to a given split region in DRAM. + * + * Input Parameters: + * area - A given region created after setting a split line. + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed within the target area. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_dram_split_region(enum pms_area_e area, + enum pms_world_e world, + enum pms_flags_e flags) +{ + uint32_t offset; + + if (world == PMS_WORLD_0) + { + offset = DRAM_PMS_W0_BASE; + } + else + { + offset = DRAM_PMS_W1_BASE; + } + + uint32_t shift = offset + (area * DRAM_PMS_S); + uint32_t mask = DRAM_PMS_V << shift; + uint32_t val = (flags & DRAM_PMS_V) << shift; + + modifyreg32(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, mask, val); +} + +/**************************************************************************** + * Name: pms_set_flash_cache_split_line + * + * Description: + * Split the External Flash region into sub regions. + * + * Input Parameters: + * line - Split line to be set. + * addr - Starting address for the new region. + * length - Length of the new region in bytes. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_set_flash_cache_split_line(enum pms_split_line_e line, + uintptr_t addr, size_t length) +{ + /* The starting address of each region should be aligned to 64 KB */ + + uintptr_t aligned_addr = ALIGN_DOWN(addr, MMU_PAGE_SIZE); + + /* The length of each region should be the integral multiples of 64 KB */ + + size_t length_pages = length / MMU_PAGE_SIZE; + + switch (line) + { + case PMS_SPLIT_LINE_0: + { + modifyreg32(APB_CTRL_FLASH_ACE0_ADDR_REG, + APB_CTRL_FLASH_ACE0_ADDR_S_M, + VALUE_TO_FIELD(aligned_addr, + APB_CTRL_FLASH_ACE0_ADDR_S)); + modifyreg32(APB_CTRL_FLASH_ACE0_SIZE_REG, + APB_CTRL_FLASH_ACE0_SIZE_M, + VALUE_TO_FIELD(length_pages, + APB_CTRL_FLASH_ACE0_SIZE)); + } + break; + case PMS_SPLIT_LINE_1: + { + modifyreg32(APB_CTRL_FLASH_ACE1_ADDR_REG, + APB_CTRL_FLASH_ACE1_ADDR_S_M, + VALUE_TO_FIELD(aligned_addr, + APB_CTRL_FLASH_ACE1_ADDR_S)); + modifyreg32(APB_CTRL_FLASH_ACE1_SIZE_REG, + APB_CTRL_FLASH_ACE1_SIZE_M, + VALUE_TO_FIELD(length_pages, + APB_CTRL_FLASH_ACE1_SIZE)); + } + break; + case PMS_SPLIT_LINE_2: + { + modifyreg32(APB_CTRL_FLASH_ACE2_ADDR_REG, + APB_CTRL_FLASH_ACE2_ADDR_S_M, + VALUE_TO_FIELD(aligned_addr, + APB_CTRL_FLASH_ACE2_ADDR_S)); + modifyreg32(APB_CTRL_FLASH_ACE2_SIZE_REG, + APB_CTRL_FLASH_ACE2_SIZE_M, + VALUE_TO_FIELD(length_pages, + APB_CTRL_FLASH_ACE2_SIZE)); + } + break; + case PMS_SPLIT_LINE_3: + { + modifyreg32(APB_CTRL_FLASH_ACE3_ADDR_REG, + APB_CTRL_FLASH_ACE3_ADDR_S_M, + VALUE_TO_FIELD(aligned_addr, + APB_CTRL_FLASH_ACE3_ADDR_S)); + modifyreg32(APB_CTRL_FLASH_ACE3_SIZE_REG, + APB_CTRL_FLASH_ACE3_SIZE_M, + VALUE_TO_FIELD(length_pages, + APB_CTRL_FLASH_ACE3_SIZE)); + } + break; + default: + { + PANIC(); + } + break; + } +} + +/**************************************************************************** + * Name: pms_configure_flash_cache_split_region + * + * Description: + * Configure access permissions to a given split region in External Flash. + * + * Input Parameters: + * area - A given region created after setting a split line. + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed within the target area. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void +pms_configure_flash_cache_split_region(enum pms_area_e area, + enum pms_world_e world, + enum pms_flags_e flags) +{ + const uint32_t shift = (FLASH_CACHE_S * world); + const uint32_t mask = FLASH_CACHE_V << shift; + uint32_t attr; + + if (flags == PMS_ACCESS_ALL) + { + attr = 0b11; + } + else if ((flags & PMS_ACCESS_W) != 0) + { + PANIC(); + } + else if ((flags & PMS_ACCESS_X) != 0) + { + attr = flags | 0b1; + } + else + { + attr = flags; + } + + uint32_t val = 0x40 | (attr & FLASH_CACHE_V) << shift; + + switch (area) + { + case PMS_AREA_0: + { + modifyreg32(APB_CTRL_FLASH_ACE0_ATTR_REG, mask, val); + } + break; + case PMS_AREA_1: + { + modifyreg32(APB_CTRL_FLASH_ACE1_ATTR_REG, mask, val); + } + break; + case PMS_AREA_2: + { + modifyreg32(APB_CTRL_FLASH_ACE2_ATTR_REG, mask, val); + } + break; + case PMS_AREA_3: + { + modifyreg32(APB_CTRL_FLASH_ACE3_ATTR_REG, mask, val); + } + break; + default: + { + PANIC(); + } + break; + } +} + +/**************************************************************************** + * Name: pms_configure_peripheral_permission + * + * Description: + * Configure access permissions to a given peripheral. + * + * Input Parameters: + * periph - A given peripheral to be configured. + * world - World to which the flags will apply to. + * flags - Attributes representing the operations allowed to be + * performed with the selected peripheral. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_peripheral_permission(enum pms_peripheral_e periph, + enum pms_world_e world, + enum pms_flags_e flags) +{ + uint32_t reg = 0; + uint32_t reg_off = periph / PIF_PMS_MAX_REG_ENTRY; + uint32_t bit_field_base = 30 - (2 * (periph % PIF_PMS_MAX_REG_ENTRY)); + + switch (world) + { + case PMS_WORLD_0: + { + reg = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG + (4 * reg_off); + } + break; + case PMS_WORLD_1: + { + reg = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG + (4 * reg_off); + } + break; + default: + { + PANIC(); + } + break; + } + + uint32_t mask = PIF_PMS_V << bit_field_base; + uint32_t val = (flags & PIF_PMS_V) << bit_field_base; + + modifyreg32(reg, mask, val); +} + +/**************************************************************************** + * Name: pms_configure_irom_access + * + * Description: + * Configure the access permissions to the IROM region. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_irom_access(void) +{ + /* Kernel permission to the IROM region */ + + modifyreg32(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M, + VALUE_TO_PMS_FIELD(PMS_ACCESS_ALL, + IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS)); + + /* User permission to the IROM region */ + + modifyreg32(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG, + SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M, + VALUE_TO_PMS_FIELD(PMS_ACCESS_NONE, + IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS)); +} + +/**************************************************************************** + * Name: pms_configure_drom_access + * + * Description: + * Configure the access permissions to the DROM region. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_drom_access(void) +{ + /* Kernel permission to the DROM region */ + + modifyreg32(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M, + VALUE_TO_PMS_FIELD(PMS_ACCESS_ALL, + DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS)); + + /* User permission to the DROM region */ + + modifyreg32(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, + SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M, + VALUE_TO_PMS_FIELD(PMS_ACCESS_NONE, + DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS)); +} + +/**************************************************************************** + * Name: pms_configure_iram_access + * + * Description: + * Configure the access permissions to the IRAM region. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_iram_access(void) +{ + /* Kernel permission to the Instruction Cache */ + + pms_configure_icache_permission(PMS_AREA_0, PMS_WORLD_0, PMS_ACCESS_ALL); + pms_configure_icache_permission(PMS_AREA_1, PMS_WORLD_0, PMS_ACCESS_ALL); + + /* User permission to the Instruction Cache */ + + pms_configure_icache_permission(PMS_AREA_0, PMS_WORLD_1, PMS_ACCESS_NONE); +#ifdef CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB + /* In case the Instruction Cache size is configured to 16KB, the other 16KB + * block from Internal SRAM0 (Block1) will be used as IRAM. + */ + + pms_configure_icache_permission(PMS_AREA_1, PMS_WORLD_1, PMS_ACCESS_ALL); +#else /* CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB */ + /* In case the Instruction Cache size is configured to 32KB, the WORLD1 + * access permissions to the Internal SRAM0 must be revoked. + */ + + pms_configure_icache_permission(PMS_AREA_1, PMS_WORLD_1, PMS_ACCESS_NONE); +#endif + + /* Set split lines to partition the IRAM into regions */ + + pms_set_iram_split_line(PMS_SPLIT_LINE_0, UIRAM_END); + pms_set_iram_split_line(PMS_SPLIT_LINE_1, KIRAM_END); + + /* Configure Kernel access permissions to each split region */ + + pms_configure_iram_split_region(PMS_AREA_0, PMS_WORLD_0, PMS_ACCESS_ALL); + pms_configure_iram_split_region(PMS_AREA_1, PMS_WORLD_0, PMS_ACCESS_ALL); + pms_configure_iram_split_region(PMS_AREA_2, PMS_WORLD_0, PMS_ACCESS_ALL); + + /* Configure User access permissions to each split region */ + +#ifdef CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB + /* In case the Instruction Cache size is configured to 16KB, the IRAM + * allocation to WORLD1 will be entirely restricted to Internal SRAM0, so + * we can safely revoke permissions to the shared Internal SRAM1. + */ + + pms_configure_iram_split_region(PMS_AREA_0, PMS_WORLD_1, PMS_ACCESS_NONE); +#else /* CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB */ + /* In case the Instruction Cache size is configured to 32KB, the first + * block from the shared Internal SRAM1 (Block2) will be allocated to + * WORLD1. + */ + + pms_configure_iram_split_region(PMS_AREA_0, PMS_WORLD_1, PMS_ACCESS_ALL); +#endif + pms_configure_iram_split_region(PMS_AREA_1, PMS_WORLD_1, PMS_ACCESS_NONE); + pms_configure_iram_split_region(PMS_AREA_2, PMS_WORLD_1, PMS_ACCESS_NONE); + + /* PMS_AREA_3 corresponds to the region after the main split line, + * i.e. the entire DRAM. + */ + + pms_configure_iram_split_region(PMS_AREA_3, PMS_WORLD_0, PMS_ACCESS_NONE); + pms_configure_iram_split_region(PMS_AREA_3, PMS_WORLD_1, PMS_ACCESS_NONE); +} + +/**************************************************************************** + * Name: pms_configure_dram_access + * + * Description: + * Configure the access permissions to the DRAM region. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_dram_access(void) +{ + /* Kernel permission to the Data Cache */ + + pms_configure_dcache_permission(PMS_WORLD_0, PMS_ACCESS_ALL); + + /* User permission to the Data Cache */ + + pms_configure_dcache_permission(PMS_WORLD_1, PMS_ACCESS_NONE); + + /* Split line to protect DRAM area reserved for ROM functions. + * ALIGN_DOWN macro is used to align the address to 256 bit boundary. + */ + + uintptr_t rom_reserve_aligned = + ALIGN_DOWN(ets_rom_layout_p->dram0_rtos_reserved_start, 256); + + /* Set split lines to partition the DRAM into regions */ + + pms_set_dram_split_line(PMS_SPLIT_LINE_0, UDRAM_START); + pms_set_dram_split_line(PMS_SPLIT_LINE_1, rom_reserve_aligned); + + /* PMS_AREA_0 corresponds to the region before the main split line, + * i.e entire IRAM. + */ + + pms_configure_dram_split_region(PMS_AREA_0, PMS_WORLD_0, PMS_ACCESS_NONE); + pms_configure_dram_split_region(PMS_AREA_0, PMS_WORLD_1, PMS_ACCESS_NONE); + + /* Configure Kernel access permissions to each split region */ + + pms_configure_dram_split_region(PMS_AREA_1, PMS_WORLD_0, PMS_ACCESS_ALL); + pms_configure_dram_split_region(PMS_AREA_2, PMS_WORLD_0, PMS_ACCESS_ALL); + pms_configure_dram_split_region(PMS_AREA_3, PMS_WORLD_0, PMS_ACCESS_ALL); + + /* Configure User access permissions to each split region */ + + pms_configure_dram_split_region(PMS_AREA_1, PMS_WORLD_1, PMS_ACCESS_NONE); + pms_configure_dram_split_region(PMS_AREA_2, PMS_WORLD_1, PMS_ACCESS_ALL); + pms_configure_dram_split_region(PMS_AREA_3, PMS_WORLD_1, PMS_ACCESS_NONE); +} + +/**************************************************************************** + * Name: pms_configure_flash_cache_access + * + * Description: + * Configure the access permissions to the region dedicated to the + * Instruction and Data Caches. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void pms_configure_flash_cache_access(void) +{ + /* Invalidate Cache */ + + uint32_t cache_state = dcache_suspend(true); + cache_invalidate_icache_all(); + + size_t partition_offset = USER_IMAGE_OFFSET; + + /* Total image size must be aligned to the MMU page size (64 KB) to match + * the required granularity of the PMS split regions for the External + * Flash. + * IROM region offset in External Flash plus its size provides an accurate + * estimate about the User Image size. + */ + + size_t total_size = ALIGN_UP(g_header.irom_lma + g_header.irom_size, + MMU_PAGE_SIZE); + size_t remaining_size = EXTMEM_MAX_LENGTH - partition_offset - total_size; + + uint32_t region0_start_addr = 0x0; + uint32_t region0_size = partition_offset; + uint32_t region1_start_addr = region0_start_addr + region0_size; + uint32_t region1_size = total_size; + uint32_t region2_start_addr = region1_start_addr + region1_size; + uint32_t region2_size = remaining_size / 2; + uint32_t region3_start_addr = region2_start_addr + region2_size; + uint32_t region3_size = remaining_size / 2; + + pms_set_flash_cache_split_line(PMS_SPLIT_LINE_0, region0_start_addr, + region0_size); + pms_set_flash_cache_split_line(PMS_SPLIT_LINE_1, region1_start_addr, + region1_size); + pms_set_flash_cache_split_line(PMS_SPLIT_LINE_2, region2_start_addr, + region2_size); + pms_set_flash_cache_split_line(PMS_SPLIT_LINE_3, region3_start_addr, + region3_size); + + /* Configure Kernel access permissions to each split region */ + + pms_configure_flash_cache_split_region(PMS_AREA_0, PMS_WORLD_0, + PMS_ACCESS_ALL); + + /* WORLD0 requires access to WORLD1 to load the cache when returning to + * WORLD1 from WORLD0. + */ + + pms_configure_flash_cache_split_region(PMS_AREA_1, PMS_WORLD_0, + PMS_ACCESS_ALL); + pms_configure_flash_cache_split_region(PMS_AREA_2, PMS_WORLD_0, + PMS_ACCESS_ALL); + pms_configure_flash_cache_split_region(PMS_AREA_3, PMS_WORLD_0, + PMS_ACCESS_ALL); + + /* Configure User access permissions to each split region */ + + pms_configure_flash_cache_split_region(PMS_AREA_0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_flash_cache_split_region(PMS_AREA_1, PMS_WORLD_1, + PMS_ACCESS_ALL); + pms_configure_flash_cache_split_region(PMS_AREA_2, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_flash_cache_split_region(PMS_AREA_3, PMS_WORLD_1, + PMS_ACCESS_NONE); + + dcache_resume(cache_state); +} + +/**************************************************************************** + * Name: pms_configure_peripheral_access + * + * Description: + * Configure Kernel and Userspace permissions for accessing the chip's + * peripherals. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pms_configure_peripheral_access(void) +{ + /* Revoke User access permission to every peripheral */ + + pms_configure_peripheral_permission(PMS_UART1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_I2C, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_MISC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_IO_MUX, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_RTC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_FE, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_FE2, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_GPIO, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_G0SPI_0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_G0SPI_1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_UART, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SYSTIMER, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_TIMERGROUP1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_TIMERGROUP, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_BB, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_LEDC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_RMT, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_UHCI0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_I2C_EXT0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_BT, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_PWR, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_WIFIMAC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_RWBT, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_I2S1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_CAN, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_APB_CTRL, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SPI_2, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_WORLD_CONTROLLER, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_DIO, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_AD, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_CACHE_CONFIG, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_DMA_COPY, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_INTERRUPT, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SENSITIVE, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SYSTEM, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_BT_PWR, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_APB_ADC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_CRYPTO_DMA, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_CRYPTO_PERI, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_USB_WRAP, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_USB_DEVICE, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_I2S0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_HINF, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_PWM0, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_BACKUP, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SLC, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_PCNT, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SLCHOST, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_UART2, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_PWM1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SDIO_HOST, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_I2C_EXT1, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_SPI_3, PMS_WORLD_1, + PMS_ACCESS_NONE); + pms_configure_peripheral_permission(PMS_USB, PMS_WORLD_1, + PMS_ACCESS_NONE); +} + /**************************************************************************** * Name: configure_mpu * @@ -282,6 +1769,45 @@ static void initialize_data(void) static void configure_mpu(void) { + /* Configure interrupts for permission violation */ + + pms_enable_interrupts(); + + /* Define the Internal SRAM1 regions for code and data by configuring the + * split lines. + */ + + pms_set_sram_main_split_line(KIRAM_END); + + /* Configure Kernel and Userspace permissions for accessing the internal + * memories. + */ + + /* IROM */ + + pms_configure_irom_access(); + + /* DROM */ + + pms_configure_drom_access(); + + /* IRAM */ + + pms_configure_iram_access(); + + /* DRAM */ + + pms_configure_dram_access(); + + /* Instruction and Data Caches */ + + pms_configure_flash_cache_access(); + + /* Configure Kernel and Userspace permissions for accessing the chip's + * peripherals. + */ + + pms_configure_peripheral_access(); } /**************************************************************************** @@ -307,10 +1833,7 @@ static void configure_mpu(void) void esp32s3_userspace(void) { - uint8_t *dest; - uint8_t *end; - - /* Load IROM and DROM information from image header */ + /* Load metadata information from image header */ load_header(); @@ -318,30 +1841,58 @@ void esp32s3_userspace(void) configure_flash_mmu(); - /* Clear all of userspace .bss */ + /* Initialize userspace DRAM */ - DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && - USERSPACE->us_bssstart <= USERSPACE->us_bssend); + initialize_dram(); - dest = (uint8_t *)USERSPACE->us_bssstart; - end = (uint8_t *)USERSPACE->us_bssend; + /* Initialize userspace IRAM */ - while (dest != end) - { - *dest++ = 0; - } - - /* Initialize all of userspace .data */ - - DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && - USERSPACE->us_datastart <= USERSPACE->us_dataend); - - initialize_data(); + initialize_iram(); /* Configure MPU to grant access to the userspace */ configure_mpu(); } +/**************************************************************************** + * Name: esp32s3_pmsirqinitialize + * + * Description: + * Initialize interrupt handler for the PMS violation ISR. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_pmsirqinitialize(void) +{ + VERIFY(esp32s3_setup_irq(0, + ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE, + 1, ESP32S3_CPUINT_LEVEL)); + VERIFY(esp32s3_setup_irq(0, + ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE, + 1, ESP32S3_CPUINT_LEVEL)); + VERIFY(esp32s3_setup_irq(0, ESP32S3_PERIPH_CACHE_CORE0_ACS, 1, + ESP32S3_CPUINT_LEVEL)); + VERIFY(esp32s3_setup_irq(0, ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE, + 1, ESP32S3_CPUINT_LEVEL)); + + VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE, + pms_violation_isr, NULL)); + VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE, + pms_violation_isr, NULL)); + VERIFY(irq_attach(ESP32S3_IRQ_CACHE_CORE0_ACS, pms_violation_isr, NULL)); + VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE, + pms_violation_isr, NULL)); + + up_enable_irq(ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE); + up_enable_irq(ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE); + up_enable_irq(ESP32S3_IRQ_CACHE_CORE0_ACS); + up_enable_irq(ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE); +} + #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_userspace.h b/arch/xtensa/src/esp32s3/esp32s3_userspace.h index 2496042ed2..0deff1d0f5 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_userspace.h +++ b/arch/xtensa/src/esp32s3/esp32s3_userspace.h @@ -46,4 +46,24 @@ void esp32s3_userspace(void); #endif +/**************************************************************************** + * Name: esp32s3_pmsirqinitialize + * + * Description: + * Initialize interrupt handler for the PMS violation ISR. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void esp32s3_pmsirqinitialize(void); +#else +# define esp32s3_pmsirqinitialize() +#endif + #endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USERSPACE_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h new file mode 100644 index 0000000000..fa1c307d57 --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h @@ -0,0 +1,1135 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_APB_CTRL_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_APB_CTRL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* APB_CTRL_SYSCLK_CONF_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) + +/* APB_CTRL_RST_TICK_CNT : R/W; bitpos: [12]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (APB_CTRL_RST_TICK_CNT_V << APB_CTRL_RST_TICK_CNT_S) +#define APB_CTRL_RST_TICK_CNT_V 0x00000001 +#define APB_CTRL_RST_TICK_CNT_S 12 + +/* APB_CTRL_CLK_EN : R/W; bitpos: [11]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (APB_CTRL_CLK_EN_V << APB_CTRL_CLK_EN_S) +#define APB_CTRL_CLK_EN_V 0x00000001 +#define APB_CTRL_CLK_EN_S 11 + +/* APB_CTRL_CLK_320M_EN : R/W; bitpos: [10]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (APB_CTRL_CLK_320M_EN_V << APB_CTRL_CLK_320M_EN_S) +#define APB_CTRL_CLK_320M_EN_V 0x00000001 +#define APB_CTRL_CLK_320M_EN_S 10 + +/* APB_CTRL_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_PRE_DIV_CNT 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_M (APB_CTRL_PRE_DIV_CNT_V << APB_CTRL_PRE_DIV_CNT_S) +#define APB_CTRL_PRE_DIV_CNT_V 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_S 0 + +/* APB_CTRL_TICK_CONF_REG register + * ******* Description *********** + */ + +#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) + +/* APB_CTRL_TICK_ENABLE : R/W; bitpos: [16]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_TICK_ENABLE (BIT(16)) +#define APB_CTRL_TICK_ENABLE_M (APB_CTRL_TICK_ENABLE_V << APB_CTRL_TICK_ENABLE_S) +#define APB_CTRL_TICK_ENABLE_V 0x00000001 +#define APB_CTRL_TICK_ENABLE_S 16 + +/* APB_CTRL_CK8M_TICK_NUM : R/W; bitpos: [15:8]; default: 7; + * ******* Description *********** + */ + +#define APB_CTRL_CK8M_TICK_NUM 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_M (APB_CTRL_CK8M_TICK_NUM_V << APB_CTRL_CK8M_TICK_NUM_S) +#define APB_CTRL_CK8M_TICK_NUM_V 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_S 8 + +/* APB_CTRL_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; + * ******* Description *********** + */ + +#define APB_CTRL_XTAL_TICK_NUM 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_M (APB_CTRL_XTAL_TICK_NUM_V << APB_CTRL_XTAL_TICK_NUM_S) +#define APB_CTRL_XTAL_TICK_NUM_V 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +/* APB_CTRL_CLK_OUT_EN_REG register + * ******* Description *********** + */ + +#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x8) + +/* APB_CTRL_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_M (APB_CTRL_CLK_XTAL_OEN_V << APB_CTRL_CLK_XTAL_OEN_S) +#define APB_CTRL_CLK_XTAL_OEN_V 0x00000001 +#define APB_CTRL_CLK_XTAL_OEN_S 10 + +/* APB_CTRL_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_M (APB_CTRL_CLK40X_BB_OEN_V << APB_CTRL_CLK40X_BB_OEN_S) +#define APB_CTRL_CLK40X_BB_OEN_V 0x00000001 +#define APB_CTRL_CLK40X_BB_OEN_S 9 + +/* APB_CTRL_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_M (APB_CTRL_CLK_DAC_CPU_OEN_V << APB_CTRL_CLK_DAC_CPU_OEN_S) +#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x00000001 +#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 + +/* APB_CTRL_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_M (APB_CTRL_CLK_ADC_INF_OEN_V << APB_CTRL_CLK_ADC_INF_OEN_S) +#define APB_CTRL_CLK_ADC_INF_OEN_V 0x00000001 +#define APB_CTRL_CLK_ADC_INF_OEN_S 7 + +/* APB_CTRL_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_320M_OEN (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_M (APB_CTRL_CLK_320M_OEN_V << APB_CTRL_CLK_320M_OEN_S) +#define APB_CTRL_CLK_320M_OEN_V 0x00000001 +#define APB_CTRL_CLK_320M_OEN_S 6 + +/* APB_CTRL_CLK160_OEN : R/W; bitpos: [5]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK160_OEN (BIT(5)) +#define APB_CTRL_CLK160_OEN_M (APB_CTRL_CLK160_OEN_V << APB_CTRL_CLK160_OEN_S) +#define APB_CTRL_CLK160_OEN_V 0x00000001 +#define APB_CTRL_CLK160_OEN_S 5 + +/* APB_CTRL_CLK80_OEN : R/W; bitpos: [4]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK80_OEN (BIT(4)) +#define APB_CTRL_CLK80_OEN_M (APB_CTRL_CLK80_OEN_V << APB_CTRL_CLK80_OEN_S) +#define APB_CTRL_CLK80_OEN_V 0x00000001 +#define APB_CTRL_CLK80_OEN_S 4 + +/* APB_CTRL_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK_BB_OEN (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_M (APB_CTRL_CLK_BB_OEN_V << APB_CTRL_CLK_BB_OEN_S) +#define APB_CTRL_CLK_BB_OEN_V 0x00000001 +#define APB_CTRL_CLK_BB_OEN_S 3 + +/* APB_CTRL_CLK44_OEN : R/W; bitpos: [2]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK44_OEN (BIT(2)) +#define APB_CTRL_CLK44_OEN_M (APB_CTRL_CLK44_OEN_V << APB_CTRL_CLK44_OEN_S) +#define APB_CTRL_CLK44_OEN_V 0x00000001 +#define APB_CTRL_CLK44_OEN_S 2 + +/* APB_CTRL_CLK22_OEN : R/W; bitpos: [1]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK22_OEN (BIT(1)) +#define APB_CTRL_CLK22_OEN_M (APB_CTRL_CLK22_OEN_V << APB_CTRL_CLK22_OEN_S) +#define APB_CTRL_CLK22_OEN_V 0x00000001 +#define APB_CTRL_CLK22_OEN_S 1 + +/* APB_CTRL_CLK20_OEN : R/W; bitpos: [0]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_CLK20_OEN (BIT(0)) +#define APB_CTRL_CLK20_OEN_M (APB_CTRL_CLK20_OEN_V << APB_CTRL_CLK20_OEN_S) +#define APB_CTRL_CLK20_OEN_V 0x00000001 +#define APB_CTRL_CLK20_OEN_S 0 + +/* APB_CTRL_WIFI_BB_CFG_REG register + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xc) + +/* APB_CTRL_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_BB_CFG 0xffffffff +#define APB_CTRL_WIFI_BB_CFG_M (APB_CTRL_WIFI_BB_CFG_V << APB_CTRL_WIFI_BB_CFG_S) +#define APB_CTRL_WIFI_BB_CFG_V 0xffffffff +#define APB_CTRL_WIFI_BB_CFG_S 0 + +/* APB_CTRL_WIFI_BB_CFG_2_REG register + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x10) + +/* APB_CTRL_WIFI_BB_CFG_2 : R/W; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_BB_CFG_2 0xffffffff +#define APB_CTRL_WIFI_BB_CFG_2_M (APB_CTRL_WIFI_BB_CFG_2_V << APB_CTRL_WIFI_BB_CFG_2_S) +#define APB_CTRL_WIFI_BB_CFG_2_V 0xffffffff +#define APB_CTRL_WIFI_BB_CFG_2_S 0 + +/* APB_CTRL_WIFI_CLK_EN_REG register + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x14) + +/* APB_CTRL_WIFI_CLK_EN : R/W; bitpos: [31:0]; default: 4294762544; + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_CLK_EN 0xffffffff +#define APB_CTRL_WIFI_CLK_EN_M (APB_CTRL_WIFI_CLK_EN_V << APB_CTRL_WIFI_CLK_EN_S) +#define APB_CTRL_WIFI_CLK_EN_V 0xffffffff +#define APB_CTRL_WIFI_CLK_EN_S 0 + +/* APB_CTRL_WIFI_RST_EN_REG register + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18) + +/* APB_CTRL_WIFI_RST : R/W; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_WIFI_RST 0xffffffff +#define APB_CTRL_WIFI_RST_M (APB_CTRL_WIFI_RST_V << APB_CTRL_WIFI_RST_S) +#define APB_CTRL_WIFI_RST_V 0xffffffff +#define APB_CTRL_WIFI_RST_S 0 + +/* APB_CTRL_HOST_INF_SEL_REG register + * ******* Description *********** + */ + +#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x1c) + +/* APB_CTRL_PERI_IO_SWAP : R/W; bitpos: [7:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_PERI_IO_SWAP 0x000000ff +#define APB_CTRL_PERI_IO_SWAP_M (APB_CTRL_PERI_IO_SWAP_V << APB_CTRL_PERI_IO_SWAP_S) +#define APB_CTRL_PERI_IO_SWAP_V 0x000000ff +#define APB_CTRL_PERI_IO_SWAP_S 0 + +/* APB_CTRL_EXT_MEM_PMS_LOCK_REG register + * ******* Description *********** + */ + +#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x20) + +/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W; bitpos: [0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_M (APB_CTRL_EXT_MEM_PMS_LOCK_V << APB_CTRL_EXT_MEM_PMS_LOCK_S) +#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x00000001 +#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 + +/* APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG register + * ******* Description *********** + */ + +#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24) + +/* APB_CTRL_WRITEBACK_BYPASS : R/W; bitpos: [0]; default: 0; + * Set 1 to bypass cache writeback request to external memory so that spi + * will not check its attribute. + */ + +#define APB_CTRL_WRITEBACK_BYPASS (BIT(0)) +#define APB_CTRL_WRITEBACK_BYPASS_M (APB_CTRL_WRITEBACK_BYPASS_V << APB_CTRL_WRITEBACK_BYPASS_S) +#define APB_CTRL_WRITEBACK_BYPASS_V 0x00000001 +#define APB_CTRL_WRITEBACK_BYPASS_S 0 + +/* APB_CTRL_FLASH_ACE0_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x28) + +/* APB_CTRL_FLASH_ACE0_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_ATTR 0x000001ff +#define APB_CTRL_FLASH_ACE0_ATTR_M (APB_CTRL_FLASH_ACE0_ATTR_V << APB_CTRL_FLASH_ACE0_ATTR_S) +#define APB_CTRL_FLASH_ACE0_ATTR_V 0x000001ff +#define APB_CTRL_FLASH_ACE0_ATTR_S 0 + +/* APB_CTRL_FLASH_ACE1_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x2c) + +/* APB_CTRL_FLASH_ACE1_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_ATTR 0x000001ff +#define APB_CTRL_FLASH_ACE1_ATTR_M (APB_CTRL_FLASH_ACE1_ATTR_V << APB_CTRL_FLASH_ACE1_ATTR_S) +#define APB_CTRL_FLASH_ACE1_ATTR_V 0x000001ff +#define APB_CTRL_FLASH_ACE1_ATTR_S 0 + +/* APB_CTRL_FLASH_ACE2_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30) + +/* APB_CTRL_FLASH_ACE2_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_ATTR 0x000001ff +#define APB_CTRL_FLASH_ACE2_ATTR_M (APB_CTRL_FLASH_ACE2_ATTR_V << APB_CTRL_FLASH_ACE2_ATTR_S) +#define APB_CTRL_FLASH_ACE2_ATTR_V 0x000001ff +#define APB_CTRL_FLASH_ACE2_ATTR_S 0 + +/* APB_CTRL_FLASH_ACE3_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x34) + +/* APB_CTRL_FLASH_ACE3_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_ATTR 0x000001ff +#define APB_CTRL_FLASH_ACE3_ATTR_M (APB_CTRL_FLASH_ACE3_ATTR_V << APB_CTRL_FLASH_ACE3_ATTR_S) +#define APB_CTRL_FLASH_ACE3_ATTR_V 0x000001ff +#define APB_CTRL_FLASH_ACE3_ATTR_S 0 + +/* APB_CTRL_FLASH_ACE0_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x38) + +/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_ADDR_S 0xffffffff +#define APB_CTRL_FLASH_ACE0_ADDR_S_M (APB_CTRL_FLASH_ACE0_ADDR_S_V << APB_CTRL_FLASH_ACE0_ADDR_S_S) +#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xffffffff +#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 + +/* APB_CTRL_FLASH_ACE1_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3c) + +/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W; bitpos: [31:0]; default: 268435456; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_ADDR_S 0xffffffff +#define APB_CTRL_FLASH_ACE1_ADDR_S_M (APB_CTRL_FLASH_ACE1_ADDR_S_V << APB_CTRL_FLASH_ACE1_ADDR_S_S) +#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xffffffff +#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 + +/* APB_CTRL_FLASH_ACE2_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x40) + +/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W; bitpos: [31:0]; default: 536870912; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_ADDR_S 0xffffffff +#define APB_CTRL_FLASH_ACE2_ADDR_S_M (APB_CTRL_FLASH_ACE2_ADDR_S_V << APB_CTRL_FLASH_ACE2_ADDR_S_S) +#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xffffffff +#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 + +/* APB_CTRL_FLASH_ACE3_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x44) + +/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W; bitpos: [31:0]; default: 805306368; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_ADDR_S 0xffffffff +#define APB_CTRL_FLASH_ACE3_ADDR_S_M (APB_CTRL_FLASH_ACE3_ADDR_S_V << APB_CTRL_FLASH_ACE3_ADDR_S_S) +#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xffffffff +#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 + +/* APB_CTRL_FLASH_ACE0_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48) + +/* APB_CTRL_FLASH_ACE0_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE0_SIZE 0x0000ffff +#define APB_CTRL_FLASH_ACE0_SIZE_M (APB_CTRL_FLASH_ACE0_SIZE_V << APB_CTRL_FLASH_ACE0_SIZE_S) +#define APB_CTRL_FLASH_ACE0_SIZE_V 0x0000ffff +#define APB_CTRL_FLASH_ACE0_SIZE_S 0 + +/* APB_CTRL_FLASH_ACE1_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x4c) + +/* APB_CTRL_FLASH_ACE1_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE1_SIZE 0x0000ffff +#define APB_CTRL_FLASH_ACE1_SIZE_M (APB_CTRL_FLASH_ACE1_SIZE_V << APB_CTRL_FLASH_ACE1_SIZE_S) +#define APB_CTRL_FLASH_ACE1_SIZE_V 0x0000ffff +#define APB_CTRL_FLASH_ACE1_SIZE_S 0 + +/* APB_CTRL_FLASH_ACE2_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x50) + +/* APB_CTRL_FLASH_ACE2_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE2_SIZE 0x0000ffff +#define APB_CTRL_FLASH_ACE2_SIZE_M (APB_CTRL_FLASH_ACE2_SIZE_V << APB_CTRL_FLASH_ACE2_SIZE_S) +#define APB_CTRL_FLASH_ACE2_SIZE_V 0x0000ffff +#define APB_CTRL_FLASH_ACE2_SIZE_S 0 + +/* APB_CTRL_FLASH_ACE3_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54) + +/* APB_CTRL_FLASH_ACE3_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_FLASH_ACE3_SIZE 0x0000ffff +#define APB_CTRL_FLASH_ACE3_SIZE_M (APB_CTRL_FLASH_ACE3_SIZE_V << APB_CTRL_FLASH_ACE3_SIZE_S) +#define APB_CTRL_FLASH_ACE3_SIZE_V 0x0000ffff +#define APB_CTRL_FLASH_ACE3_SIZE_S 0 + +/* APB_CTRL_SRAM_ACE0_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x58) + +/* APB_CTRL_SRAM_ACE0_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_ATTR 0x000001ff +#define APB_CTRL_SRAM_ACE0_ATTR_M (APB_CTRL_SRAM_ACE0_ATTR_V << APB_CTRL_SRAM_ACE0_ATTR_S) +#define APB_CTRL_SRAM_ACE0_ATTR_V 0x000001ff +#define APB_CTRL_SRAM_ACE0_ATTR_S 0 + +/* APB_CTRL_SRAM_ACE1_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x5c) + +/* APB_CTRL_SRAM_ACE1_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_ATTR 0x000001ff +#define APB_CTRL_SRAM_ACE1_ATTR_M (APB_CTRL_SRAM_ACE1_ATTR_V << APB_CTRL_SRAM_ACE1_ATTR_S) +#define APB_CTRL_SRAM_ACE1_ATTR_V 0x000001ff +#define APB_CTRL_SRAM_ACE1_ATTR_S 0 + +/* APB_CTRL_SRAM_ACE2_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60) + +/* APB_CTRL_SRAM_ACE2_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_ATTR 0x000001ff +#define APB_CTRL_SRAM_ACE2_ATTR_M (APB_CTRL_SRAM_ACE2_ATTR_V << APB_CTRL_SRAM_ACE2_ATTR_S) +#define APB_CTRL_SRAM_ACE2_ATTR_V 0x000001ff +#define APB_CTRL_SRAM_ACE2_ATTR_S 0 + +/* APB_CTRL_SRAM_ACE3_ATTR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x64) + +/* APB_CTRL_SRAM_ACE3_ATTR : R/W; bitpos: [8:0]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_ATTR 0x000001ff +#define APB_CTRL_SRAM_ACE3_ATTR_M (APB_CTRL_SRAM_ACE3_ATTR_V << APB_CTRL_SRAM_ACE3_ATTR_S) +#define APB_CTRL_SRAM_ACE3_ATTR_V 0x000001ff +#define APB_CTRL_SRAM_ACE3_ATTR_S 0 + +/* APB_CTRL_SRAM_ACE0_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x68) + +/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_ADDR_S 0xffffffff +#define APB_CTRL_SRAM_ACE0_ADDR_S_M (APB_CTRL_SRAM_ACE0_ADDR_S_V << APB_CTRL_SRAM_ACE0_ADDR_S_S) +#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xffffffff +#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 + +/* APB_CTRL_SRAM_ACE1_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6c) + +/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W; bitpos: [31:0]; default: 268435456; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_ADDR_S 0xffffffff +#define APB_CTRL_SRAM_ACE1_ADDR_S_M (APB_CTRL_SRAM_ACE1_ADDR_S_V << APB_CTRL_SRAM_ACE1_ADDR_S_S) +#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xffffffff +#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 + +/* APB_CTRL_SRAM_ACE2_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x70) + +/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W; bitpos: [31:0]; default: 536870912; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_ADDR_S 0xffffffff +#define APB_CTRL_SRAM_ACE2_ADDR_S_M (APB_CTRL_SRAM_ACE2_ADDR_S_V << APB_CTRL_SRAM_ACE2_ADDR_S_S) +#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xffffffff +#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 + +/* APB_CTRL_SRAM_ACE3_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x74) + +/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W; bitpos: [31:0]; default: 805306368; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_ADDR_S 0xffffffff +#define APB_CTRL_SRAM_ACE3_ADDR_S_M (APB_CTRL_SRAM_ACE3_ADDR_S_V << APB_CTRL_SRAM_ACE3_ADDR_S_S) +#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xffffffff +#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 + +/* APB_CTRL_SRAM_ACE0_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78) + +/* APB_CTRL_SRAM_ACE0_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE0_SIZE 0x0000ffff +#define APB_CTRL_SRAM_ACE0_SIZE_M (APB_CTRL_SRAM_ACE0_SIZE_V << APB_CTRL_SRAM_ACE0_SIZE_S) +#define APB_CTRL_SRAM_ACE0_SIZE_V 0x0000ffff +#define APB_CTRL_SRAM_ACE0_SIZE_S 0 + +/* APB_CTRL_SRAM_ACE1_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x7c) + +/* APB_CTRL_SRAM_ACE1_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE1_SIZE 0x0000ffff +#define APB_CTRL_SRAM_ACE1_SIZE_M (APB_CTRL_SRAM_ACE1_SIZE_V << APB_CTRL_SRAM_ACE1_SIZE_S) +#define APB_CTRL_SRAM_ACE1_SIZE_V 0x0000ffff +#define APB_CTRL_SRAM_ACE1_SIZE_S 0 + +/* APB_CTRL_SRAM_ACE2_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x80) + +/* APB_CTRL_SRAM_ACE2_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE2_SIZE 0x0000ffff +#define APB_CTRL_SRAM_ACE2_SIZE_M (APB_CTRL_SRAM_ACE2_SIZE_V << APB_CTRL_SRAM_ACE2_SIZE_S) +#define APB_CTRL_SRAM_ACE2_SIZE_V 0x0000ffff +#define APB_CTRL_SRAM_ACE2_SIZE_S 0 + +/* APB_CTRL_SRAM_ACE3_SIZE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84) + +/* APB_CTRL_SRAM_ACE3_SIZE : R/W; bitpos: [15:0]; default: 4096; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_ACE3_SIZE 0x0000ffff +#define APB_CTRL_SRAM_ACE3_SIZE_M (APB_CTRL_SRAM_ACE3_SIZE_V << APB_CTRL_SRAM_ACE3_SIZE_S) +#define APB_CTRL_SRAM_ACE3_SIZE_V 0x0000ffff +#define APB_CTRL_SRAM_ACE3_SIZE_S 0 + +/* APB_CTRL_SPI_MEM_PMS_CTRL_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x88) + +/* APB_CTRL_SPI_MEM_REJECT_CDE : RO; bitpos: [6:2]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001f +#define APB_CTRL_SPI_MEM_REJECT_CDE_M (APB_CTRL_SPI_MEM_REJECT_CDE_V << APB_CTRL_SPI_MEM_REJECT_CDE_S) +#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x0000001f +#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 + +/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD; bitpos: [1]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_M (APB_CTRL_SPI_MEM_REJECT_CLR_V << APB_CTRL_SPI_MEM_REJECT_CLR_S) +#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x00000001 +#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 + +/* APB_CTRL_SPI_MEM_REJECT_INT : RO; bitpos: [0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_M (APB_CTRL_SPI_MEM_REJECT_INT_V << APB_CTRL_SPI_MEM_REJECT_INT_S) +#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x00000001 +#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 + +/* APB_CTRL_SPI_MEM_REJECT_ADDR_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x8c) + +/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO; bitpos: [31:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xffffffff +#define APB_CTRL_SPI_MEM_REJECT_ADDR_M (APB_CTRL_SPI_MEM_REJECT_ADDR_V << APB_CTRL_SPI_MEM_REJECT_ADDR_S) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xffffffff +#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 + +/* APB_CTRL_SDIO_CTRL_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x90) + +/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W; bitpos: [0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (APB_CTRL_SDIO_WIN_ACCESS_EN_V << APB_CTRL_SDIO_WIN_ACCESS_EN_S) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x00000001 +#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 + +/* APB_CTRL_REDCY_SIG0_REG register + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94) + +/* APB_CTRL_REDCY_ANDOR : RO; bitpos: [31]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_ANDOR (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_M (APB_CTRL_REDCY_ANDOR_V << APB_CTRL_REDCY_ANDOR_S) +#define APB_CTRL_REDCY_ANDOR_V 0x00000001 +#define APB_CTRL_REDCY_ANDOR_S 31 + +/* APB_CTRL_REDCY_SIG0 : R/W; bitpos: [30:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_SIG0 0x7fffffff +#define APB_CTRL_REDCY_SIG0_M (APB_CTRL_REDCY_SIG0_V << APB_CTRL_REDCY_SIG0_S) +#define APB_CTRL_REDCY_SIG0_V 0x7fffffff +#define APB_CTRL_REDCY_SIG0_S 0 + +/* APB_CTRL_REDCY_SIG1_REG register + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x98) + +/* APB_CTRL_REDCY_NANDOR : RO; bitpos: [31]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_NANDOR (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_M (APB_CTRL_REDCY_NANDOR_V << APB_CTRL_REDCY_NANDOR_S) +#define APB_CTRL_REDCY_NANDOR_V 0x00000001 +#define APB_CTRL_REDCY_NANDOR_S 31 + +/* APB_CTRL_REDCY_SIG1 : R/W; bitpos: [30:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_REDCY_SIG1 0x7fffffff +#define APB_CTRL_REDCY_SIG1_M (APB_CTRL_REDCY_SIG1_V << APB_CTRL_REDCY_SIG1_S) +#define APB_CTRL_REDCY_SIG1_V 0x7fffffff +#define APB_CTRL_REDCY_SIG1_S 0 + +/* APB_CTRL_FRONT_END_MEM_PD_REG register + * ******* Description *********** + */ + +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9c) + +/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W; bitpos: [7]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7)) +#define APB_CTRL_FREQ_MEM_FORCE_PD_M (APB_CTRL_FREQ_MEM_FORCE_PD_V << APB_CTRL_FREQ_MEM_FORCE_PD_S) +#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x00000001 +#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7 + +/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6)) +#define APB_CTRL_FREQ_MEM_FORCE_PU_M (APB_CTRL_FREQ_MEM_FORCE_PU_V << APB_CTRL_FREQ_MEM_FORCE_PU_S) +#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x00000001 +#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6 + +/* APB_CTRL_DC_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_M (APB_CTRL_DC_MEM_FORCE_PD_V << APB_CTRL_DC_MEM_FORCE_PD_S) +#define APB_CTRL_DC_MEM_FORCE_PD_V 0x00000001 +#define APB_CTRL_DC_MEM_FORCE_PD_S 5 + +/* APB_CTRL_DC_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_M (APB_CTRL_DC_MEM_FORCE_PU_V << APB_CTRL_DC_MEM_FORCE_PU_S) +#define APB_CTRL_DC_MEM_FORCE_PU_V 0x00000001 +#define APB_CTRL_DC_MEM_FORCE_PU_S 4 + +/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_M (APB_CTRL_PBUS_MEM_FORCE_PD_V << APB_CTRL_PBUS_MEM_FORCE_PD_S) +#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x00000001 +#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 + +/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_M (APB_CTRL_PBUS_MEM_FORCE_PU_V << APB_CTRL_PBUS_MEM_FORCE_PU_S) +#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x00000001 +#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 + +/* APB_CTRL_AGC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_M (APB_CTRL_AGC_MEM_FORCE_PD_V << APB_CTRL_AGC_MEM_FORCE_PD_S) +#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x00000001 +#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 + +/* APB_CTRL_AGC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1; + * ******* Description *********** + */ + +#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_M (APB_CTRL_AGC_MEM_FORCE_PU_V << APB_CTRL_AGC_MEM_FORCE_PU_S) +#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x00000001 +#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 + +/* APB_CTRL_SPI_MEM_ECC_CTRL_REG register + * ******* Description *********** + */ + +#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xa0) + +/* APB_CTRL_SRAM_PAGE_SIZE : R/W; bitpos: [21:20]; default: 2; + * Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 + * bytes. 2: 1024 bytes. 3: 2048 bytes. + */ + +#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003 +#define APB_CTRL_SRAM_PAGE_SIZE_M (APB_CTRL_SRAM_PAGE_SIZE_V << APB_CTRL_SRAM_PAGE_SIZE_S) +#define APB_CTRL_SRAM_PAGE_SIZE_V 0x00000003 +#define APB_CTRL_SRAM_PAGE_SIZE_S 20 + +/* APB_CTRL_FLASH_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; + * Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: + * 1024 bytes. 3: 2048 bytes. + */ + +#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003 +#define APB_CTRL_FLASH_PAGE_SIZE_M (APB_CTRL_FLASH_PAGE_SIZE_V << APB_CTRL_FLASH_PAGE_SIZE_S) +#define APB_CTRL_FLASH_PAGE_SIZE_V 0x00000003 +#define APB_CTRL_FLASH_PAGE_SIZE_S 18 + +/* APB_CTRL_CLKGATE_FORCE_ON_REG register + * ******* Description *********** + */ + +#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0xa8) + +/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [13:3]; default: 2047; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007ff +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M (APB_CTRL_SRAM_CLKGATE_FORCE_ON_V << APB_CTRL_SRAM_CLKGATE_FORCE_ON_S) +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x000007ff +#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3 + +/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [2:0]; default: 7; + * ******* Description *********** + */ + +#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M (APB_CTRL_ROM_CLKGATE_FORCE_ON_V << APB_CTRL_ROM_CLKGATE_FORCE_ON_S) +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x00000007 +#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0 + +/* APB_CTRL_MEM_POWER_DOWN_REG register + * ******* Description *********** + */ + +#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0xac) + +/* APB_CTRL_SRAM_POWER_DOWN : R/W; bitpos: [13:3]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_POWER_DOWN 0x000007ff +#define APB_CTRL_SRAM_POWER_DOWN_M (APB_CTRL_SRAM_POWER_DOWN_V << APB_CTRL_SRAM_POWER_DOWN_S) +#define APB_CTRL_SRAM_POWER_DOWN_V 0x000007ff +#define APB_CTRL_SRAM_POWER_DOWN_S 3 + +/* APB_CTRL_ROM_POWER_DOWN : R/W; bitpos: [2:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_ROM_POWER_DOWN 0x00000007 +#define APB_CTRL_ROM_POWER_DOWN_M (APB_CTRL_ROM_POWER_DOWN_V << APB_CTRL_ROM_POWER_DOWN_S) +#define APB_CTRL_ROM_POWER_DOWN_V 0x00000007 +#define APB_CTRL_ROM_POWER_DOWN_S 0 + +/* APB_CTRL_MEM_POWER_UP_REG register + * ******* Description *********** + */ + +#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xb0) + +/* APB_CTRL_SRAM_POWER_UP : R/W; bitpos: [13:3]; default: 2047; + * ******* Description *********** + */ + +#define APB_CTRL_SRAM_POWER_UP 0x000007ff +#define APB_CTRL_SRAM_POWER_UP_M (APB_CTRL_SRAM_POWER_UP_V << APB_CTRL_SRAM_POWER_UP_S) +#define APB_CTRL_SRAM_POWER_UP_V 0x000007ff +#define APB_CTRL_SRAM_POWER_UP_S 3 + +/* APB_CTRL_ROM_POWER_UP : R/W; bitpos: [2:0]; default: 7; + * ******* Description *********** + */ + +#define APB_CTRL_ROM_POWER_UP 0x00000007 +#define APB_CTRL_ROM_POWER_UP_M (APB_CTRL_ROM_POWER_UP_V << APB_CTRL_ROM_POWER_UP_S) +#define APB_CTRL_ROM_POWER_UP_V 0x00000007 +#define APB_CTRL_ROM_POWER_UP_S 0 + +/* APB_CTRL_RETENTION_CTRL_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xb4) + +/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W; bitpos: [27]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27)) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (APB_CTRL_NOBYPASS_CPU_ISO_RST_V << APB_CTRL_NOBYPASS_CPU_ISO_RST_S) +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x00000001 +#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 + +/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W; bitpos: [26:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CPU_LINK_ADDR 0x07ffffff +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M (APB_CTRL_RETENTION_CPU_LINK_ADDR_V << APB_CTRL_RETENTION_CPU_LINK_ADDR_S) +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V 0x07ffffff +#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S 0 + +/* APB_CTRL_RETENTION_CTRL1_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL1_REG (DR_REG_APB_CTRL_BASE + 0xb8) + +/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W; bitpos: [26:0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_TAG_LINK_ADDR 0x07ffffff +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M (APB_CTRL_RETENTION_TAG_LINK_ADDR_V << APB_CTRL_RETENTION_TAG_LINK_ADDR_S) +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V 0x07ffffff +#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S 0 + +/* APB_CTRL_RETENTION_CTRL2_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0xbc) + +/* APB_CTRL_RET_ICACHE_ENABLE : R/W; bitpos: [31]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RET_ICACHE_ENABLE (BIT(31)) +#define APB_CTRL_RET_ICACHE_ENABLE_M (APB_CTRL_RET_ICACHE_ENABLE_V << APB_CTRL_RET_ICACHE_ENABLE_S) +#define APB_CTRL_RET_ICACHE_ENABLE_V 0x00000001 +#define APB_CTRL_RET_ICACHE_ENABLE_S 31 + +/* APB_CTRL_RET_ICACHE_START_POINT : R/W; bitpos: [29:22]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RET_ICACHE_START_POINT 0x000000ff +#define APB_CTRL_RET_ICACHE_START_POINT_M (APB_CTRL_RET_ICACHE_START_POINT_V << APB_CTRL_RET_ICACHE_START_POINT_S) +#define APB_CTRL_RET_ICACHE_START_POINT_V 0x000000ff +#define APB_CTRL_RET_ICACHE_START_POINT_S 22 + +/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W; bitpos: [20:13]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_RET_ICACHE_VLD_SIZE 0x000000ff +#define APB_CTRL_RET_ICACHE_VLD_SIZE_M (APB_CTRL_RET_ICACHE_VLD_SIZE_V << APB_CTRL_RET_ICACHE_VLD_SIZE_S) +#define APB_CTRL_RET_ICACHE_VLD_SIZE_V 0x000000ff +#define APB_CTRL_RET_ICACHE_VLD_SIZE_S 13 + +/* APB_CTRL_RET_ICACHE_SIZE : R/W; bitpos: [11:4]; default: 255; + * ******* Description *********** + */ + +#define APB_CTRL_RET_ICACHE_SIZE 0x000000ff +#define APB_CTRL_RET_ICACHE_SIZE_M (APB_CTRL_RET_ICACHE_SIZE_V << APB_CTRL_RET_ICACHE_SIZE_S) +#define APB_CTRL_RET_ICACHE_SIZE_V 0x000000ff +#define APB_CTRL_RET_ICACHE_SIZE_S 4 + +/* APB_CTRL_RETENTION_CTRL3_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL3_REG (DR_REG_APB_CTRL_BASE + 0xc0) + +/* APB_CTRL_RET_DCACHE_ENABLE : R/W; bitpos: [31]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RET_DCACHE_ENABLE (BIT(31)) +#define APB_CTRL_RET_DCACHE_ENABLE_M (APB_CTRL_RET_DCACHE_ENABLE_V << APB_CTRL_RET_DCACHE_ENABLE_S) +#define APB_CTRL_RET_DCACHE_ENABLE_V 0x00000001 +#define APB_CTRL_RET_DCACHE_ENABLE_S 31 + +/* APB_CTRL_RET_DCACHE_START_POINT : R/W; bitpos: [30:22]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RET_DCACHE_START_POINT 0x000001ff +#define APB_CTRL_RET_DCACHE_START_POINT_M (APB_CTRL_RET_DCACHE_START_POINT_V << APB_CTRL_RET_DCACHE_START_POINT_S) +#define APB_CTRL_RET_DCACHE_START_POINT_V 0x000001ff +#define APB_CTRL_RET_DCACHE_START_POINT_S 22 + +/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W; bitpos: [21:13]; default: 511; + * ******* Description *********** + */ + +#define APB_CTRL_RET_DCACHE_VLD_SIZE 0x000001ff +#define APB_CTRL_RET_DCACHE_VLD_SIZE_M (APB_CTRL_RET_DCACHE_VLD_SIZE_V << APB_CTRL_RET_DCACHE_VLD_SIZE_S) +#define APB_CTRL_RET_DCACHE_VLD_SIZE_V 0x000001ff +#define APB_CTRL_RET_DCACHE_VLD_SIZE_S 13 + +/* APB_CTRL_RET_DCACHE_SIZE : R/W; bitpos: [12:4]; default: 511; + * ******* Description *********** + */ + +#define APB_CTRL_RET_DCACHE_SIZE 0x000001ff +#define APB_CTRL_RET_DCACHE_SIZE_M (APB_CTRL_RET_DCACHE_SIZE_V << APB_CTRL_RET_DCACHE_SIZE_S) +#define APB_CTRL_RET_DCACHE_SIZE_V 0x000001ff +#define APB_CTRL_RET_DCACHE_SIZE_S 4 + +/* APB_CTRL_RETENTION_CTRL4_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL4_REG (DR_REG_APB_CTRL_BASE + 0xc4) + +/* APB_CTRL_RETENTION_INV_CFG : R/W; bitpos: [31:0]; default: 4294967295; + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_INV_CFG 0xffffffff +#define APB_CTRL_RETENTION_INV_CFG_M (APB_CTRL_RETENTION_INV_CFG_V << APB_CTRL_RETENTION_INV_CFG_S) +#define APB_CTRL_RETENTION_INV_CFG_V 0xffffffff +#define APB_CTRL_RETENTION_INV_CFG_S 0 + +/* APB_CTRL_RETENTION_CTRL5_REG register + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_CTRL5_REG (DR_REG_APB_CTRL_BASE + 0xc8) + +/* APB_CTRL_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0; + * ******* Description *********** + */ + +#define APB_CTRL_RETENTION_DISABLE (BIT(0)) +#define APB_CTRL_RETENTION_DISABLE_M (APB_CTRL_RETENTION_DISABLE_V << APB_CTRL_RETENTION_DISABLE_S) +#define APB_CTRL_RETENTION_DISABLE_V 0x00000001 +#define APB_CTRL_RETENTION_DISABLE_S 0 + +/* APB_CTRL_DATE_REG register + * ******* Description *********** + */ + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3fc) + +/* APB_CTRL_DATE : R/W; bitpos: [31:0]; default: 34607440; + * Version control + */ + +#define APB_CTRL_DATE 0xffffffff +#define APB_CTRL_DATE_M (APB_CTRL_DATE_V << APB_CTRL_DATE_S) +#define APB_CTRL_DATE_V 0xffffffff +#define APB_CTRL_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_APB_CTRL_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h new file mode 100644 index 0000000000..1e246d1c3b --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h @@ -0,0 +1,8495 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SENSITIVE_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SENSITIVE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG register + * Cache data array configuration register 0. + */ + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x0) + +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock cache data array registers. + */ + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK (BIT(0)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M (SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V << SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V 0x00000001 +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S 0 + +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG register + * Cache data array configuration register 1. + */ + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG (DR_REG_SENSITIVE_BASE + 0x4) + +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W; bitpos: [7:0]; default: + * 255; + * Cache data array connection configuration. + */ + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN 0x000000ff +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M (SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V << SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V 0x000000ff +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S 0 + +/* SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register + * APB peripheral configuration register 0. + */ + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x8) + +/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock APB peripheral Configuration Register. + */ + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x00000001 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 + +/* SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register + * APB peripheral configuration register 1. + */ + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0xc) + +/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: + * 1; + * Set 1 to support split function for AHB access to APB peripherals. + */ + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x00000001 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 + +/* SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register + * Internal SRAM configuration register 0. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x10) + +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock internal SRAM Configuration Register. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x00000001 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 + +/* SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register + * Internal SRAM configuration register 1. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x14) + +/* SENSITIVE_INTERNAL_SRAM_CPU_USAGE : R/W; bitpos: [10:4]; default: 127; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by cpu. + */ + +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_M (SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V << SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S 4 + +/* SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE : R/W; bitpos: [3:2]; default: 3; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by dcache. + */ + +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_M (SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V << SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S 2 + +/* SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE : R/W; bitpos: [1:0]; default: 3; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by icache. + */ + +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_M (SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V << SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S 0 + +/* SENSITIVE_INTERNAL_SRAM_USAGE_2_REG register + * Internal SRAM configuration register 2. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x18) + +/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC : R/W; bitpos: [17:16]; + * default: 0; + * Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace + * bus. + */ + +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_M (SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V << SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S) +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S 16 + +/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC : R/W; bitpos: [15:14]; + * default: 0; + * Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace + * bus. + */ + +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_M (SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V << SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S) +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V 0x00000003 +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S 14 + +/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE : R/W; bitpos: [13:7]; default: + * 0; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by core1 trace bus. + */ + +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_M (SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V << SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S 7 + +/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE : R/W; bitpos: [6:0]; default: + * 0; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by core0 trace bus. + */ + +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_M (SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V << SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S 0 + +/* SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register + * Internal SRAM configuration register 3. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x1c) + +/* SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE : R/W; bitpos: [3:0]; default: 0; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by mac dump. + */ + +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE 0x0000000f +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_M (SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V << SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V 0x0000000f +#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S 0 + +/* SENSITIVE_INTERNAL_SRAM_USAGE_4_REG register + * Internal SRAM configuration register 4. + */ + +#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x20) + +/* SENSITIVE_INTERNAL_SRAM_LOG_USAGE : R/W; bitpos: [6:0]; default: 0; + * Set 1 to someone bit means corresponding internal SRAM level can be + * accessed by log bus. + */ + +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_M (SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V << SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S) +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V 0x0000007f +#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S 0 + +/* SENSITIVE_RETENTION_DISABLE_REG register + * Retention configuration register. + */ + +#define SENSITIVE_RETENTION_DISABLE_REG (DR_REG_SENSITIVE_BASE + 0x24) + +/* SENSITIVE_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0; + * Set 1 to disable retention function and lock disable state. + */ + +#define SENSITIVE_RETENTION_DISABLE (BIT(0)) +#define SENSITIVE_RETENTION_DISABLE_M (SENSITIVE_RETENTION_DISABLE_V << SENSITIVE_RETENTION_DISABLE_S) +#define SENSITIVE_RETENTION_DISABLE_V 0x00000001 +#define SENSITIVE_RETENTION_DISABLE_S 0 + +/* SENSITIVE_CACHE_TAG_ACCESS_0_REG register + * Cache tag configuration register 0. + */ + +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x28) + +/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock cache tag Configuration Register. + */ + +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x00000001 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 + +/* SENSITIVE_CACHE_TAG_ACCESS_1_REG register + * Cache tag configuration register 1. + */ + +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2c) + +/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1; + * Set 1 to enable Dcache wrtie access tag memory. + */ + +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x00000001 +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 + +/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1; + * Set 1 to enable Dcache read access tag memory. + */ + +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x00000001 +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 + +/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1; + * Set 1 to enable Icache wrtie access tag memory. + */ + +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x00000001 +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 + +/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1; + * Set 1 to enable Icache read access tag memory. + */ + +#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x00000001 +#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 + +/* SENSITIVE_CACHE_MMU_ACCESS_0_REG register + * Cache MMU configuration register 0. + */ + +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x30) + +/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock cache MMU registers. + */ + +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x00000001 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 + +/* SENSITIVE_CACHE_MMU_ACCESS_1_REG register + * Cache MMU configuration register 1. + */ + +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x34) + +/* SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1; + * Set 1 to enable write access MMU memory. + */ + +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x00000001 +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 + +/* SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1; + * Set 1 to enable read access MMU memory. + */ + +#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_M (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x00000001 +#define SENSITIVE_PRO_MMU_RD_ACS_S 0 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG register + * spi2 dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x38) + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock spi2 dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG register + * spi2 dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x3c) + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * spi2's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * spi2's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * spi2's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * spi2's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * spi2's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * spi2's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG register + * spi3 dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x40) + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock spi3 dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG register + * spi3 dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x44) + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * spi3's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * spi3's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * spi3's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * spi3's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * spi3's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * spi3's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG register + * uhci0 dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x48) + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock uhci0 dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG register + * uhci0 dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x4c) + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [11:10]; default: 3; + * uhci0's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [9:8]; default: 3; + * uhci0's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: + * [7:6]; default: 3; + * uhci0's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: + * [5:4]; default: 3; + * uhci0's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: + * [3:2]; default: 3; + * uhci0's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: + * [1:0]; default: 3; + * uhci0's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG register + * i2s0 dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x50) + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock i2s0 dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG register + * i2s0 dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x54) + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * i2s0's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * i2s0's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * i2s0's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * i2s0's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * i2s0's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * i2s0's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG register + * i2s1 dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x58) + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock i2s1 dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG register + * i2s1 dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x5c) + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * i2s1's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * i2s1's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * i2s1's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * i2s1's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * i2s1's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * i2s1's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG register + * mac dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x60) + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock mac dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG register + * mac dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x64) + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * mac's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * mac's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * mac's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * mac's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * mac's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * mac's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG register + * backup dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x68) + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock backup dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG register + * backup dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x6c) + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [11:10]; default: 3; + * backup's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [9:8]; default: 3; + * backup's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: + * [7:6]; default: 3; + * backup's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: + * [5:4]; default: 3; + * backup's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: + * [3:2]; default: 3; + * backup's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: + * [1:0]; default: 3; + * backup's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG register + * aes dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x70) + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock aes dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG register + * aes dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x74) + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * aes's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * aes's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * aes's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * aes's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * aes's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * aes's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG register + * sha dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x78) + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock sha dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG register + * sha dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x7c) + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * sha's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * sha's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * sha's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * sha's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * sha's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * sha's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG register + * adc_dac dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x80) + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock adc_dac dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG register + * adc_dac dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x84) + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [11:10]; default: 3; + * adc_dac's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [9:8]; default: 3; + * adc_dac's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: + * [7:6]; default: 3; + * adc_dac's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: + * [5:4]; default: 3; + * adc_dac's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: + * [3:2]; default: 3; + * adc_dac's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: + * [1:0]; default: 3; + * adc_dac's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG register + * rmt dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x88) + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock rmt dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG register + * rmt dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x8c) + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * rmt's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * rmt's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * rmt's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * rmt's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * rmt's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * rmt's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG register + * lcd_cam dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x90) + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock lcd_cam dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG register + * lcd_cam dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x94) + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [11:10]; default: 3; + * lcd_cam's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [9:8]; default: 3; + * lcd_cam's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: + * [7:6]; default: 3; + * lcd_cam's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: + * [5:4]; default: 3; + * lcd_cam's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: + * [3:2]; default: 3; + * lcd_cam's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: + * [1:0]; default: 3; + * lcd_cam's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG register + * usb dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x98) + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock usb dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG register + * usb dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x9c) + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * usb's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * usb's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * usb's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * usb's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * usb's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * usb's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG register + * lc dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xa0) + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: + * 0; + * Set 1 to lock lc dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG register + * lc dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xa4) + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * lc's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * lc's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * lc's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * lc's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * lc's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * lc's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG register + * sdio dma permission configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xa8) + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock sdio dma permission Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG register + * sdio dma permission configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xac) + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W; + * bitpos: [11:10]; default: 3; + * sdio's permission(store,load) in dcache data sram block1 + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W; + * bitpos: [9:8]; default: 3; + * sdio's permission(store,load) in dcache data sram block0 + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 : R/W; bitpos: [7:6]; + * default: 3; + * sdio's permission(store,load) in data region3 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S 6 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 : R/W; bitpos: [5:4]; + * default: 3; + * sdio's permission(store,load) in data region2 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S 4 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 : R/W; bitpos: [3:2]; + * default: 3; + * sdio's permission(store,load) in data region1 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S 2 + +/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 : R/W; bitpos: [1:0]; + * default: 3; + * sdio's permission(store,load) in data region0 of SRAM + */ + +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M (SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S) +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S 0 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG register + * dma permission monitor configuration register 0. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xb0) + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock dma permission monitor Configuration Register. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG register + * dma permission monitor configuration register 1. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xb4) + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: + * 1; + * Set 1 to enable dma pms monitor, if dma access violated permission, will + * trigger interrupt. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear dma_pms_monitor_violate interrupt + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG register + * dma permission monitor configuration register 2. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xb8) + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: + * [24:3]; default: 0; + * recorded dma's address bit[25:4] status when dma access violated + * permission, real address is 0x3c00_0000+addr*16 + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003fffff +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x003fffff +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: + * [2:1]; default: 0; + * recorded dma's world status when dma access violated permission + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * recorded dma's interrupt status when dma access violated permission + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG register + * dma permission monitor configuration register 3. + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xbc) + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: + * [16:1]; default: 0; + * recorded dma's byte enable status when dma access violated permission + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000ffff +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0x0000ffff +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 + +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; + * default: 0; + * recorded dma's write status when dma access violated permission, + * 1(write), 0(read) + */ + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG register + * sram split line configuration register 0 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xc0) + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W; bitpos: + * [0]; default: 0; + * Set 1 to lock sram split configuration register + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG register + * sram split line configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xc4) + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W; bitpos: [21:14]; + * default: 0; + * splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of + * actual address + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W; bitpos: [13:12]; + * default: 0; + * category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of + * SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, + * configured as 0x11, else if splitaddress higher than block6 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S 12 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W; bitpos: [11:10]; + * default: 0; + * category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of + * SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, + * configured as 0x11, else if splitaddress higher than block5 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S 10 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W; bitpos: [9:8]; + * default: 0; + * category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of + * SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, + * configured as 0x11, else if splitaddress higher than block4 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S 8 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W; bitpos: [7:6]; + * default: 0; + * category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of + * SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, + * configured as 0x11, else if splitaddress higher than block3 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S 6 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W; bitpos: [5:4]; + * default: 0; + * category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of + * SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, + * configured as 0x11, else if splitaddress higher than block2 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W; bitpos: [3:2]; + * default: 0; + * category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of + * SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, + * configured as 0x11, else if splitaddress higher than block1 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W; bitpos: [1:0]; + * default: 0; + * category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of + * SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, + * configured as 0x11, else if splitaddress higher than block0 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG register + * sram split line configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xc8) + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; + * default: 0; + * splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of + * actual address + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W; bitpos: [13:12]; + * default: 0; + * category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of + * SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, + * configured as 0x11, else if splitaddress higher than block6 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S 12 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W; bitpos: [11:10]; + * default: 0; + * category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of + * SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, + * configured as 0x11, else if splitaddress higher than block5 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S 10 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W; bitpos: [9:8]; + * default: 0; + * category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of + * SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, + * configured as 0x11, else if splitaddress higher than block4 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S 8 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W; bitpos: [7:6]; + * default: 0; + * category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of + * SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, + * configured as 0x11, else if splitaddress higher than block3 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S 6 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; + * default: 0; + * category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of + * SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, + * configured as 0x11, else if splitaddress higher than block2 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; + * default: 0; + * category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of + * SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, + * configured as 0x11, else if splitaddress higher than block1 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; + * default: 0; + * category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of + * SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, + * configured as 0x11, else if splitaddress higher than block0 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG register + * sram split line configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xcc) + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; + * default: 0; + * splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of + * actual address + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0x000000ff +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W; bitpos: [13:12]; + * default: 0; + * category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of + * SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, + * configured as 0x11, else if splitaddress higher than block6 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S 12 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W; bitpos: [11:10]; + * default: 0; + * category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of + * SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, + * configured as 0x11, else if splitaddress higher than block5 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S 10 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W; bitpos: [9:8]; + * default: 0; + * category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of + * SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, + * configured as 0x11, else if splitaddress higher than block4 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S 8 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W; bitpos: [7:6]; + * default: 0; + * category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of + * SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, + * configured as 0x11, else if splitaddress higher than block3 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S 6 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; + * default: 0; + * category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of + * SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, + * configured as 0x11, else if splitaddress higher than block2 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; + * default: 0; + * category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of + * SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, + * configured as 0x11, else if splitaddress higher than block1 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 + +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; + * default: 0; + * category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of + * SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, + * configured as 0x11, else if splitaddress higher than block0 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG register + * sram split line configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0xd0) + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; + * default: 0; + * splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of + * actual address + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x000000ff +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0x000000ff +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W; bitpos: [13:12]; + * default: 0; + * category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of + * SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, + * configured as 0x11, else if splitaddress higher than block6 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S 12 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W; bitpos: [11:10]; + * default: 0; + * category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of + * SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, + * configured as 0x11, else if splitaddress higher than block5 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S 10 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W; bitpos: [9:8]; + * default: 0; + * category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of + * SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, + * configured as 0x11, else if splitaddress higher than block4 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S 8 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W; bitpos: [7:6]; + * default: 0; + * category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of + * SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, + * configured as 0x11, else if splitaddress higher than block3 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S 6 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; + * default: 0; + * category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of + * SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, + * configured as 0x11, else if splitaddress higher than block2 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; + * default: 0; + * category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of + * SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, + * configured as 0x11, else if splitaddress higher than block1 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; + * default: 0; + * category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of + * SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, + * configured as 0x11, else if splitaddress higher than block0 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG register + * sram split line configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0xd4) + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; + * default: 0; + * splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of + * actual address + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x000000ff +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0x000000ff +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W; bitpos: [13:12]; + * default: 0; + * category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of + * SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, + * configured as 0x11, else if splitaddress higher than block6 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S 12 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W; bitpos: [11:10]; + * default: 0; + * category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of + * SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, + * configured as 0x11, else if splitaddress higher than block5 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S 10 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W; bitpos: [9:8]; + * default: 0; + * category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of + * SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, + * configured as 0x11, else if splitaddress higher than block4 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S 8 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W; bitpos: [7:6]; + * default: 0; + * category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of + * SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, + * configured as 0x11, else if splitaddress higher than block3 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S 6 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; + * default: 0; + * category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of + * SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, + * configured as 0x11, else if splitaddress higher than block2 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; + * default: 0; + * category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of + * SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, + * configured as 0x11, else if splitaddress higher than block1 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 + +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; + * default: 0; + * category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of + * SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, + * configured as 0x11, else if splitaddress higher than block0 of SRAM, + * configured as 0x00 + */ + +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG register + * corex iram0 permission configuration register 0 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xd8) + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock corex iram0 permission configuration register + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG register + * corex iram0 permission configuration register 0 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xdc) + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: + * [20:18]; default: 7; + * core0/core1's permission of rom in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [17:15]; default: 7; + * core0/core1's permission of icache data sram block1 in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 15 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [14:12]; default: 7; + * core0/core1's permission of icache data sram block0 in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: + * [11:9]; default: 7; + * core0/core1's permission of instruction region3 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: + * [8:6]; default: 7; + * core0/core1's permission of instruction region2 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: + * [5:3]; default: 7; + * core0/core1's permission of instruction region1 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: + * [2:0]; default: 7; + * core0/core1's permission of instruction region0 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG register + * corex iram0 permission configuration register 1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xe0) + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: + * [20:18]; default: 7; + * core0/core1's permission of rom in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [17:15]; default: 7; + * core0/core1's permission of icache data sram block1 in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 15 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [14:12]; default: 7; + * core0/core1's permission of icache data sram block0 in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: + * [11:9]; default: 7; + * core0/core1's permission of instruction region3 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: + * [8:6]; default: 7; + * core0/core1's permission of instruction region2 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: + * [5:3]; default: 7; + * core0/core1's permission of instruction region1 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 + +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: + * [2:0]; default: 7; + * core0/core1's permission of instruction region0 of SRAM in world1 + */ + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG register + * core0 iram0 permission monitor configuration register 0 + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xe4) + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 iram0 permission monitor register + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG register + * core0 iram0 permission monitor configuration register 1 + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xe8) + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable core0 iram0 permission monitor, when core0_iram violated + * permission, will trigger interrupt + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear core0 iram0 permission violated interrupt + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG register + * core0 iram0 permission monitor configuration register 2 + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xec) + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: + * [28:5]; default: 0; + * recorded core0 iram0 address [25:2] status when core0 iram0 violated + * permission, the real address is 0x40000000+addr*4 + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00ffffff +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x00ffffff +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: + * [4:3]; default: 0; + * recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1. + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO; bitpos: + * [2]; default: 0; + * recorded core0 iram0 loadstore status, indicated the type of operation, + * 0(fetch), 1(load/store). + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [1]; + * default: 0; + * recorded core0 iram0 wr status, only if loadstore is 1 have meaning, + * 1(store), 0(load). + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 + +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * recorded core0 iram0 pms monitor interrupt status. + */ + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG register + * core1 iram0 permission monitor configuration register 0 + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xf0) + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 iram0 permission monitor register + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG register + * core1 iram0 permission monitor configuration register 1 + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xf4) + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable core1 iram0 permission monitor, when core1_iram violated + * permission, will trigger interrupt + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear core1 iram0 permission violated interrupt + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG register + * core1 iram0 permission monitor configuration register 2 + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xf8) + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: + * [28:5]; default: 0; + * recorded core1 iram0 address [25:2] status when core1 iram0 violated + * permission, the real address is 0x40000000+addr*4 + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00ffffff +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x00ffffff +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: + * [4:3]; default: 0; + * recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1. + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO; bitpos: + * [2]; default: 0; + * recorded core1 iram0 loadstore status, indicated the type of operation, + * 0(fetch), 1(load/store). + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [1]; + * default: 0; + * recorded core1 iram0 wr status, only if loadstore is 1 have meaning, + * 1(store), 0(load). + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 + +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * recorded core1 iram0 pms monitor interrupt status. + */ + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG register + * corex dram0 permission configuration register 0 + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xfc) + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock corex dram0 permission configuration register + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG register + * corex dram0 permission configuration register 1 + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x100) + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: + * [27:26]; default: 3; + * core0/core1's permission(sotre,load) of rom in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: + * [25:24]; default: 3; + * core0/core1's permission(sotre,load) of rom in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [23:22]; default: 3; + * core0/core1's permission of dcache data sram block1 in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [21:20]; default: 3; + * core0/core1's permission of dcache data sram block0 in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: + * [19:18]; default: 3; + * core0/core1's permission of data region3 of SRAM in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: + * [17:16]; default: 3; + * core0/core1's permission of data region2 of SRAM in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: + * [15:14]; default: 3; + * core0/core1's permission of data region1 of SRAM in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: + * [13:12]; default: 3; + * core0/core1's permission of data region0 of SRAM in world1. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : + * R/W; bitpos: [11:10]; default: 3; + * core0/core1's permission of dcache data sram block1 in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : + * R/W; bitpos: [9:8]; default: 3; + * core0/core1's permission of dcache data sram block0 in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: + * [7:6]; default: 3; + * core0/core1's permission of data region3 of SRAM in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: + * [5:4]; default: 3; + * core0/core1's permission of data region2 of SRAM in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: + * [3:2]; default: 3; + * core0/core1's permission of data region1 of SRAM in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 + +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: + * [1:0]; default: 3; + * core0/core1's permission of data region0 of SRAM in world0. + */ + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG register + * core0 dram0 permission monitor configuration register 0 + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x104) + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 dram0 permission monitor configuration register. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG register + * core0 dram0 permission monitor configuration register 1 + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x108) + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable core0 dram0 permission monitor interrupt. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear core0 dram0 permission monior interrupt. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG register + * core0 dram0 permission monitor configuration register 2. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x10c) + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: + * [25:4]; default: 0; + * recorded core0 dram0 address[25:4] status when core0 dram0 violated + * permission,the real address is 0x3c000000+addr*16 + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003fffff +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x003fffff +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: + * [3:2]; default: 0; + * recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO; bitpos: [1]; + * default: 0; + * recorded core0 dram0 lock status, 1 means s32c1i access. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * recorded core0 dram0 permission monitor interrupt status. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG register + * core0 dram0 permission monitor configuration register 3. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x110) + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: + * [16:1]; default: 0; + * recorded core0 dram0 byteen status. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000ffff +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0x0000ffff +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 + +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; + * default: 0; + * recorded core0 dram0 wr status, 1 means store, 0 means load. + */ + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG register + * core1 dram0 permission monitor configuration register 0 + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x114) + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 dram0 permission monitor configuration register. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG register + * core1 dram0 permission monitor configuration register 1 + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x118) + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable core1 dram0 permission monitor interrupt. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear core1 dram0 permission monior interrupt. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG register + * core1 dram0 permission monitor configuration register 2. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x11c) + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: + * [25:4]; default: 0; + * recorded core1 dram0 address[25:4] status when core1 dram0 violated + * permission,the real address is 0x3c000000+addr*16 + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003fffff +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x003fffff +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: + * [3:2]; default: 0; + * recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x00000003 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO; bitpos: [1]; + * default: 0; + * recorded core1 dram0 lock status, 1 means s32c1i access. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * recorded core1 dram0 permission monitor interrupt status. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG register + * core1 dram0 permission monitor configuration register 3. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x120) + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: + * [16:1]; default: 0; + * recorded core1 dram0 byteen status. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000ffff +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0x0000ffff +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 + +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; + * default: 0; + * recorded core1 dram0 wr status, 1 means store, 0 means load. + */ + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x00000001 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG register + * Core0 access peripherals permission configuration register 0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 access peripherals permission Configuration Register. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG register + * Core0 access peripherals permission configuration register 1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W; bitpos: [31:30]; + * default: 3; + * Core0 access uart1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access i2s0 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W; bitpos: [27:26]; + * default: 3; + * Core0 access i2c permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W; bitpos: [25:24]; + * default: 3; + * Core0 access misc permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W; bitpos: [21:20]; + * default: 3; + * Core0 access hinf permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access io_mux permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access rtc permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access fe permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access fe2 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access gpio permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access g0spi_0 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access g0spi_1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access uart permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG register + * Core0 access peripherals permission configuration register 2. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12c) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W; bitpos: + * [31:30]; default: 3; + * Core0 access systimer permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W; bitpos: + * [29:28]; default: 3; + * Core0 access timergroup1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W; bitpos: + * [27:26]; default: 3; + * Core0 access timergroup permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W; bitpos: [25:24]; + * default: 3; + * Core0 access pwm0 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W; bitpos: [23:22]; + * default: 3; + * Core0 access bb permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W; bitpos: [19:18]; + * default: 3; + * Core0 access backup permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S 18 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access ledc permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access slc permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access pcnt permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access rmt permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access slchost permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access uhci0 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access i2c_ext0 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access bt permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG register + * Core0 access peripherals permission configuration register 3. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access pwr permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W; bitpos: + * [27:26]; default: 3; + * Core0 access wifimac permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W; bitpos: [23:22]; + * default: 3; + * Core0 access rwbt permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access uart2 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access i2s1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access pwm1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access can permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W; bitpos: + * [9:8]; default: 3; + * Core0 access sdio_host permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access i2c_ext1 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access apb_ctrl permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access spi_3 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access spi_2 permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG register + * Core0 access peripherals permission configuration register 4. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W; + * bitpos: [31:30]; default: 3; + * Core0 access world_controller permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access dio permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W; bitpos: [27:26]; + * default: 3; + * Core0 access ad permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W; bitpos: + * [25:24]; default: 3; + * Core0 access cache_config permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W; bitpos: + * [23:22]; default: 3; + * Core0 access dma_copy permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W; bitpos: + * [21:20]; default: 3; + * Core0 access interrupt permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W; bitpos: + * [19:18]; default: 3; + * Core0 access sensitive permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access system permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access usb permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access bt_pwr permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W; bitpos: + * [11:10]; default: 3; + * Core0 access lcd_cam permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access apb_adc permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W; bitpos: + * [7:6]; default: 3; + * Core0 access crypto_dma permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W; bitpos: + * [5:4]; default: 3; + * Core0 access crypto_peri permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access usb_wrap permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W; bitpos: + * [1:0]; default: 3; + * Core0 access usb_device permission in world0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG register + * Core0 access peripherals permission configuration register 5. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W; bitpos: [31:30]; + * default: 3; + * Core0 access uart1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access i2s0 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W; bitpos: [27:26]; + * default: 3; + * Core0 access i2c permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W; bitpos: [25:24]; + * default: 3; + * Core0 access misc permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W; bitpos: [21:20]; + * default: 3; + * Core0 access hinf permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access io_mux permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access rtc permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access fe permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access fe2 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access gpio permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access g0spi_0 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access g0spi_1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access uart permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG register + * Core0 access peripherals permission configuration register 6. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13c) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W; bitpos: + * [31:30]; default: 3; + * Core0 access systimer permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W; bitpos: + * [29:28]; default: 3; + * Core0 access timergroup1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W; bitpos: + * [27:26]; default: 3; + * Core0 access timergroup permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W; bitpos: [25:24]; + * default: 3; + * Core0 access pwm0 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W; bitpos: [23:22]; + * default: 3; + * Core0 access bb permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W; bitpos: [19:18]; + * default: 3; + * Core0 access backup permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S 18 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access ledc permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access slc permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access pcnt permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access rmt permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access slchost permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access uhci0 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access i2c_ext0 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access bt permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG register + * Core0 access peripherals permission configuration register 7. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access pwr permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W; bitpos: + * [27:26]; default: 3; + * Core0 access wifimac permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W; bitpos: [23:22]; + * default: 3; + * Core0 access rwbt permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access uart2 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access i2s1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access pwm1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W; bitpos: [11:10]; + * default: 3; + * Core0 access can permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W; bitpos: + * [9:8]; default: 3; + * Core0 access sdio_host permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W; bitpos: [7:6]; + * default: 3; + * Core0 access i2c_ext1 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W; bitpos: [5:4]; + * default: 3; + * Core0 access apb_ctrl permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access spi_3 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W; bitpos: [1:0]; + * default: 3; + * Core0 access spi_2 permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG register + * Core0 access peripherals permission configuration register 8. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W; + * bitpos: [31:30]; default: 3; + * Core0 access world_controller permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W; bitpos: [29:28]; + * default: 3; + * Core0 access dio permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W; bitpos: [27:26]; + * default: 3; + * Core0 access ad permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W; bitpos: + * [25:24]; default: 3; + * Core0 access cache_config permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W; bitpos: + * [23:22]; default: 3; + * Core0 access dma_copy permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W; bitpos: + * [21:20]; default: 3; + * Core0 access interrupt permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W; bitpos: + * [19:18]; default: 3; + * Core0 access sensitive permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W; bitpos: [17:16]; + * default: 3; + * Core0 access system permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W; bitpos: [15:14]; + * default: 3; + * Core0 access usb permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 14 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W; bitpos: [13:12]; + * default: 3; + * Core0 access bt_pwr permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W; bitpos: + * [11:10]; default: 3; + * Core0 access lcd_cam permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W; bitpos: [9:8]; + * default: 3; + * Core0 access apb_adc permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W; bitpos: + * [7:6]; default: 3; + * Core0 access crypto_dma permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W; bitpos: + * [5:4]; default: 3; + * Core0 access crypto_peri permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W; bitpos: [3:2]; + * default: 3; + * Core0 access usb_wrap permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W; bitpos: + * [1:0]; default: 3; + * Core0 access usb_device permission in world1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG register + * Core0 access peripherals permission configuration register 9. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCFast memory split address in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCFast memory split address in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG register + * Core0 access peripherals permission configuration register 10. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14c) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCFast memory high region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCFast memory low region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCFast memory high region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCFast memory low region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG register + * Core0 access peripherals permission configuration register 11. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x150) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCSlow_0 memory split address in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCSlow_0 memory split address in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG register + * Core0 access peripherals permission configuration register 12. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x154) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCSlow_0 memory high region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCSlow_0 memory low region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCSlow_0 memory high region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCSlow_0 memory low region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG register + * Core0 access peripherals permission configuration register 13. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x158) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCSlow_1 memory split address in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCSlow_1 memory split address in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG register + * Core0 access peripherals permission configuration register 14. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x15c) + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCSlow_1 memory high region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCSlow_1 memory low region permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCSlow_1 memory high region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCSlow_1 memory low region permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG register + * Core0 region permission register 0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x160) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 region permission registers. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG register + * Core0 region permission register 1. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x164) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W; bitpos: + * [21:20]; default: 3; + * Region 10 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S 20 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W; bitpos: + * [19:18]; default: 3; + * Region 9 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S 18 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W; bitpos: + * [17:16]; default: 3; + * Region 8 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S 16 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W; bitpos: + * [15:14]; default: 3; + * Region 7 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S 14 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W; bitpos: + * [13:12]; default: 3; + * Region 6 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W; bitpos: + * [11:10]; default: 3; + * Region 5 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W; bitpos: + * [9:8]; default: 3; + * Region 4 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W; bitpos: + * [7:6]; default: 3; + * Region 3 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W; bitpos: + * [5:4]; default: 3; + * Region 2 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W; bitpos: + * [3:2]; default: 3; + * Region 1 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W; bitpos: + * [1:0]; default: 3; + * Region 0 permission in world 0 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG register + * Core0 region permission register 2. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x168) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W; bitpos: + * [21:20]; default: 3; + * Region 10 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S 20 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W; bitpos: + * [19:18]; default: 3; + * Region 9 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S 18 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W; bitpos: + * [17:16]; default: 3; + * Region 8 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S 16 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W; bitpos: + * [15:14]; default: 3; + * Region 7 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S 14 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W; bitpos: + * [13:12]; default: 3; + * Region 6 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W; bitpos: + * [11:10]; default: 3; + * Region 5 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W; bitpos: + * [9:8]; default: 3; + * Region 4 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W; bitpos: + * [7:6]; default: 3; + * Region 3 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W; bitpos: + * [5:4]; default: 3; + * Region 2 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W; bitpos: + * [3:2]; default: 3; + * Region 1 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W; bitpos: + * [1:0]; default: 3; + * Region 0 permission in world 1 for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x00000003 +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG register + * Core0 region permission register 3. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x16c) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 : R/W; bitpos: [29:0]; + * default: 0; + * Region 0 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG register + * Core0 region permission register 4. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x170) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 : R/W; bitpos: [29:0]; + * default: 0; + * Region 0 end address and Region 1 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG register + * Core0 region permission register 5. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x174) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 : R/W; bitpos: [29:0]; + * default: 0; + * Region 1 end address and Region 2 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG register + * Core0 region permission register 6. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x178) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 : R/W; bitpos: [29:0]; + * default: 0; + * Region 2 end address and Region 3 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG register + * Core0 region permission register 7. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x17c) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 : R/W; bitpos: [29:0]; + * default: 0; + * Region 3 end address and Region 4 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG register + * Core0 region permission register 8. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x180) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 : R/W; bitpos: [29:0]; + * default: 0; + * Region 4 end address and Region 5 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG register + * Core0 region permission register 9. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x184) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 : R/W; bitpos: [29:0]; + * default: 0; + * Region 5 end address and Region 6 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG register + * Core0 region permission register 10. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x188) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 : R/W; bitpos: [29:0]; + * default: 0; + * Region 6 end address and Region 7 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG register + * Core0 region permission register 11. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x18c) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 : R/W; bitpos: [29:0]; + * default: 0; + * Region 7 end address and Region 8 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG register + * Core0 region permission register 12. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x190) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 : R/W; bitpos: [29:0]; + * default: 0; + * Region 8 end address and Region 9 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG register + * Core0 region permission register 13. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x194) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 : R/W; bitpos: [29:0]; + * default: 0; + * Region 9 end address and Region 10 start address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S 0 + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG register + * Core0 region permission register 14. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x198) + +/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 : R/W; bitpos: [29:0]; + * default: 0; + * Region 10 end address for core0. + */ + +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_M (SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V << SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S) +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V 0x3fffffff +#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG register + * Core0 permission report register 0. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x19c) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 permission report registers. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG register + * Core0 permission report register 1. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x1a0) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: + * 1; + * Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: + * 1; + * Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG register + * Core0 permission report register 2. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x1a4) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO; bitpos: + * [7:6]; default: 0; + * Record world information when core0 initiate illegal access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [5]; + * default: 0; + * Record access direction when core0 initiate illegal access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: + * [4:2]; default: 0; + * Record access type when core0 initate illegal access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO; bitpos: + * [1]; default: 0; + * Record hport information when core0 initiate illegal access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: + * 0; + * Record core0 illegal access interrupt state. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG register + * Core0 permission report register 3. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x1a8) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO; bitpos: + * [31:0]; default: 0; + * Record address information when core0 initiate illegal access. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xffffffff +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xffffffff +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG register + * Core0 permission report register 4. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x1ac) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable interrupt that core0 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear interrupt that core0 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG register + * Core0 permission report register 5. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x1b0) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO; + * bitpos: [4:3]; default: 0; + * Record world information when core0 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; + * bitpos: [2:1]; default: 0; + * Record access type when core0 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * Record core0 unsupported access type interrupt state. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG register + * Core0 permission report register 6. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x1b4) + +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; + * bitpos: [31:0]; default: 0; + * Record address information when core0 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xffffffff +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xffffffff +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG register + * core0 vecbase override configuration register 0 + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x1b8) + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core0 vecbase configuration register + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M (SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V << SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S 0 + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG register + * core0 vecbase override configuration register 0 + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1bc) + +/* SENSITIVE_CORE_0_VECBASE_WORLD_MASK : R/W; bitpos: [0]; default: 1; + * Set 1 to mask world, then only world0_value will work. + */ + +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M (SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V << SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S) +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V 0x00000001 +#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S 0 + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG register + * core0 vecbase override configuration register 1 + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1c0) + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W; bitpos: [23:22]; default: 0; + * Set 0x3 to sel vecbase_override to override vecbase register. + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M (SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V << SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V 0x00000003 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S 22 + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE : R/W; bitpos: [21:0]; + * default: 0; + * world0 vecbase_override register, when core0 in world0 use this register + * to override vecbase register. + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE 0x003fffff +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M (SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V << SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V 0x003fffff +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S 0 + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG register + * core0 vecbase override configuration register 1 + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG (DR_REG_SENSITIVE_BASE + 0x1c4) + +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE : R/W; bitpos: [21:0]; + * default: 0; + * world1 vecbase_override register, when core0 in world1 use this register + * to override vecbase register. + */ + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE 0x003fffff +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M (SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V << SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V 0x003fffff +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S 0 + +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG register + * core0 toomanyexception override configuration register 0. + */ + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1c8) + +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock core0 toomanyexception override configuration register + */ + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V << SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x00000001 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 + +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG register + * core0 toomanyexception override configuration register 1. + */ + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1cc) + +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W; bitpos: [0]; + * default: 1; + * Set 1 to mask toomanyexception. + */ + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M (SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V << SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x00000001 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG register + * Core1 access peripherals permission configuration register 0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x1d0) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 pif permission configuration register. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG register + * Core1 access peripherals permission configuration register 1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x1d4) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W; bitpos: [31:30]; + * default: 3; + * Core1 access uart1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access i2s0 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W; bitpos: [27:26]; + * default: 3; + * Core1 access i2c permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W; bitpos: [25:24]; + * default: 3; + * Core1 access misc permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W; bitpos: [21:20]; + * default: 3; + * Core1 access hinf permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access io_mux permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access rtc permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access fe permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access fe2 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access gpio permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access g0spi_0 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access g0spi_1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access uart permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG register + * Core1 access peripherals permission configuration register 2. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x1d8) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W; bitpos: + * [31:30]; default: 3; + * Core1 access systimer permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W; bitpos: + * [29:28]; default: 3; + * Core1 access timergroup1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W; bitpos: + * [27:26]; default: 3; + * Core1 access timergroup permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W; bitpos: [25:24]; + * default: 3; + * Core1 access pwm0 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W; bitpos: [23:22]; + * default: 3; + * Core1 access bb permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W; bitpos: [19:18]; + * default: 3; + * Core1 access backup permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S 18 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access ledc permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access slc permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access pcnt permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access rmt permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access slchost permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access uhci0 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access i2c_ext0 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access bt permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG register + * Core1 access peripherals permission configuration register 3. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x1dc) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access pwr permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W; bitpos: + * [27:26]; default: 3; + * Core1 access wifimac permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W; bitpos: [23:22]; + * default: 3; + * Core1 access rwbt permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access uart2 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access i2s1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access pwm1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access can permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W; bitpos: + * [9:8]; default: 3; + * Core1 access sdio_host permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access i2c_ext1 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access apb_ctrl permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access spi_3 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access spi_2 permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG register + * Core1 access peripherals permission configuration register 4. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x1e0) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W; + * bitpos: [31:30]; default: 3; + * Core1 access world_controller permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access dio permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W; bitpos: [27:26]; + * default: 3; + * Core1 access ad permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W; bitpos: + * [25:24]; default: 3; + * Core1 access cache_config permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W; bitpos: + * [23:22]; default: 3; + * Core1 access dma_copy permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W; bitpos: + * [21:20]; default: 3; + * Core1 access interrupt permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 20 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W; bitpos: + * [19:18]; default: 3; + * Core1 access sensitive permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 18 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access system permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access usb permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access bt_pwr permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W; bitpos: + * [11:10]; default: 3; + * Core1 access lcd_cam permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access apb_adc permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W; bitpos: + * [7:6]; default: 3; + * Core1 access crypto_dma permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W; bitpos: + * [5:4]; default: 3; + * Core1 access crypto_peri permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access usb_wrap permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W; bitpos: + * [1:0]; default: 3; + * Core1 access usb_device permission in world0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG register + * Core1 access peripherals permission configuration register 5. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x1e4) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W; bitpos: [31:30]; + * default: 3; + * Core1 access uart1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access i2s0 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W; bitpos: [27:26]; + * default: 3; + * Core1 access i2c permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W; bitpos: [25:24]; + * default: 3; + * Core1 access misc permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W; bitpos: [21:20]; + * default: 3; + * Core1 access hinf permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access io_mux permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access rtc permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access fe permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access fe2 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access gpio permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access g0spi_0 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access g0spi_1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access uart permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG register + * Core1 access peripherals permission configuration register 6. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x1e8) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W; bitpos: + * [31:30]; default: 3; + * Core1 access systimer permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W; bitpos: + * [29:28]; default: 3; + * Core1 access timergroup1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W; bitpos: + * [27:26]; default: 3; + * Core1 access timergroup permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W; bitpos: [25:24]; + * default: 3; + * Core1 access pwm0 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W; bitpos: [23:22]; + * default: 3; + * Core1 access bb permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W; bitpos: [19:18]; + * default: 3; + * Core1 access backup permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S 18 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access ledc permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access slc permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access pcnt permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access rmt permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access slchost permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access uhci0 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access i2c_ext0 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access bt permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG register + * Core1 access peripherals permission configuration register 7. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x1ec) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access pwr permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W; bitpos: + * [27:26]; default: 3; + * Core1 access wifimac permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W; bitpos: [23:22]; + * default: 3; + * Core1 access rwbt permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access uart2 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access i2s1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access pwm1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W; bitpos: [11:10]; + * default: 3; + * Core1 access can permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W; bitpos: + * [9:8]; default: 3; + * Core1 access sdio_host permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W; bitpos: [7:6]; + * default: 3; + * Core1 access i2c_ext1 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W; bitpos: [5:4]; + * default: 3; + * Core1 access apb_ctrl permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access spi_3 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W; bitpos: [1:0]; + * default: 3; + * Core1 access spi_2 permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG register + * Core1 access peripherals permission configuration register 8. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x1f0) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W; + * bitpos: [31:30]; default: 3; + * Core1 access world_controller permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 30 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W; bitpos: [29:28]; + * default: 3; + * Core1 access dio permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 28 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W; bitpos: [27:26]; + * default: 3; + * Core1 access ad permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 26 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W; bitpos: + * [25:24]; default: 3; + * Core1 access cache_config permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 24 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W; bitpos: + * [23:22]; default: 3; + * Core1 access dma_copy permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 22 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W; bitpos: + * [21:20]; default: 3; + * Core1 access interrupt permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 20 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W; bitpos: + * [19:18]; default: 3; + * Core1 access sensitive permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 18 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W; bitpos: [17:16]; + * default: 3; + * Core1 access system permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 16 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W; bitpos: [15:14]; + * default: 3; + * Core1 access usb permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 14 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W; bitpos: [13:12]; + * default: 3; + * Core1 access bt_pwr permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S 12 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W; bitpos: + * [11:10]; default: 3; + * Core1 access lcd_cam permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W; bitpos: [9:8]; + * default: 3; + * Core1 access apb_adc permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W; bitpos: + * [7:6]; default: 3; + * Core1 access crypto_dma permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W; bitpos: + * [5:4]; default: 3; + * Core1 access crypto_peri permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W; bitpos: [3:2]; + * default: 3; + * Core1 access usb_wrap permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W; bitpos: + * [1:0]; default: 3; + * Core1 access usb_device permission in world1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG register + * Core1 access peripherals permission configuration register 9. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x1f4) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCFast memory split address in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCFast memory split address in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG register + * core1 access peripherals permission configuration register 10. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x1f8) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCFast memory high region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCFast memory low region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCFast memory high region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCFast memory low region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG register + * core1 access peripherals permission configuration register 11. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x1fc) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCSlow_0 memory split address in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCSlow_0 memory split address in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG register + * core1 access peripherals permission configuration register 12. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x200) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCSlow_0 memory high region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCSlow_0 memory low region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCSlow_0 memory high region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCSlow_0 memory low region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG register + * core1 access peripherals permission configuration register 13. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x204) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W; + * bitpos: [21:11]; default: 2047; + * RTCSlow_1 memory split address in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W; + * bitpos: [10:0]; default: 2047; + * RTCSlow_1 memory split address in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x000007ff +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG register + * core1 access peripherals permission configuration register 14. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x208) + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W; bitpos: + * [11:9]; default: 7; + * RTCSlow_1 memory high region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W; bitpos: + * [8:6]; default: 7; + * RTCSlow_1 memory low region permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W; bitpos: + * [5:3]; default: 7; + * RTCSlow_1 memory high region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 + +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W; bitpos: + * [2:0]; default: 7; + * RTCSlow_1 memory low region permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V << SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG register + * core1 region permission register 0. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x20c) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 region permission registers. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG register + * core1 region permission register 1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x210) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W; bitpos: + * [21:20]; default: 3; + * Region 10 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S 20 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W; bitpos: + * [19:18]; default: 3; + * Region 9 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S 18 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W; bitpos: + * [17:16]; default: 3; + * Region 8 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S 16 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W; bitpos: + * [15:14]; default: 3; + * Region 7 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S 14 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W; bitpos: + * [13:12]; default: 3; + * Region 6 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S 12 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W; bitpos: + * [11:10]; default: 3; + * Region 5 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S 10 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W; bitpos: + * [9:8]; default: 3; + * Region 4 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S 8 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W; bitpos: + * [7:6]; default: 3; + * Region 3 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S 6 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W; bitpos: + * [5:4]; default: 3; + * Region 2 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S 4 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W; bitpos: + * [3:2]; default: 3; + * Region 1 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S 2 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W; bitpos: + * [1:0]; default: 3; + * Region 0 permission in world 0 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG register + * core1 region permission register 2. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x214) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W; bitpos: + * [21:20]; default: 3; + * Region 10 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S 20 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W; bitpos: + * [19:18]; default: 3; + * Region 9 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S 18 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W; bitpos: + * [17:16]; default: 3; + * Region 8 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S 16 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W; bitpos: + * [15:14]; default: 3; + * Region 7 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S 14 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W; bitpos: + * [13:12]; default: 3; + * Region 6 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S 12 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W; bitpos: + * [11:10]; default: 3; + * Region 5 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S 10 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W; bitpos: + * [9:8]; default: 3; + * Region 4 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S 8 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W; bitpos: + * [7:6]; default: 3; + * Region 3 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S 6 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W; bitpos: + * [5:4]; default: 3; + * Region 2 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S 4 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W; bitpos: + * [3:2]; default: 3; + * Region 1 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S 2 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W; bitpos: + * [1:0]; default: 3; + * Region 0 permission in world 1 for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V 0x00000003 +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG register + * core1 region permission register 3. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x218) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 : R/W; bitpos: [29:0]; + * default: 0; + * Region 0 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG register + * core1 region permission register 4. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x21c) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 : R/W; bitpos: [29:0]; + * default: 0; + * Region 0 end address and Region 1 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG register + * core1 region permission register 5. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x220) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 : R/W; bitpos: [29:0]; + * default: 0; + * Region 1 end address and Region 2 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG register + * core1 region permission register 6. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x224) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 : R/W; bitpos: [29:0]; + * default: 0; + * Region 2 end address and Region 3 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG register + * core1 region permission register 7. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x228) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 : R/W; bitpos: [29:0]; + * default: 0; + * Region 3 end address and Region 4 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG register + * core1 region permission register 8. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x22c) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 : R/W; bitpos: [29:0]; + * default: 0; + * Region 4 end address and Region 5 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG register + * core1 region permission register 9. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x230) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 : R/W; bitpos: [29:0]; + * default: 0; + * Region 5 end address and Region 6 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG register + * core1 region permission register 10. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x234) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 : R/W; bitpos: [29:0]; + * default: 0; + * Region 6 end address and Region 7 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG register + * core1 region permission register 11. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x238) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 : R/W; bitpos: [29:0]; + * default: 0; + * Region 7 end address and Region 8 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG register + * core1 region permission register 12. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x23c) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 : R/W; bitpos: [29:0]; + * default: 0; + * Region 8 end address and Region 9 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG register + * core1 region permission register 13. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x240) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 : R/W; bitpos: [29:0]; + * default: 0; + * Region 9 end address and Region 10 start address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S 0 + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG register + * core1 region permission register 14. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x244) + +/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 : R/W; bitpos: [29:0]; + * default: 0; + * Region 10 end address for core1. + */ + +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_M (SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V << SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S) +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V 0x3fffffff +#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG register + * core1 permission report register 0. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x248) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 permission report registers. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG register + * core1 permission report register 1. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x24c) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: + * 1; + * Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: + * 1; + * Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG register + * core1 permission report register 2. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x250) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO; bitpos: + * [7:6]; default: 0; + * Record world information when core1 initiate illegal access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [5]; + * default: 0; + * Record access direction when core1 initiate illegal access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: + * [4:2]; default: 0; + * Record access type when core1 initate illegal access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO; bitpos: + * [1]; default: 0; + * Record hport information when core1 initiate illegal access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: + * 0; + * Record core1 illegal access interrupt state. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG register + * core1 permission report register 3. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x254) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO; bitpos: + * [31:0]; default: 0; + * Record address information when core1 initiate illegal access. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xffffffff +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xffffffff +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG register + * core1 permission report register 4. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x258) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; + * default: 1; + * Set 1 to enable interrupt that core1 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; + * default: 1; + * Set 1 to clear interrupt that core1 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG register + * core1 permission report register 5. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x25c) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO; + * bitpos: [4:3]; default: 0; + * Record world information when core1 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; + * bitpos: [2:1]; default: 0; + * Record access type when core1 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; + * default: 0; + * Record core1 unsupported access type interrupt state. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG register + * core1 permission report register 6. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x260) + +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; + * bitpos: [31:0]; default: 0; + * Record address information when core1 initiate unsupported access type. + */ + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xffffffff +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xffffffff +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG register + * core1 vecbase override configuration register 0 + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x264) + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock core1 vecbase configuration register + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M (SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V << SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S 0 + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG register + * core1 vecbase override configuration register 0 + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x268) + +/* SENSITIVE_CORE_1_VECBASE_WORLD_MASK : R/W; bitpos: [0]; default: 1; + * Set 1 to mask world, then only world0_value will work. + */ + +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M (SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V << SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S) +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V 0x00000001 +#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S 0 + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG register + * core1 vecbase override configuration register 1 + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x26c) + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W; bitpos: [23:22]; default: 0; + * Set 0x3 to sel vecbase_override to override vecbase register. + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M (SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V << SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V 0x00000003 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S 22 + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE : R/W; bitpos: [21:0]; + * default: 0; + * world0 vecbase_override register, when core1 in world0 use this register + * to override vecbase register. + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE 0x003fffff +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_M (SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V << SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V 0x003fffff +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S 0 + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG register + * core1 vecbase override configuration register 1 + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG (DR_REG_SENSITIVE_BASE + 0x270) + +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE : R/W; bitpos: [21:0]; + * default: 0; + * world1 vecbase_override register, when core1 in world1 use this register + * to override vecbase register. + */ + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE 0x003fffff +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M (SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V << SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V 0x003fffff +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S 0 + +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG register + * core1 toomanyexception override configuration register 0. + */ + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x274) + +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W; bitpos: [0]; + * default: 0; + * Set 1 to lock core1 toomanyexception override configuration register + */ + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V << SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x00000001 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 + +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG register + * core1 toomanyexception override configuration register 1. + */ + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x278) + +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W; bitpos: [0]; + * default: 1; + * Set 1 to mask toomanyexception. + */ + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M (SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V << SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x00000001 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG register + * BackUp access peripherals permission configuration register 0. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x27c) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock BackUp permission configuration registers. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG register + * BackUp access peripherals permission configuration register 1. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x280) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W; bitpos: [31:30]; default: + * 3; + * BackUp access uart1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S 30 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W; bitpos: [29:28]; default: + * 3; + * BackUp access i2s0 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S 28 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W; bitpos: [27:26]; default: 3; + * BackUp access i2c permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S 26 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W; bitpos: [25:24]; default: + * 3; + * BackUp access misc permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S 24 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF : R/W; bitpos: [21:20]; default: + * 3; + * BackUp access hinf permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S 20 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W; bitpos: [17:16]; + * default: 3; + * BackUp access io_mux permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S 16 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W; bitpos: [15:14]; default: 3; + * BackUp access rtc permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W; bitpos: [11:10]; default: 3; + * BackUp access fe permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S 10 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W; bitpos: [9:8]; default: 3; + * BackUp access fe2 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S 8 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W; bitpos: [7:6]; default: 3; + * BackUp access gpio permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S 6 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W; bitpos: [5:4]; default: + * 3; + * BackUp access g0spi_0 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S 4 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W; bitpos: [3:2]; default: + * 3; + * BackUp access g0spi_1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S 2 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W; bitpos: [1:0]; default: 3; + * BackUp access uart permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG register + * BackUp access peripherals permission configuration register 2. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x284) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W; bitpos: [31:30]; + * default: 3; + * BackUp access systimer permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S 30 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W; bitpos: [29:28]; + * default: 3; + * BackUp access timergroup1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S 28 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W; bitpos: [27:26]; + * default: 3; + * BackUp access timergroup permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S 26 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 : R/W; bitpos: [25:24]; default: + * 3; + * BackUp access pwm0 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S 24 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W; bitpos: [23:22]; default: 3; + * BackUp access bb permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S 22 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP : R/W; bitpos: [19:18]; + * default: 3; + * BackUp access backup permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S 18 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W; bitpos: [17:16]; default: + * 3; + * BackUp access ledc permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S 16 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC : R/W; bitpos: [15:14]; default: 3; + * BackUp access slc permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S 14 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT : R/W; bitpos: [13:12]; default: + * 3; + * BackUp access pcnt permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S 12 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W; bitpos: [11:10]; default: 3; + * BackUp access rmt permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S 10 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST : R/W; bitpos: [9:8]; default: + * 3; + * BackUp access slchost permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S 8 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W; bitpos: [7:6]; default: 3; + * BackUp access uhci0 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S 6 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W; bitpos: [5:4]; + * default: 3; + * BackUp access i2c_ext0 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S 4 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W; bitpos: [1:0]; default: 3; + * BackUp access bt permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG register + * BackUp access peripherals permission configuration register 3. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x288) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W; bitpos: [29:28]; default: 3; + * BackUp access pwr permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S 28 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W; bitpos: [27:26]; + * default: 3; + * BackUp access wifimac permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S 26 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W; bitpos: [23:22]; default: + * 3; + * BackUp access rwbt permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S 22 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 : R/W; bitpos: [17:16]; default: + * 3; + * BackUp access uart2 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S 16 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W; bitpos: [15:14]; default: + * 3; + * BackUp access i2s1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S 14 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 : R/W; bitpos: [13:12]; default: + * 3; + * BackUp access pwm1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S 12 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W; bitpos: [11:10]; default: 3; + * BackUp access can permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S 10 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST : R/W; bitpos: [9:8]; + * default: 3; + * BackUp access sdio_host permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S 8 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 : R/W; bitpos: [7:6]; + * default: 3; + * BackUp access i2c_ext1 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S 6 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W; bitpos: [5:4]; + * default: 3; + * BackUp access apb_ctrl permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S 4 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 : R/W; bitpos: [3:2]; default: 3; + * BackUp access spi_3 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S 2 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W; bitpos: [1:0]; default: 3; + * BackUp access spi_2 permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG register + * BackUp access peripherals permission configuration register 4. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x28c) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER : R/W; bitpos: + * [31:30]; default: 3; + * BackUp access world_controller permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S 30 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO : R/W; bitpos: [29:28]; default: 3; + * BackUp access dio permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S 28 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD : R/W; bitpos: [27:26]; default: 3; + * BackUp access ad permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S 26 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG : R/W; bitpos: [25:24]; + * default: 3; + * BackUp access cache_config permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S 24 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY : R/W; bitpos: [23:22]; + * default: 3; + * BackUp access dma_copy permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S 22 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT : R/W; bitpos: [21:20]; + * default: 3; + * BackUp access interrupt permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S 20 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE : R/W; bitpos: [19:18]; + * default: 3; + * BackUp access sensitive permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S 18 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM : R/W; bitpos: [17:16]; + * default: 3; + * BackUp access system permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S 16 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB : R/W; bitpos: [15:14]; default: 3; + * BackUp access usb permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S 14 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W; bitpos: [13:12]; + * default: 3; + * BackUp access bt_pwr permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S 12 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM : R/W; bitpos: [11:10]; + * default: 3; + * BackUp access lcd_cam permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S 10 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W; bitpos: [9:8]; default: + * 3; + * BackUp access apb_adc permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S 8 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W; bitpos: [7:6]; + * default: 3; + * BackUp access crypto_dma permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S 6 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W; bitpos: [5:4]; + * default: 3; + * BackUp access crypto_peri permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S 4 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W; bitpos: [3:2]; + * default: 3; + * BackUp access usb_wrap permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S 2 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W; bitpos: [1:0]; + * default: 3; + * BackUp access usb_device permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG register + * BackUp access peripherals permission configuration register 5. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x290) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR : R/W; bitpos: + * [10:0]; default: 2047; + * BackUp access rtcfast_spltaddr permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR 0x000007ff +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V 0x000007ff +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG register + * BackUp access peripherals permission configuration register 6. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x294) + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H : R/W; bitpos: [5:3]; + * default: 7; + * BackUp access rtcfast_h permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S 3 + +/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L : R/W; bitpos: [2:0]; + * default: 7; + * BackUp access rtcfast_l permission. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S) +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG register + * BackUp permission report register 0. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x298) + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock BackUp permission report registers. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG register + * BackUp permission report register 1. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x29c) + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: + * 1; + * Set 1 to enable interrupt that BackUp initiate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S 1 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: + * 1; + * Set 1 to clear interrupt that BackUp initiate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG register + * BackUp permission report register 2. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x2a0) + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [6]; + * default: 0; + * Record access direction when BackUp initiate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(6)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 6 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: + * [5:3]; default: 0; + * Record access type when BackUp initate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x00000007 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 3 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO; bitpos: + * [2:1]; default: 0; + * Record htrans when BackUp initate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V 0x00000003 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S 1 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: + * 0; + * Record BackUp illegal access interrupt state. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V 0x00000001 +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S 0 + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG register + * BackUp permission report register 3. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x2a4) + +/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO; bitpos: [31:0]; + * default: 0; + * Record address information when BackUp initiate illegal access. + */ + +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR 0xffffffff +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S) +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V 0xffffffff +#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S 0 + +/* SENSITIVE_EDMA_BOUNDARY_LOCK_REG register + * EDMA boundary lock register. + */ + +#define SENSITIVE_EDMA_BOUNDARY_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2a8) + +/* SENSITIVE_EDMA_BOUNDARY_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA boundary registers. + */ + +#define SENSITIVE_EDMA_BOUNDARY_LOCK (BIT(0)) +#define SENSITIVE_EDMA_BOUNDARY_LOCK_M (SENSITIVE_EDMA_BOUNDARY_LOCK_V << SENSITIVE_EDMA_BOUNDARY_LOCK_S) +#define SENSITIVE_EDMA_BOUNDARY_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_BOUNDARY_LOCK_S 0 + +/* SENSITIVE_EDMA_BOUNDARY_0_REG register + * EDMA boundary 0 configuration + */ + +#define SENSITIVE_EDMA_BOUNDARY_0_REG (DR_REG_SENSITIVE_BASE + 0x2ac) + +/* SENSITIVE_EDMA_BOUNDARY_0 : R/W; bitpos: [13:0]; default: 0; + * This field is used to configure the boundary 0 of external RAM. The unit + * is 4K. For example, set this field to 0x80, then the address boundary 0 + * would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + */ + +#define SENSITIVE_EDMA_BOUNDARY_0 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_0_M (SENSITIVE_EDMA_BOUNDARY_0_V << SENSITIVE_EDMA_BOUNDARY_0_S) +#define SENSITIVE_EDMA_BOUNDARY_0_V 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_0_S 0 + +/* SENSITIVE_EDMA_BOUNDARY_1_REG register + * EDMA boundary 1 configuration + */ + +#define SENSITIVE_EDMA_BOUNDARY_1_REG (DR_REG_SENSITIVE_BASE + 0x2b0) + +/* SENSITIVE_EDMA_BOUNDARY_1 : R/W; bitpos: [13:0]; default: 8192; + * This field is used to configure the boundary 1 of external RAM. The unit + * is 4K. For example, set this field to 0x80, then the address boundary 0 + * would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + */ + +#define SENSITIVE_EDMA_BOUNDARY_1 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_1_M (SENSITIVE_EDMA_BOUNDARY_1_V << SENSITIVE_EDMA_BOUNDARY_1_S) +#define SENSITIVE_EDMA_BOUNDARY_1_V 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_1_S 0 + +/* SENSITIVE_EDMA_BOUNDARY_2_REG register + * EDMA boundary 2 configuration + */ + +#define SENSITIVE_EDMA_BOUNDARY_2_REG (DR_REG_SENSITIVE_BASE + 0x2b4) + +/* SENSITIVE_EDMA_BOUNDARY_2 : R/W; bitpos: [13:0]; default: 8192; + * This field is used to configure the boundary 2 of external RAM. The unit + * is 4K. For example, set this field to 0x80, then the address boundary 0 + * would be 0x3C080000 (0x3C000000 + 0x80 * 4K). + */ + +#define SENSITIVE_EDMA_BOUNDARY_2 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_2_M (SENSITIVE_EDMA_BOUNDARY_2_V << SENSITIVE_EDMA_BOUNDARY_2_S) +#define SENSITIVE_EDMA_BOUNDARY_2_V 0x00003fff +#define SENSITIVE_EDMA_BOUNDARY_2_S 0 + +/* SENSITIVE_EDMA_PMS_SPI2_LOCK_REG register + * EDMA-SPI2 permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2b8) + +/* SENSITIVE_EDMA_PMS_SPI2_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-SPI2 permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_SPI2_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_M (SENSITIVE_EDMA_PMS_SPI2_LOCK_V << SENSITIVE_EDMA_PMS_SPI2_LOCK_S) +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_SPI2_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_SPI2_REG register + * EDMA-SPI2 permission control register. + */ + +#define SENSITIVE_EDMA_PMS_SPI2_REG (DR_REG_SENSITIVE_BASE + 0x2bc) + +/* SENSITIVE_EDMA_PMS_SPI2_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of SPI2 accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_M (SENSITIVE_EDMA_PMS_SPI2_ATTR2_V << SENSITIVE_EDMA_PMS_SPI2_ATTR2_S) +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_SPI2_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of SPI2 accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M (SENSITIVE_EDMA_PMS_SPI2_ATTR1_V << SENSITIVE_EDMA_PMS_SPI2_ATTR1_S) +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_SPI3_LOCK_REG register + * EDMA-SPI3 permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2c0) + +/* SENSITIVE_EDMA_PMS_SPI3_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-SPI3 permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_SPI3_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_M (SENSITIVE_EDMA_PMS_SPI3_LOCK_V << SENSITIVE_EDMA_PMS_SPI3_LOCK_S) +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_SPI3_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_SPI3_REG register + * EDMA-SPI3 permission control register. + */ + +#define SENSITIVE_EDMA_PMS_SPI3_REG (DR_REG_SENSITIVE_BASE + 0x2c4) + +/* SENSITIVE_EDMA_PMS_SPI3_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of SPI3 accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_M (SENSITIVE_EDMA_PMS_SPI3_ATTR2_V << SENSITIVE_EDMA_PMS_SPI3_ATTR2_S) +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_SPI3_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of SPI3 accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M (SENSITIVE_EDMA_PMS_SPI3_ATTR1_V << SENSITIVE_EDMA_PMS_SPI3_ATTR1_S) +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG register + * EDMA-UHCI0 permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2c8) + +/* SENSITIVE_EDMA_PMS_UHCI0_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-UHCI0 permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_M (SENSITIVE_EDMA_PMS_UHCI0_LOCK_V << SENSITIVE_EDMA_PMS_UHCI0_LOCK_S) +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_UHCI0_REG register + * EDMA-UHCI0 permission control register. + */ + +#define SENSITIVE_EDMA_PMS_UHCI0_REG (DR_REG_SENSITIVE_BASE + 0x2cc) + +/* SENSITIVE_EDMA_PMS_UHCI0_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of UHCI0 accessing + * address, which is larger than boundary 1 and less than boundary 2, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_M (SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V << SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S) +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_UHCI0_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of UHCI0 accessing + * address, which is larger than boundary 0 and less than boundary 1, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M (SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V << SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S) +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_I2S0_LOCK_REG register + * EDMA-I2S0 permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2d0) + +/* SENSITIVE_EDMA_PMS_I2S0_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-I2S0 permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_I2S0_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_M (SENSITIVE_EDMA_PMS_I2S0_LOCK_V << SENSITIVE_EDMA_PMS_I2S0_LOCK_S) +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_I2S0_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_I2S0_REG register + * EDMA-I2S0 permission control register. + */ + +#define SENSITIVE_EDMA_PMS_I2S0_REG (DR_REG_SENSITIVE_BASE + 0x2d4) + +/* SENSITIVE_EDMA_PMS_I2S0_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of I2S0 accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_M (SENSITIVE_EDMA_PMS_I2S0_ATTR2_V << SENSITIVE_EDMA_PMS_I2S0_ATTR2_S) +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_I2S0_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of I2S0 accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M (SENSITIVE_EDMA_PMS_I2S0_ATTR1_V << SENSITIVE_EDMA_PMS_I2S0_ATTR1_S) +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_I2S1_LOCK_REG register + * EDMA-I2S1 permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2d8) + +/* SENSITIVE_EDMA_PMS_I2S1_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-I2S1 permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_I2S1_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_M (SENSITIVE_EDMA_PMS_I2S1_LOCK_V << SENSITIVE_EDMA_PMS_I2S1_LOCK_S) +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_I2S1_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_I2S1_REG register + * EDMA-I2S1 permission control register. + */ + +#define SENSITIVE_EDMA_PMS_I2S1_REG (DR_REG_SENSITIVE_BASE + 0x2dc) + +/* SENSITIVE_EDMA_PMS_I2S1_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of I2S1 accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_M (SENSITIVE_EDMA_PMS_I2S1_ATTR2_V << SENSITIVE_EDMA_PMS_I2S1_ATTR2_S) +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_I2S1_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of I2S1 accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M (SENSITIVE_EDMA_PMS_I2S1_ATTR1_V << SENSITIVE_EDMA_PMS_I2S1_ATTR1_S) +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG register + * EDMA-LCD/CAM permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2e0) + +/* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-LCD/CAM permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_M (SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V << SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S) +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_LCD_CAM_REG register + * EDMA-LCD/CAM permission control register. + */ + +#define SENSITIVE_EDMA_PMS_LCD_CAM_REG (DR_REG_SENSITIVE_BASE + 0x2e4) + +/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of LCD/CAM accessing + * address, which is larger than boundary 1 and less than boundary 2, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_M (SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V << SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S) +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of LCD/CAM accessing + * address, which is larger than boundary 0 and less than boundary 1, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M (SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V << SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S) +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_AES_LOCK_REG register + * EDMA-AES permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_AES_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2e8) + +/* SENSITIVE_EDMA_PMS_AES_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-AES permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_AES_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_AES_LOCK_M (SENSITIVE_EDMA_PMS_AES_LOCK_V << SENSITIVE_EDMA_PMS_AES_LOCK_S) +#define SENSITIVE_EDMA_PMS_AES_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_AES_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_AES_REG register + * EDMA-AES permission control register. + */ + +#define SENSITIVE_EDMA_PMS_AES_REG (DR_REG_SENSITIVE_BASE + 0x2ec) + +/* SENSITIVE_EDMA_PMS_AES_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of AES accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_AES_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR2_M (SENSITIVE_EDMA_PMS_AES_ATTR2_V << SENSITIVE_EDMA_PMS_AES_ATTR2_S) +#define SENSITIVE_EDMA_PMS_AES_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_AES_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of AES accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_AES_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR1_M (SENSITIVE_EDMA_PMS_AES_ATTR1_V << SENSITIVE_EDMA_PMS_AES_ATTR1_S) +#define SENSITIVE_EDMA_PMS_AES_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_AES_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_SHA_LOCK_REG register + * EDMA-SHA permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_SHA_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2f0) + +/* SENSITIVE_EDMA_PMS_SHA_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-SHA permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_SHA_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_SHA_LOCK_M (SENSITIVE_EDMA_PMS_SHA_LOCK_V << SENSITIVE_EDMA_PMS_SHA_LOCK_S) +#define SENSITIVE_EDMA_PMS_SHA_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_SHA_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_SHA_REG register + * EDMA-SHA permission control register. + */ + +#define SENSITIVE_EDMA_PMS_SHA_REG (DR_REG_SENSITIVE_BASE + 0x2f4) + +/* SENSITIVE_EDMA_PMS_SHA_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of SHA accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SHA_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_M (SENSITIVE_EDMA_PMS_SHA_ATTR2_V << SENSITIVE_EDMA_PMS_SHA_ATTR2_S) +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_SHA_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of SHA accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_SHA_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_M (SENSITIVE_EDMA_PMS_SHA_ATTR1_V << SENSITIVE_EDMA_PMS_SHA_ATTR1_S) +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_SHA_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG register + * EDMA-ADC/DAC permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x2f8) + +/* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-ADC/DAC permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_M (SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V << SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S) +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_ADC_DAC_REG register + * EDMA-ADC/DAC permission control register. + */ + +#define SENSITIVE_EDMA_PMS_ADC_DAC_REG (DR_REG_SENSITIVE_BASE + 0x2fc) + +/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of ADC/DAC accessing + * address, which is larger than boundary 1 and less than boundary 2, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_M (SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V << SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S) +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of ADC/DAC accessing + * address, which is larger than boundary 0 and less than boundary 1, + * through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set + * this bit to enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M (SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V << SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S) +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S 0 + +/* SENSITIVE_EDMA_PMS_RMT_LOCK_REG register + * EDMA-RMT permission lock register. + */ + +#define SENSITIVE_EDMA_PMS_RMT_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x300) + +/* SENSITIVE_EDMA_PMS_RMT_LOCK : R/W; bitpos: [0]; default: 0; + * Set 1 to lock EDMA-RMT permission control registers. + */ + +#define SENSITIVE_EDMA_PMS_RMT_LOCK (BIT(0)) +#define SENSITIVE_EDMA_PMS_RMT_LOCK_M (SENSITIVE_EDMA_PMS_RMT_LOCK_V << SENSITIVE_EDMA_PMS_RMT_LOCK_S) +#define SENSITIVE_EDMA_PMS_RMT_LOCK_V 0x00000001 +#define SENSITIVE_EDMA_PMS_RMT_LOCK_S 0 + +/* SENSITIVE_EDMA_PMS_RMT_REG register + * EDMA-RMT permission control register. + */ + +#define SENSITIVE_EDMA_PMS_RMT_REG (DR_REG_SENSITIVE_BASE + 0x304) + +/* SENSITIVE_EDMA_PMS_RMT_ATTR2 : R/W; bitpos: [3:2]; default: 3; + * This field is used to configure the permission of RMT accessing address, + * which is larger than boundary 1 and less than boundary 2, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_RMT_ATTR2 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_M (SENSITIVE_EDMA_PMS_RMT_ATTR2_V << SENSITIVE_EDMA_PMS_RMT_ATTR2_S) +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_V 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR2_S 2 + +/* SENSITIVE_EDMA_PMS_RMT_ATTR1 : R/W; bitpos: [1:0]; default: 3; + * This field is used to configure the permission of RMT accessing address, + * which is larger than boundary 0 and less than boundary 1, through EDMA. + * Bit 0: set this bit to enable read permission. Bit 1: set this bit to + * enable write permission. + */ + +#define SENSITIVE_EDMA_PMS_RMT_ATTR1 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_M (SENSITIVE_EDMA_PMS_RMT_ATTR1_V << SENSITIVE_EDMA_PMS_RMT_ATTR1_S) +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_V 0x00000003 +#define SENSITIVE_EDMA_PMS_RMT_ATTR1_S 0 + +/* SENSITIVE_CLOCK_GATE_REG_REG register + * Sensitive module clock gate configuration register. + */ + +#define SENSITIVE_CLOCK_GATE_REG_REG (DR_REG_SENSITIVE_BASE + 0x308) + +/* SENSITIVE_REG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable clock gate function. + */ + +#define SENSITIVE_REG_CLK_EN (BIT(0)) +#define SENSITIVE_REG_CLK_EN_M (SENSITIVE_REG_CLK_EN_V << SENSITIVE_REG_CLK_EN_S) +#define SENSITIVE_REG_CLK_EN_V 0x00000001 +#define SENSITIVE_REG_CLK_EN_S 0 + +/* SENSITIVE_RTC_PMS_REG register + * RTC coprocessor permission register. + */ + +#define SENSITIVE_RTC_PMS_REG (DR_REG_SENSITIVE_BASE + 0x30c) + +/* SENSITIVE_DIS_RTC_CPU : R/W; bitpos: [0]; default: 0; + * Set 1 to disable rtc coprocessor. + */ + +#define SENSITIVE_DIS_RTC_CPU (BIT(0)) +#define SENSITIVE_DIS_RTC_CPU_M (SENSITIVE_DIS_RTC_CPU_V << SENSITIVE_DIS_RTC_CPU_S) +#define SENSITIVE_DIS_RTC_CPU_V 0x00000001 +#define SENSITIVE_DIS_RTC_CPU_S 0 + +/* SENSITIVE_DATE_REG register + * Sensitive version register. + */ + +#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc) + +/* SENSITIVE_DATE : R/W; bitpos: [27:0]; default: 34607744; + * Sensitive Date register. + */ + +#define SENSITIVE_DATE 0x0fffffff +#define SENSITIVE_DATE_M (SENSITIVE_DATE_V << SENSITIVE_DATE_S) +#define SENSITIVE_DATE_V 0x0fffffff +#define SENSITIVE_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SENSITIVE_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h index 5959aabf59..cab5e90668 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h @@ -25,8 +25,10 @@ * Included Files ****************************************************************************/ +#ifndef __ASSEMBLY__ #include #include +#endif #include "xtensa_attr.h" @@ -148,6 +150,8 @@ #define BIT(nr) (1UL << (nr)) +#ifndef __ASSEMBLY__ + /* Write value to register */ #define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) @@ -260,6 +264,8 @@ #define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M)) +#endif /* __ASSEMBLY__ */ + /* Peripheral Clock */ #define APB_CLK_FREQ_ROM (40*1000000) @@ -435,6 +441,8 @@ #define RTC_PLL_FREQ_320M 320 #define RTC_PLL_FREQ_480M 480 +#ifndef __ASSEMBLY__ + /**************************************************************************** * Inline Functions ****************************************************************************/ @@ -486,4 +494,6 @@ static inline bool IRAM_ATTR esp32s3_ptr_exec(const void *p) || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); } +#endif /* __ASSEMBLY__ */ + #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h new file mode 100644 index 0000000000..0100e29afa --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h @@ -0,0 +1,1908 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_WCL_CORE_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_WCL_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* WCL_CORE_0_ENTRY_1_ADDR_REG register + * Core_0 Entry 1 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_1_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x0) + +/* WCL_CORE_0_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 1 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_1_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_1_ADDR_M (WCL_CORE_0_ENTRY_1_ADDR_V << WCL_CORE_0_ENTRY_1_ADDR_S) +#define WCL_CORE_0_ENTRY_1_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_1_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_2_ADDR_REG register + * Core_0 Entry 2 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_2_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x4) + +/* WCL_CORE_0_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 2 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_2_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_2_ADDR_M (WCL_CORE_0_ENTRY_2_ADDR_V << WCL_CORE_0_ENTRY_2_ADDR_S) +#define WCL_CORE_0_ENTRY_2_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_2_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_3_ADDR_REG register + * Core_0 Entry 3 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_3_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x8) + +/* WCL_CORE_0_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 3 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_3_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_3_ADDR_M (WCL_CORE_0_ENTRY_3_ADDR_V << WCL_CORE_0_ENTRY_3_ADDR_S) +#define WCL_CORE_0_ENTRY_3_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_3_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_4_ADDR_REG register + * Core_0 Entry 4 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_4_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0xc) + +/* WCL_CORE_0_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 4 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_4_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_4_ADDR_M (WCL_CORE_0_ENTRY_4_ADDR_V << WCL_CORE_0_ENTRY_4_ADDR_S) +#define WCL_CORE_0_ENTRY_4_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_4_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_5_ADDR_REG register + * Core_0 Entry 5 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_5_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x10) + +/* WCL_CORE_0_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 5 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_5_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_5_ADDR_M (WCL_CORE_0_ENTRY_5_ADDR_V << WCL_CORE_0_ENTRY_5_ADDR_S) +#define WCL_CORE_0_ENTRY_5_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_5_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_6_ADDR_REG register + * Core_0 Entry 6 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_6_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x14) + +/* WCL_CORE_0_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 6 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_6_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_6_ADDR_M (WCL_CORE_0_ENTRY_6_ADDR_V << WCL_CORE_0_ENTRY_6_ADDR_S) +#define WCL_CORE_0_ENTRY_6_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_6_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_7_ADDR_REG register + * Core_0 Entry 7 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_7_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x18) + +/* WCL_CORE_0_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 7 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_7_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_7_ADDR_M (WCL_CORE_0_ENTRY_7_ADDR_V << WCL_CORE_0_ENTRY_7_ADDR_S) +#define WCL_CORE_0_ENTRY_7_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_7_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_8_ADDR_REG register + * Core_0 Entry 8 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_8_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x1c) + +/* WCL_CORE_0_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 8 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_8_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_8_ADDR_M (WCL_CORE_0_ENTRY_8_ADDR_V << WCL_CORE_0_ENTRY_8_ADDR_S) +#define WCL_CORE_0_ENTRY_8_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_8_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_9_ADDR_REG register + * Core_0 Entry 9 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_9_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x20) + +/* WCL_CORE_0_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 9 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_9_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_9_ADDR_M (WCL_CORE_0_ENTRY_9_ADDR_V << WCL_CORE_0_ENTRY_9_ADDR_S) +#define WCL_CORE_0_ENTRY_9_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_9_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_10_ADDR_REG register + * Core_0 Entry 10 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_10_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x24) + +/* WCL_CORE_0_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 10 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_10_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_10_ADDR_M (WCL_CORE_0_ENTRY_10_ADDR_V << WCL_CORE_0_ENTRY_10_ADDR_S) +#define WCL_CORE_0_ENTRY_10_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_10_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_11_ADDR_REG register + * Core_0 Entry 11 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_11_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x28) + +/* WCL_CORE_0_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 11 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_11_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_11_ADDR_M (WCL_CORE_0_ENTRY_11_ADDR_V << WCL_CORE_0_ENTRY_11_ADDR_S) +#define WCL_CORE_0_ENTRY_11_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_11_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_12_ADDR_REG register + * Core_0 Entry 12 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_12_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x2c) + +/* WCL_CORE_0_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 12 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_12_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_12_ADDR_M (WCL_CORE_0_ENTRY_12_ADDR_V << WCL_CORE_0_ENTRY_12_ADDR_S) +#define WCL_CORE_0_ENTRY_12_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_12_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_13_ADDR_REG register + * Core_0 Entry 13 address configuration Register + */ + +#define WCL_CORE_0_ENTRY_13_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x30) + +/* WCL_CORE_0_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_0 Entry 13 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_0_ENTRY_13_ADDR 0xffffffff +#define WCL_CORE_0_ENTRY_13_ADDR_M (WCL_CORE_0_ENTRY_13_ADDR_V << WCL_CORE_0_ENTRY_13_ADDR_S) +#define WCL_CORE_0_ENTRY_13_ADDR_V 0xffffffff +#define WCL_CORE_0_ENTRY_13_ADDR_S 0 + +/* WCL_CORE_0_ENTRY_CHECK_REG register + * Core_0 Entry check configuration Register + */ + +#define WCL_CORE_0_ENTRY_CHECK_REG (DR_REG_WORLD_CNTL_BASE + 0x7c) + +/* WCL_CORE_0_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + +#define WCL_CORE_0_ENTRY_CHECK 0x00001fff +#define WCL_CORE_0_ENTRY_CHECK_M (WCL_CORE_0_ENTRY_CHECK_V << WCL_CORE_0_ENTRY_CHECK_S) +#define WCL_CORE_0_ENTRY_CHECK_V 0x00001fff +#define WCL_CORE_0_ENTRY_CHECK_S 1 + +/* WCL_CORE_0_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ + +#define WCL_CORE_0_STATUSTABLE1_REG (DR_REG_WORLD_CNTL_BASE + 0x80) + +/* WCL_CORE_0_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + +#define WCL_CORE_0_CURRENT_1 (BIT(5)) +#define WCL_CORE_0_CURRENT_1_M (WCL_CORE_0_CURRENT_1_V << WCL_CORE_0_CURRENT_1_S) +#define WCL_CORE_0_CURRENT_1_V 0x00000001 +#define WCL_CORE_0_CURRENT_1_S 5 + +/* WCL_CORE_0_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + +#define WCL_CORE_0_FROM_ENTRY_1 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_1_M (WCL_CORE_0_FROM_ENTRY_1_V << WCL_CORE_0_FROM_ENTRY_1_S) +#define WCL_CORE_0_FROM_ENTRY_1_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_1_S 1 + +/* WCL_CORE_0_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + +#define WCL_CORE_0_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_1_M (WCL_CORE_0_FROM_WORLD_1_V << WCL_CORE_0_FROM_WORLD_1_S) +#define WCL_CORE_0_FROM_WORLD_1_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_1_S 0 + +/* WCL_CORE_0_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ + +#define WCL_CORE_0_STATUSTABLE2_REG (DR_REG_WORLD_CNTL_BASE + 0x84) + +/* WCL_CORE_0_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + +#define WCL_CORE_0_CURRENT_2 (BIT(5)) +#define WCL_CORE_0_CURRENT_2_M (WCL_CORE_0_CURRENT_2_V << WCL_CORE_0_CURRENT_2_S) +#define WCL_CORE_0_CURRENT_2_V 0x00000001 +#define WCL_CORE_0_CURRENT_2_S 5 + +/* WCL_CORE_0_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + +#define WCL_CORE_0_FROM_ENTRY_2 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_2_M (WCL_CORE_0_FROM_ENTRY_2_V << WCL_CORE_0_FROM_ENTRY_2_S) +#define WCL_CORE_0_FROM_ENTRY_2_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_2_S 1 + +/* WCL_CORE_0_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + +#define WCL_CORE_0_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_2_M (WCL_CORE_0_FROM_WORLD_2_V << WCL_CORE_0_FROM_WORLD_2_S) +#define WCL_CORE_0_FROM_WORLD_2_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_2_S 0 + +/* WCL_CORE_0_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ + +#define WCL_CORE_0_STATUSTABLE3_REG (DR_REG_WORLD_CNTL_BASE + 0x88) + +/* WCL_CORE_0_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + +#define WCL_CORE_0_CURRENT_3 (BIT(5)) +#define WCL_CORE_0_CURRENT_3_M (WCL_CORE_0_CURRENT_3_V << WCL_CORE_0_CURRENT_3_S) +#define WCL_CORE_0_CURRENT_3_V 0x00000001 +#define WCL_CORE_0_CURRENT_3_S 5 + +/* WCL_CORE_0_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + +#define WCL_CORE_0_FROM_ENTRY_3 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_3_M (WCL_CORE_0_FROM_ENTRY_3_V << WCL_CORE_0_FROM_ENTRY_3_S) +#define WCL_CORE_0_FROM_ENTRY_3_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_3_S 1 + +/* WCL_CORE_0_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + +#define WCL_CORE_0_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_3_M (WCL_CORE_0_FROM_WORLD_3_V << WCL_CORE_0_FROM_WORLD_3_S) +#define WCL_CORE_0_FROM_WORLD_3_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_3_S 0 + +/* WCL_CORE_0_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ + +#define WCL_CORE_0_STATUSTABLE4_REG (DR_REG_WORLD_CNTL_BASE + 0x8c) + +/* WCL_CORE_0_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + +#define WCL_CORE_0_CURRENT_4 (BIT(5)) +#define WCL_CORE_0_CURRENT_4_M (WCL_CORE_0_CURRENT_4_V << WCL_CORE_0_CURRENT_4_S) +#define WCL_CORE_0_CURRENT_4_V 0x00000001 +#define WCL_CORE_0_CURRENT_4_S 5 + +/* WCL_CORE_0_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + +#define WCL_CORE_0_FROM_ENTRY_4 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_4_M (WCL_CORE_0_FROM_ENTRY_4_V << WCL_CORE_0_FROM_ENTRY_4_S) +#define WCL_CORE_0_FROM_ENTRY_4_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_4_S 1 + +/* WCL_CORE_0_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + +#define WCL_CORE_0_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_4_M (WCL_CORE_0_FROM_WORLD_4_V << WCL_CORE_0_FROM_WORLD_4_S) +#define WCL_CORE_0_FROM_WORLD_4_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_4_S 0 + +/* WCL_CORE_0_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ + +#define WCL_CORE_0_STATUSTABLE5_REG (DR_REG_WORLD_CNTL_BASE + 0x90) + +/* WCL_CORE_0_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + +#define WCL_CORE_0_CURRENT_5 (BIT(5)) +#define WCL_CORE_0_CURRENT_5_M (WCL_CORE_0_CURRENT_5_V << WCL_CORE_0_CURRENT_5_S) +#define WCL_CORE_0_CURRENT_5_V 0x00000001 +#define WCL_CORE_0_CURRENT_5_S 5 + +/* WCL_CORE_0_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + +#define WCL_CORE_0_FROM_ENTRY_5 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_5_M (WCL_CORE_0_FROM_ENTRY_5_V << WCL_CORE_0_FROM_ENTRY_5_S) +#define WCL_CORE_0_FROM_ENTRY_5_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_5_S 1 + +/* WCL_CORE_0_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + +#define WCL_CORE_0_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_5_M (WCL_CORE_0_FROM_WORLD_5_V << WCL_CORE_0_FROM_WORLD_5_S) +#define WCL_CORE_0_FROM_WORLD_5_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_5_S 0 + +/* WCL_CORE_0_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ + +#define WCL_CORE_0_STATUSTABLE6_REG (DR_REG_WORLD_CNTL_BASE + 0x94) + +/* WCL_CORE_0_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + +#define WCL_CORE_0_CURRENT_6 (BIT(5)) +#define WCL_CORE_0_CURRENT_6_M (WCL_CORE_0_CURRENT_6_V << WCL_CORE_0_CURRENT_6_S) +#define WCL_CORE_0_CURRENT_6_V 0x00000001 +#define WCL_CORE_0_CURRENT_6_S 5 + +/* WCL_CORE_0_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + +#define WCL_CORE_0_FROM_ENTRY_6 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_6_M (WCL_CORE_0_FROM_ENTRY_6_V << WCL_CORE_0_FROM_ENTRY_6_S) +#define WCL_CORE_0_FROM_ENTRY_6_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_6_S 1 + +/* WCL_CORE_0_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + +#define WCL_CORE_0_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_6_M (WCL_CORE_0_FROM_WORLD_6_V << WCL_CORE_0_FROM_WORLD_6_S) +#define WCL_CORE_0_FROM_WORLD_6_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_6_S 0 + +/* WCL_CORE_0_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ + +#define WCL_CORE_0_STATUSTABLE7_REG (DR_REG_WORLD_CNTL_BASE + 0x98) + +/* WCL_CORE_0_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + +#define WCL_CORE_0_CURRENT_7 (BIT(5)) +#define WCL_CORE_0_CURRENT_7_M (WCL_CORE_0_CURRENT_7_V << WCL_CORE_0_CURRENT_7_S) +#define WCL_CORE_0_CURRENT_7_V 0x00000001 +#define WCL_CORE_0_CURRENT_7_S 5 + +/* WCL_CORE_0_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + +#define WCL_CORE_0_FROM_ENTRY_7 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_7_M (WCL_CORE_0_FROM_ENTRY_7_V << WCL_CORE_0_FROM_ENTRY_7_S) +#define WCL_CORE_0_FROM_ENTRY_7_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_7_S 1 + +/* WCL_CORE_0_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + +#define WCL_CORE_0_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_7_M (WCL_CORE_0_FROM_WORLD_7_V << WCL_CORE_0_FROM_WORLD_7_S) +#define WCL_CORE_0_FROM_WORLD_7_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_7_S 0 + +/* WCL_CORE_0_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ + +#define WCL_CORE_0_STATUSTABLE8_REG (DR_REG_WORLD_CNTL_BASE + 0x9c) + +/* WCL_CORE_0_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + +#define WCL_CORE_0_CURRENT_8 (BIT(5)) +#define WCL_CORE_0_CURRENT_8_M (WCL_CORE_0_CURRENT_8_V << WCL_CORE_0_CURRENT_8_S) +#define WCL_CORE_0_CURRENT_8_V 0x00000001 +#define WCL_CORE_0_CURRENT_8_S 5 + +/* WCL_CORE_0_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + +#define WCL_CORE_0_FROM_ENTRY_8 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_8_M (WCL_CORE_0_FROM_ENTRY_8_V << WCL_CORE_0_FROM_ENTRY_8_S) +#define WCL_CORE_0_FROM_ENTRY_8_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_8_S 1 + +/* WCL_CORE_0_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + +#define WCL_CORE_0_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_8_M (WCL_CORE_0_FROM_WORLD_8_V << WCL_CORE_0_FROM_WORLD_8_S) +#define WCL_CORE_0_FROM_WORLD_8_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_8_S 0 + +/* WCL_CORE_0_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ + +#define WCL_CORE_0_STATUSTABLE9_REG (DR_REG_WORLD_CNTL_BASE + 0xa0) + +/* WCL_CORE_0_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + +#define WCL_CORE_0_CURRENT_9 (BIT(5)) +#define WCL_CORE_0_CURRENT_9_M (WCL_CORE_0_CURRENT_9_V << WCL_CORE_0_CURRENT_9_S) +#define WCL_CORE_0_CURRENT_9_V 0x00000001 +#define WCL_CORE_0_CURRENT_9_S 5 + +/* WCL_CORE_0_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + +#define WCL_CORE_0_FROM_ENTRY_9 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_9_M (WCL_CORE_0_FROM_ENTRY_9_V << WCL_CORE_0_FROM_ENTRY_9_S) +#define WCL_CORE_0_FROM_ENTRY_9_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_9_S 1 + +/* WCL_CORE_0_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + +#define WCL_CORE_0_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_9_M (WCL_CORE_0_FROM_WORLD_9_V << WCL_CORE_0_FROM_WORLD_9_S) +#define WCL_CORE_0_FROM_WORLD_9_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_9_S 0 + +/* WCL_CORE_0_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ + +#define WCL_CORE_0_STATUSTABLE10_REG (DR_REG_WORLD_CNTL_BASE + 0xa4) + +/* WCL_CORE_0_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + +#define WCL_CORE_0_CURRENT_10 (BIT(5)) +#define WCL_CORE_0_CURRENT_10_M (WCL_CORE_0_CURRENT_10_V << WCL_CORE_0_CURRENT_10_S) +#define WCL_CORE_0_CURRENT_10_V 0x00000001 +#define WCL_CORE_0_CURRENT_10_S 5 + +/* WCL_CORE_0_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + +#define WCL_CORE_0_FROM_ENTRY_10 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_10_M (WCL_CORE_0_FROM_ENTRY_10_V << WCL_CORE_0_FROM_ENTRY_10_S) +#define WCL_CORE_0_FROM_ENTRY_10_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_10_S 1 + +/* WCL_CORE_0_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + +#define WCL_CORE_0_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_10_M (WCL_CORE_0_FROM_WORLD_10_V << WCL_CORE_0_FROM_WORLD_10_S) +#define WCL_CORE_0_FROM_WORLD_10_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_10_S 0 + +/* WCL_CORE_0_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ + +#define WCL_CORE_0_STATUSTABLE11_REG (DR_REG_WORLD_CNTL_BASE + 0xa8) + +/* WCL_CORE_0_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + +#define WCL_CORE_0_CURRENT_11 (BIT(5)) +#define WCL_CORE_0_CURRENT_11_M (WCL_CORE_0_CURRENT_11_V << WCL_CORE_0_CURRENT_11_S) +#define WCL_CORE_0_CURRENT_11_V 0x00000001 +#define WCL_CORE_0_CURRENT_11_S 5 + +/* WCL_CORE_0_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + +#define WCL_CORE_0_FROM_ENTRY_11 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_11_M (WCL_CORE_0_FROM_ENTRY_11_V << WCL_CORE_0_FROM_ENTRY_11_S) +#define WCL_CORE_0_FROM_ENTRY_11_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_11_S 1 + +/* WCL_CORE_0_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + +#define WCL_CORE_0_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_11_M (WCL_CORE_0_FROM_WORLD_11_V << WCL_CORE_0_FROM_WORLD_11_S) +#define WCL_CORE_0_FROM_WORLD_11_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_11_S 0 + +/* WCL_CORE_0_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ + +#define WCL_CORE_0_STATUSTABLE12_REG (DR_REG_WORLD_CNTL_BASE + 0xac) + +/* WCL_CORE_0_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + +#define WCL_CORE_0_CURRENT_12 (BIT(5)) +#define WCL_CORE_0_CURRENT_12_M (WCL_CORE_0_CURRENT_12_V << WCL_CORE_0_CURRENT_12_S) +#define WCL_CORE_0_CURRENT_12_V 0x00000001 +#define WCL_CORE_0_CURRENT_12_S 5 + +/* WCL_CORE_0_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + +#define WCL_CORE_0_FROM_ENTRY_12 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_12_M (WCL_CORE_0_FROM_ENTRY_12_V << WCL_CORE_0_FROM_ENTRY_12_S) +#define WCL_CORE_0_FROM_ENTRY_12_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_12_S 1 + +/* WCL_CORE_0_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + +#define WCL_CORE_0_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_12_M (WCL_CORE_0_FROM_WORLD_12_V << WCL_CORE_0_FROM_WORLD_12_S) +#define WCL_CORE_0_FROM_WORLD_12_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_12_S 0 + +/* WCL_CORE_0_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ + +#define WCL_CORE_0_STATUSTABLE13_REG (DR_REG_WORLD_CNTL_BASE + 0xb0) + +/* WCL_CORE_0_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + +#define WCL_CORE_0_CURRENT_13 (BIT(5)) +#define WCL_CORE_0_CURRENT_13_M (WCL_CORE_0_CURRENT_13_V << WCL_CORE_0_CURRENT_13_S) +#define WCL_CORE_0_CURRENT_13_V 0x00000001 +#define WCL_CORE_0_CURRENT_13_S 5 + +/* WCL_CORE_0_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + +#define WCL_CORE_0_FROM_ENTRY_13 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_13_M (WCL_CORE_0_FROM_ENTRY_13_V << WCL_CORE_0_FROM_ENTRY_13_S) +#define WCL_CORE_0_FROM_ENTRY_13_V 0x0000000f +#define WCL_CORE_0_FROM_ENTRY_13_S 1 + +/* WCL_CORE_0_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + +#define WCL_CORE_0_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_0_FROM_WORLD_13_M (WCL_CORE_0_FROM_WORLD_13_V << WCL_CORE_0_FROM_WORLD_13_S) +#define WCL_CORE_0_FROM_WORLD_13_V 0x00000001 +#define WCL_CORE_0_FROM_WORLD_13_S 0 + +/* WCL_CORE_0_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ + +#define WCL_CORE_0_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CNTL_BASE + 0xfc) + +/* WCL_CORE_0_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all + * STATUSTABLE registers,for example,bit 1 represents the current field of + * STATUSTABLE1,bit2 represents the current field of STATUSTABLE2 + */ + +#define WCL_CORE_0_STATUSTABLE_CURRENT 0x00001fff +#define WCL_CORE_0_STATUSTABLE_CURRENT_M (WCL_CORE_0_STATUSTABLE_CURRENT_V << WCL_CORE_0_STATUSTABLE_CURRENT_S) +#define WCL_CORE_0_STATUSTABLE_CURRENT_V 0x00001fff +#define WCL_CORE_0_STATUSTABLE_CURRENT_S 1 + +/* WCL_CORE_0_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ + +#define WCL_CORE_0_MESSAGE_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x100) + +/* WCL_CORE_0_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + +#define WCL_CORE_0_MESSAGE_ADDR 0xffffffff +#define WCL_CORE_0_MESSAGE_ADDR_M (WCL_CORE_0_MESSAGE_ADDR_V << WCL_CORE_0_MESSAGE_ADDR_S) +#define WCL_CORE_0_MESSAGE_ADDR_V 0xffffffff +#define WCL_CORE_0_MESSAGE_ADDR_S 0 + +/* WCL_CORE_0_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ + +#define WCL_CORE_0_MESSAGE_MAX_REG (DR_REG_WORLD_CNTL_BASE + 0x104) + +/* WCL_CORE_0_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + +#define WCL_CORE_0_MESSAGE_MAX 0x0000000f +#define WCL_CORE_0_MESSAGE_MAX_M (WCL_CORE_0_MESSAGE_MAX_V << WCL_CORE_0_MESSAGE_MAX_S) +#define WCL_CORE_0_MESSAGE_MAX_V 0x0000000f +#define WCL_CORE_0_MESSAGE_MAX_S 0 + +/* WCL_CORE_0_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ + +#define WCL_CORE_0_MESSAGE_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x108) + +/* WCL_CORE_0_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer + * operation,and is checking address. + */ + +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_M (WCL_CORE_0_MESSAGE_ADDRESSPHASE_V << WCL_CORE_0_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_V 0x00000001 +#define WCL_CORE_0_MESSAGE_ADDRESSPHASE_S 6 + +/* WCL_CORE_0_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer + * operation,and is checking data + */ + +#define WCL_CORE_0_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_0_MESSAGE_DATAPHASE_M (WCL_CORE_0_MESSAGE_DATAPHASE_V << WCL_CORE_0_MESSAGE_DATAPHASE_S) +#define WCL_CORE_0_MESSAGE_DATAPHASE_V 0x00000001 +#define WCL_CORE_0_MESSAGE_DATAPHASE_S 5 + +/* WCL_CORE_0_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + +#define WCL_CORE_0_MESSAGE_EXPECT 0x0000000f +#define WCL_CORE_0_MESSAGE_EXPECT_M (WCL_CORE_0_MESSAGE_EXPECT_V << WCL_CORE_0_MESSAGE_EXPECT_S) +#define WCL_CORE_0_MESSAGE_EXPECT_V 0x0000000f +#define WCL_CORE_0_MESSAGE_EXPECT_S 1 + +/* WCL_CORE_0_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + +#define WCL_CORE_0_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_0_MESSAGE_MATCH_M (WCL_CORE_0_MESSAGE_MATCH_V << WCL_CORE_0_MESSAGE_MATCH_S) +#define WCL_CORE_0_MESSAGE_MATCH_V 0x00000001 +#define WCL_CORE_0_MESSAGE_MATCH_S 0 + +/* WCL_CORE_0_World_TRIGGER_ADDR_REG register + * Core_0 trigger address configuration Register + */ + +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x140) + +/* WCL_CORE_0_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to + * WORLD1,when the CPU executes to this address,switch to WORLD1 + */ + +#define WCL_CORE_0_WORLD_TRIGGER_ADDR 0xffffffff +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_M (WCL_CORE_0_WORLD_TRIGGER_ADDR_V << WCL_CORE_0_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_V 0xffffffff +#define WCL_CORE_0_WORLD_TRIGGER_ADDR_S 0 + +/* WCL_CORE_0_World_PREPARE_REG register + * Core_0 prepare world configuration Register + */ + +#define WCL_CORE_0_WORLD_PREPARE_REG (DR_REG_WORLD_CNTL_BASE + 0x144) + +/* WCL_CORE_0_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 + * means WORLD1 + */ + +#define WCL_CORE_0_WORLD_PREPARE 0x00000003 +#define WCL_CORE_0_WORLD_PREPARE_M (WCL_CORE_0_WORLD_PREPARE_V << WCL_CORE_0_WORLD_PREPARE_S) +#define WCL_CORE_0_WORLD_PREPARE_V 0x00000003 +#define WCL_CORE_0_WORLD_PREPARE_S 0 + +/* WCL_CORE_0_World_UPDATE_REG register + * Core_0 configuration update register + */ + +#define WCL_CORE_0_WORLD_UPDATE_REG (DR_REG_WORLD_CNTL_BASE + 0x148) + +/* WCL_CORE_0_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any + * value,the hardware only checks the write operation of this register and + * does not case about its value + */ + +#define WCL_CORE_0_UPDATE 0xffffffff +#define WCL_CORE_0_UPDATE_M (WCL_CORE_0_UPDATE_V << WCL_CORE_0_UPDATE_S) +#define WCL_CORE_0_UPDATE_V 0xffffffff +#define WCL_CORE_0_UPDATE_S 0 + +/* WCL_CORE_0_World_Cancel_REG register + * Core_0 configuration cancel register + */ + +#define WCL_CORE_0_WORLD_CANCEL_REG (DR_REG_WORLD_CNTL_BASE + 0x14c) + +/* WCL_CORE_0_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger + * address and update configuration complete,use this register to cancel + * world switch, jujst need write any value,the hardware only checks the + * write operation of this register and does not case about its value + */ + +#define WCL_CORE_0_WORLD_CANCEL 0xffffffff +#define WCL_CORE_0_WORLD_CANCEL_M (WCL_CORE_0_WORLD_CANCEL_V << WCL_CORE_0_WORLD_CANCEL_S) +#define WCL_CORE_0_WORLD_CANCEL_V 0xffffffff +#define WCL_CORE_0_WORLD_CANCEL_S 0 + +/* WCL_CORE_0_World_IRam0_REG register + * Core_0 Iram0 world register + */ + +#define WCL_CORE_0_WORLD_IRAM0_REG (DR_REG_WORLD_CNTL_BASE + 0x150) + +/* WCL_CORE_0_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + +#define WCL_CORE_0_WORLD_IRAM0 0x00000003 +#define WCL_CORE_0_WORLD_IRAM0_M (WCL_CORE_0_WORLD_IRAM0_V << WCL_CORE_0_WORLD_IRAM0_S) +#define WCL_CORE_0_WORLD_IRAM0_V 0x00000003 +#define WCL_CORE_0_WORLD_IRAM0_S 0 + +/* WCL_CORE_0_World_DRam0_PIF_REG register + * Core_0 dram0 and PIF world register + */ + +#define WCL_CORE_0_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CNTL_BASE + 0x154) + +/* WCL_CORE_0_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + +#define WCL_CORE_0_WORLD_DRAM0_PIF 0x00000003 +#define WCL_CORE_0_WORLD_DRAM0_PIF_M (WCL_CORE_0_WORLD_DRAM0_PIF_V << WCL_CORE_0_WORLD_DRAM0_PIF_S) +#define WCL_CORE_0_WORLD_DRAM0_PIF_V 0x00000003 +#define WCL_CORE_0_WORLD_DRAM0_PIF_S 0 + +/* WCL_CORE_0_World_Phase_REG register + * Core_0 world status register + */ + +#define WCL_CORE_0_WORLD_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x158) + +/* WCL_CORE_0_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1, 1 means + * value. + */ + +#define WCL_CORE_0_WORLD_PHASE (BIT(0)) +#define WCL_CORE_0_WORLD_PHASE_M (WCL_CORE_0_WORLD_PHASE_V << WCL_CORE_0_WORLD_PHASE_S) +#define WCL_CORE_0_WORLD_PHASE_V 0x00000001 +#define WCL_CORE_0_WORLD_PHASE_S 0 + +/* WCL_CORE_0_NMI_MASK_ENABLE_REG register + * Core_0 NMI mask enable register + */ + +#define WCL_CORE_0_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CNTL_BASE + 0x180) + +/* WCL_CORE_0_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask,it can write any value,when write this + * register,the hardware start masking NMI interrupt + */ + +#define WCL_CORE_0_NMI_MASK_ENABLE 0xffffffff +#define WCL_CORE_0_NMI_MASK_ENABLE_M (WCL_CORE_0_NMI_MASK_ENABLE_V << WCL_CORE_0_NMI_MASK_ENABLE_S) +#define WCL_CORE_0_NMI_MASK_ENABLE_V 0xffffffff +#define WCL_CORE_0_NMI_MASK_ENABLE_S 0 + +/* WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG register + * Core_0 NMI mask trigger address register + */ + +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x184) + +/* WCL_CORE_0_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address, when CPU executes to this + * address,NMI mask automatically fails + */ + +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR 0xffffffff +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_V 0xffffffff +#define WCL_CORE_0_NMI_MASK_TRIGGER_ADDR_S 0 + +/* WCL_CORE_0_NMI_MASK_DISABLE_REG register + * Core_0 NMI mask disable register + */ + +#define WCL_CORE_0_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CNTL_BASE + 0x188) + +/* WCL_CORE_0_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask,it will not take effect + * immediately,only when the CPU executes to the trigger address will it + * start to cancel NMI mask + */ + +#define WCL_CORE_0_NMI_MASK_DISABLE 0xffffffff +#define WCL_CORE_0_NMI_MASK_DISABLE_M (WCL_CORE_0_NMI_MASK_DISABLE_V << WCL_CORE_0_NMI_MASK_DISABLE_S) +#define WCL_CORE_0_NMI_MASK_DISABLE_V 0xffffffff +#define WCL_CORE_0_NMI_MASK_DISABLE_S 0 + +/* WCL_CORE_0_NMI_MASK_CANCLE_REG register + * Core_0 NMI mask disable register + */ + +#define WCL_CORE_0_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CNTL_BASE + 0x18c) + +/* WCL_CORE_0_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + +#define WCL_CORE_0_NMI_MASK_CANCEL 0xffffffff +#define WCL_CORE_0_NMI_MASK_CANCEL_M (WCL_CORE_0_NMI_MASK_CANCEL_V << WCL_CORE_0_NMI_MASK_CANCEL_S) +#define WCL_CORE_0_NMI_MASK_CANCEL_V 0xffffffff +#define WCL_CORE_0_NMI_MASK_CANCEL_S 0 + +/* WCL_CORE_0_NMI_MASK_REG register + * Core_0 NMI mask register + */ + +#define WCL_CORE_0_NMI_MASK_REG (DR_REG_WORLD_CNTL_BASE + 0x190) + +/* WCL_CORE_0_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + +#define WCL_CORE_0_NMI_MASK (BIT(0)) +#define WCL_CORE_0_NMI_MASK_M (WCL_CORE_0_NMI_MASK_V << WCL_CORE_0_NMI_MASK_S) +#define WCL_CORE_0_NMI_MASK_V 0x00000001 +#define WCL_CORE_0_NMI_MASK_S 0 + +/* WCL_CORE_0_NMI_MASK_PHASE_REG register + * Core_0 NMI mask phase register + */ + +#define WCL_CORE_0_NMI_MASK_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x194) + +/* WCL_CORE_0_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, + * 1 means NMI interrupt is being masked + */ + +#define WCL_CORE_0_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_0_NMI_MASK_PHASE_M (WCL_CORE_0_NMI_MASK_PHASE_V << WCL_CORE_0_NMI_MASK_PHASE_S) +#define WCL_CORE_0_NMI_MASK_PHASE_V 0x00000001 +#define WCL_CORE_0_NMI_MASK_PHASE_S 0 + +/* WCL_CORE_1_ENTRY_1_ADDR_REG register + * Core_1 Entry 1 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_1_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x400) + +/* WCL_CORE_1_ENTRY_1_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 1 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_1_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_1_ADDR_M (WCL_CORE_1_ENTRY_1_ADDR_V << WCL_CORE_1_ENTRY_1_ADDR_S) +#define WCL_CORE_1_ENTRY_1_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_1_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_2_ADDR_REG register + * Core_1 Entry 2 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_2_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x404) + +/* WCL_CORE_1_ENTRY_2_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 2 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_2_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_2_ADDR_M (WCL_CORE_1_ENTRY_2_ADDR_V << WCL_CORE_1_ENTRY_2_ADDR_S) +#define WCL_CORE_1_ENTRY_2_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_2_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_3_ADDR_REG register + * Core_1 Entry 3 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_3_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x408) + +/* WCL_CORE_1_ENTRY_3_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 3 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_3_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_3_ADDR_M (WCL_CORE_1_ENTRY_3_ADDR_V << WCL_CORE_1_ENTRY_3_ADDR_S) +#define WCL_CORE_1_ENTRY_3_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_3_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_4_ADDR_REG register + * Core_1 Entry 4 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_4_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x40c) + +/* WCL_CORE_1_ENTRY_4_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 4 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_4_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_4_ADDR_M (WCL_CORE_1_ENTRY_4_ADDR_V << WCL_CORE_1_ENTRY_4_ADDR_S) +#define WCL_CORE_1_ENTRY_4_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_4_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_5_ADDR_REG register + * Core_1 Entry 5 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_5_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x410) + +/* WCL_CORE_1_ENTRY_5_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 5 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_5_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_5_ADDR_M (WCL_CORE_1_ENTRY_5_ADDR_V << WCL_CORE_1_ENTRY_5_ADDR_S) +#define WCL_CORE_1_ENTRY_5_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_5_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_6_ADDR_REG register + * Core_1 Entry 6 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_6_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x414) + +/* WCL_CORE_1_ENTRY_6_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 6 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_6_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_6_ADDR_M (WCL_CORE_1_ENTRY_6_ADDR_V << WCL_CORE_1_ENTRY_6_ADDR_S) +#define WCL_CORE_1_ENTRY_6_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_6_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_7_ADDR_REG register + * Core_1 Entry 7 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_7_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x418) + +/* WCL_CORE_1_ENTRY_7_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 7 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_7_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_7_ADDR_M (WCL_CORE_1_ENTRY_7_ADDR_V << WCL_CORE_1_ENTRY_7_ADDR_S) +#define WCL_CORE_1_ENTRY_7_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_7_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_8_ADDR_REG register + * Core_1 Entry 8 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_8_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x41c) + +/* WCL_CORE_1_ENTRY_8_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 8 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_8_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_8_ADDR_M (WCL_CORE_1_ENTRY_8_ADDR_V << WCL_CORE_1_ENTRY_8_ADDR_S) +#define WCL_CORE_1_ENTRY_8_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_8_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_9_ADDR_REG register + * Core_1 Entry 9 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_9_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x420) + +/* WCL_CORE_1_ENTRY_9_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 9 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_9_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_9_ADDR_M (WCL_CORE_1_ENTRY_9_ADDR_V << WCL_CORE_1_ENTRY_9_ADDR_S) +#define WCL_CORE_1_ENTRY_9_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_9_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_10_ADDR_REG register + * Core_1 Entry 10 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_10_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x424) + +/* WCL_CORE_1_ENTRY_10_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 10 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_10_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_10_ADDR_M (WCL_CORE_1_ENTRY_10_ADDR_V << WCL_CORE_1_ENTRY_10_ADDR_S) +#define WCL_CORE_1_ENTRY_10_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_10_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_11_ADDR_REG register + * Core_1 Entry 11 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_11_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x428) + +/* WCL_CORE_1_ENTRY_11_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 11 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_11_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_11_ADDR_M (WCL_CORE_1_ENTRY_11_ADDR_V << WCL_CORE_1_ENTRY_11_ADDR_S) +#define WCL_CORE_1_ENTRY_11_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_11_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_12_ADDR_REG register + * Core_1 Entry 12 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_12_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x42c) + +/* WCL_CORE_1_ENTRY_12_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 12 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_12_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_12_ADDR_M (WCL_CORE_1_ENTRY_12_ADDR_V << WCL_CORE_1_ENTRY_12_ADDR_S) +#define WCL_CORE_1_ENTRY_12_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_12_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_13_ADDR_REG register + * Core_1 Entry 13 address configuration Register + */ + +#define WCL_CORE_1_ENTRY_13_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x430) + +/* WCL_CORE_1_ENTRY_13_ADDR : R/W; bitpos: [31:0]; default: 0; + * Core_1 Entry 13 address from WORLD1 to WORLD0 + */ + +#define WCL_CORE_1_ENTRY_13_ADDR 0xffffffff +#define WCL_CORE_1_ENTRY_13_ADDR_M (WCL_CORE_1_ENTRY_13_ADDR_V << WCL_CORE_1_ENTRY_13_ADDR_S) +#define WCL_CORE_1_ENTRY_13_ADDR_V 0xffffffff +#define WCL_CORE_1_ENTRY_13_ADDR_S 0 + +/* WCL_CORE_1_ENTRY_CHECK_REG register + * Core_1 Entry check configuration Register + */ + +#define WCL_CORE_1_ENTRY_CHECK_REG (DR_REG_WORLD_CNTL_BASE + 0x47c) + +/* WCL_CORE_1_ENTRY_CHECK : R/W; bitpos: [13:1]; default: 1; + * This filed is used to enable entry address check + */ + +#define WCL_CORE_1_ENTRY_CHECK 0x00001fff +#define WCL_CORE_1_ENTRY_CHECK_M (WCL_CORE_1_ENTRY_CHECK_V << WCL_CORE_1_ENTRY_CHECK_S) +#define WCL_CORE_1_ENTRY_CHECK_V 0x00001fff +#define WCL_CORE_1_ENTRY_CHECK_S 1 + +/* WCL_CORE_1_STATUSTABLE1_REG register + * Status register of world switch of entry 1 + */ + +#define WCL_CORE_1_STATUSTABLE1_REG (DR_REG_WORLD_CNTL_BASE + 0x480) + +/* WCL_CORE_1_CURRENT_1 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 1 + */ + +#define WCL_CORE_1_CURRENT_1 (BIT(5)) +#define WCL_CORE_1_CURRENT_1_M (WCL_CORE_1_CURRENT_1_V << WCL_CORE_1_CURRENT_1_S) +#define WCL_CORE_1_CURRENT_1_V 0x00000001 +#define WCL_CORE_1_CURRENT_1_S 5 + +/* WCL_CORE_1_FROM_ENTRY_1 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 1 + */ + +#define WCL_CORE_1_FROM_ENTRY_1 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_1_M (WCL_CORE_1_FROM_ENTRY_1_V << WCL_CORE_1_FROM_ENTRY_1_S) +#define WCL_CORE_1_FROM_ENTRY_1_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_1_S 1 + +/* WCL_CORE_1_FROM_WORLD_1 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 1 + */ + +#define WCL_CORE_1_FROM_WORLD_1 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_1_M (WCL_CORE_1_FROM_WORLD_1_V << WCL_CORE_1_FROM_WORLD_1_S) +#define WCL_CORE_1_FROM_WORLD_1_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_1_S 0 + +/* WCL_CORE_1_STATUSTABLE2_REG register + * Status register of world switch of entry 2 + */ + +#define WCL_CORE_1_STATUSTABLE2_REG (DR_REG_WORLD_CNTL_BASE + 0x484) + +/* WCL_CORE_1_CURRENT_2 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 2 + */ + +#define WCL_CORE_1_CURRENT_2 (BIT(5)) +#define WCL_CORE_1_CURRENT_2_M (WCL_CORE_1_CURRENT_2_V << WCL_CORE_1_CURRENT_2_S) +#define WCL_CORE_1_CURRENT_2_V 0x00000001 +#define WCL_CORE_1_CURRENT_2_S 5 + +/* WCL_CORE_1_FROM_ENTRY_2 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 2 + */ + +#define WCL_CORE_1_FROM_ENTRY_2 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_2_M (WCL_CORE_1_FROM_ENTRY_2_V << WCL_CORE_1_FROM_ENTRY_2_S) +#define WCL_CORE_1_FROM_ENTRY_2_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_2_S 1 + +/* WCL_CORE_1_FROM_WORLD_2 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 2 + */ + +#define WCL_CORE_1_FROM_WORLD_2 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_2_M (WCL_CORE_1_FROM_WORLD_2_V << WCL_CORE_1_FROM_WORLD_2_S) +#define WCL_CORE_1_FROM_WORLD_2_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_2_S 0 + +/* WCL_CORE_1_STATUSTABLE3_REG register + * Status register of world switch of entry 3 + */ + +#define WCL_CORE_1_STATUSTABLE3_REG (DR_REG_WORLD_CNTL_BASE + 0x488) + +/* WCL_CORE_1_CURRENT_3 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 3 + */ + +#define WCL_CORE_1_CURRENT_3 (BIT(5)) +#define WCL_CORE_1_CURRENT_3_M (WCL_CORE_1_CURRENT_3_V << WCL_CORE_1_CURRENT_3_S) +#define WCL_CORE_1_CURRENT_3_V 0x00000001 +#define WCL_CORE_1_CURRENT_3_S 5 + +/* WCL_CORE_1_FROM_ENTRY_3 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 3 + */ + +#define WCL_CORE_1_FROM_ENTRY_3 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_3_M (WCL_CORE_1_FROM_ENTRY_3_V << WCL_CORE_1_FROM_ENTRY_3_S) +#define WCL_CORE_1_FROM_ENTRY_3_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_3_S 1 + +/* WCL_CORE_1_FROM_WORLD_3 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 3 + */ + +#define WCL_CORE_1_FROM_WORLD_3 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_3_M (WCL_CORE_1_FROM_WORLD_3_V << WCL_CORE_1_FROM_WORLD_3_S) +#define WCL_CORE_1_FROM_WORLD_3_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_3_S 0 + +/* WCL_CORE_1_STATUSTABLE4_REG register + * Status register of world switch of entry 4 + */ + +#define WCL_CORE_1_STATUSTABLE4_REG (DR_REG_WORLD_CNTL_BASE + 0x48c) + +/* WCL_CORE_1_CURRENT_4 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 4 + */ + +#define WCL_CORE_1_CURRENT_4 (BIT(5)) +#define WCL_CORE_1_CURRENT_4_M (WCL_CORE_1_CURRENT_4_V << WCL_CORE_1_CURRENT_4_S) +#define WCL_CORE_1_CURRENT_4_V 0x00000001 +#define WCL_CORE_1_CURRENT_4_S 5 + +/* WCL_CORE_1_FROM_ENTRY_4 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 4 + */ + +#define WCL_CORE_1_FROM_ENTRY_4 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_4_M (WCL_CORE_1_FROM_ENTRY_4_V << WCL_CORE_1_FROM_ENTRY_4_S) +#define WCL_CORE_1_FROM_ENTRY_4_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_4_S 1 + +/* WCL_CORE_1_FROM_WORLD_4 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 4 + */ + +#define WCL_CORE_1_FROM_WORLD_4 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_4_M (WCL_CORE_1_FROM_WORLD_4_V << WCL_CORE_1_FROM_WORLD_4_S) +#define WCL_CORE_1_FROM_WORLD_4_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_4_S 0 + +/* WCL_CORE_1_STATUSTABLE5_REG register + * Status register of world switch of entry 5 + */ + +#define WCL_CORE_1_STATUSTABLE5_REG (DR_REG_WORLD_CNTL_BASE + 0x490) + +/* WCL_CORE_1_CURRENT_5 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 5 + */ + +#define WCL_CORE_1_CURRENT_5 (BIT(5)) +#define WCL_CORE_1_CURRENT_5_M (WCL_CORE_1_CURRENT_5_V << WCL_CORE_1_CURRENT_5_S) +#define WCL_CORE_1_CURRENT_5_V 0x00000001 +#define WCL_CORE_1_CURRENT_5_S 5 + +/* WCL_CORE_1_FROM_ENTRY_5 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 5 + */ + +#define WCL_CORE_1_FROM_ENTRY_5 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_5_M (WCL_CORE_1_FROM_ENTRY_5_V << WCL_CORE_1_FROM_ENTRY_5_S) +#define WCL_CORE_1_FROM_ENTRY_5_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_5_S 1 + +/* WCL_CORE_1_FROM_WORLD_5 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 5 + */ + +#define WCL_CORE_1_FROM_WORLD_5 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_5_M (WCL_CORE_1_FROM_WORLD_5_V << WCL_CORE_1_FROM_WORLD_5_S) +#define WCL_CORE_1_FROM_WORLD_5_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_5_S 0 + +/* WCL_CORE_1_STATUSTABLE6_REG register + * Status register of world switch of entry 6 + */ + +#define WCL_CORE_1_STATUSTABLE6_REG (DR_REG_WORLD_CNTL_BASE + 0x494) + +/* WCL_CORE_1_CURRENT_6 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 6 + */ + +#define WCL_CORE_1_CURRENT_6 (BIT(5)) +#define WCL_CORE_1_CURRENT_6_M (WCL_CORE_1_CURRENT_6_V << WCL_CORE_1_CURRENT_6_S) +#define WCL_CORE_1_CURRENT_6_V 0x00000001 +#define WCL_CORE_1_CURRENT_6_S 5 + +/* WCL_CORE_1_FROM_ENTRY_6 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 6 + */ + +#define WCL_CORE_1_FROM_ENTRY_6 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_6_M (WCL_CORE_1_FROM_ENTRY_6_V << WCL_CORE_1_FROM_ENTRY_6_S) +#define WCL_CORE_1_FROM_ENTRY_6_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_6_S 1 + +/* WCL_CORE_1_FROM_WORLD_6 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 6 + */ + +#define WCL_CORE_1_FROM_WORLD_6 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_6_M (WCL_CORE_1_FROM_WORLD_6_V << WCL_CORE_1_FROM_WORLD_6_S) +#define WCL_CORE_1_FROM_WORLD_6_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_6_S 0 + +/* WCL_CORE_1_STATUSTABLE7_REG register + * Status register of world switch of entry 7 + */ + +#define WCL_CORE_1_STATUSTABLE7_REG (DR_REG_WORLD_CNTL_BASE + 0x498) + +/* WCL_CORE_1_CURRENT_7 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 7 + */ + +#define WCL_CORE_1_CURRENT_7 (BIT(5)) +#define WCL_CORE_1_CURRENT_7_M (WCL_CORE_1_CURRENT_7_V << WCL_CORE_1_CURRENT_7_S) +#define WCL_CORE_1_CURRENT_7_V 0x00000001 +#define WCL_CORE_1_CURRENT_7_S 5 + +/* WCL_CORE_1_FROM_ENTRY_7 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 7 + */ + +#define WCL_CORE_1_FROM_ENTRY_7 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_7_M (WCL_CORE_1_FROM_ENTRY_7_V << WCL_CORE_1_FROM_ENTRY_7_S) +#define WCL_CORE_1_FROM_ENTRY_7_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_7_S 1 + +/* WCL_CORE_1_FROM_WORLD_7 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 7 + */ + +#define WCL_CORE_1_FROM_WORLD_7 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_7_M (WCL_CORE_1_FROM_WORLD_7_V << WCL_CORE_1_FROM_WORLD_7_S) +#define WCL_CORE_1_FROM_WORLD_7_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_7_S 0 + +/* WCL_CORE_1_STATUSTABLE8_REG register + * Status register of world switch of entry 8 + */ + +#define WCL_CORE_1_STATUSTABLE8_REG (DR_REG_WORLD_CNTL_BASE + 0x49c) + +/* WCL_CORE_1_CURRENT_8 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 8 + */ + +#define WCL_CORE_1_CURRENT_8 (BIT(5)) +#define WCL_CORE_1_CURRENT_8_M (WCL_CORE_1_CURRENT_8_V << WCL_CORE_1_CURRENT_8_S) +#define WCL_CORE_1_CURRENT_8_V 0x00000001 +#define WCL_CORE_1_CURRENT_8_S 5 + +/* WCL_CORE_1_FROM_ENTRY_8 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 8 + */ + +#define WCL_CORE_1_FROM_ENTRY_8 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_8_M (WCL_CORE_1_FROM_ENTRY_8_V << WCL_CORE_1_FROM_ENTRY_8_S) +#define WCL_CORE_1_FROM_ENTRY_8_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_8_S 1 + +/* WCL_CORE_1_FROM_WORLD_8 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 8 + */ + +#define WCL_CORE_1_FROM_WORLD_8 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_8_M (WCL_CORE_1_FROM_WORLD_8_V << WCL_CORE_1_FROM_WORLD_8_S) +#define WCL_CORE_1_FROM_WORLD_8_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_8_S 0 + +/* WCL_CORE_1_STATUSTABLE9_REG register + * Status register of world switch of entry 9 + */ + +#define WCL_CORE_1_STATUSTABLE9_REG (DR_REG_WORLD_CNTL_BASE + 0x4a0) + +/* WCL_CORE_1_CURRENT_9 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 9 + */ + +#define WCL_CORE_1_CURRENT_9 (BIT(5)) +#define WCL_CORE_1_CURRENT_9_M (WCL_CORE_1_CURRENT_9_V << WCL_CORE_1_CURRENT_9_S) +#define WCL_CORE_1_CURRENT_9_V 0x00000001 +#define WCL_CORE_1_CURRENT_9_S 5 + +/* WCL_CORE_1_FROM_ENTRY_9 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 9 + */ + +#define WCL_CORE_1_FROM_ENTRY_9 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_9_M (WCL_CORE_1_FROM_ENTRY_9_V << WCL_CORE_1_FROM_ENTRY_9_S) +#define WCL_CORE_1_FROM_ENTRY_9_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_9_S 1 + +/* WCL_CORE_1_FROM_WORLD_9 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 9 + */ + +#define WCL_CORE_1_FROM_WORLD_9 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_9_M (WCL_CORE_1_FROM_WORLD_9_V << WCL_CORE_1_FROM_WORLD_9_S) +#define WCL_CORE_1_FROM_WORLD_9_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_9_S 0 + +/* WCL_CORE_1_STATUSTABLE10_REG register + * Status register of world switch of entry 10 + */ + +#define WCL_CORE_1_STATUSTABLE10_REG (DR_REG_WORLD_CNTL_BASE + 0x4a4) + +/* WCL_CORE_1_CURRENT_10 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 10 + */ + +#define WCL_CORE_1_CURRENT_10 (BIT(5)) +#define WCL_CORE_1_CURRENT_10_M (WCL_CORE_1_CURRENT_10_V << WCL_CORE_1_CURRENT_10_S) +#define WCL_CORE_1_CURRENT_10_V 0x00000001 +#define WCL_CORE_1_CURRENT_10_S 5 + +/* WCL_CORE_1_FROM_ENTRY_10 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 10 + */ + +#define WCL_CORE_1_FROM_ENTRY_10 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_10_M (WCL_CORE_1_FROM_ENTRY_10_V << WCL_CORE_1_FROM_ENTRY_10_S) +#define WCL_CORE_1_FROM_ENTRY_10_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_10_S 1 + +/* WCL_CORE_1_FROM_WORLD_10 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 10 + */ + +#define WCL_CORE_1_FROM_WORLD_10 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_10_M (WCL_CORE_1_FROM_WORLD_10_V << WCL_CORE_1_FROM_WORLD_10_S) +#define WCL_CORE_1_FROM_WORLD_10_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_10_S 0 + +/* WCL_CORE_1_STATUSTABLE11_REG register + * Status register of world switch of entry 11 + */ + +#define WCL_CORE_1_STATUSTABLE11_REG (DR_REG_WORLD_CNTL_BASE + 0x4a8) + +/* WCL_CORE_1_CURRENT_11 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 11 + */ + +#define WCL_CORE_1_CURRENT_11 (BIT(5)) +#define WCL_CORE_1_CURRENT_11_M (WCL_CORE_1_CURRENT_11_V << WCL_CORE_1_CURRENT_11_S) +#define WCL_CORE_1_CURRENT_11_V 0x00000001 +#define WCL_CORE_1_CURRENT_11_S 5 + +/* WCL_CORE_1_FROM_ENTRY_11 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 11 + */ + +#define WCL_CORE_1_FROM_ENTRY_11 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_11_M (WCL_CORE_1_FROM_ENTRY_11_V << WCL_CORE_1_FROM_ENTRY_11_S) +#define WCL_CORE_1_FROM_ENTRY_11_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_11_S 1 + +/* WCL_CORE_1_FROM_WORLD_11 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 11 + */ + +#define WCL_CORE_1_FROM_WORLD_11 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_11_M (WCL_CORE_1_FROM_WORLD_11_V << WCL_CORE_1_FROM_WORLD_11_S) +#define WCL_CORE_1_FROM_WORLD_11_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_11_S 0 + +/* WCL_CORE_1_STATUSTABLE12_REG register + * Status register of world switch of entry 12 + */ + +#define WCL_CORE_1_STATUSTABLE12_REG (DR_REG_WORLD_CNTL_BASE + 0x4ac) + +/* WCL_CORE_1_CURRENT_12 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 12 + */ + +#define WCL_CORE_1_CURRENT_12 (BIT(5)) +#define WCL_CORE_1_CURRENT_12_M (WCL_CORE_1_CURRENT_12_V << WCL_CORE_1_CURRENT_12_S) +#define WCL_CORE_1_CURRENT_12_V 0x00000001 +#define WCL_CORE_1_CURRENT_12_S 5 + +/* WCL_CORE_1_FROM_ENTRY_12 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 12 + */ + +#define WCL_CORE_1_FROM_ENTRY_12 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_12_M (WCL_CORE_1_FROM_ENTRY_12_V << WCL_CORE_1_FROM_ENTRY_12_S) +#define WCL_CORE_1_FROM_ENTRY_12_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_12_S 1 + +/* WCL_CORE_1_FROM_WORLD_12 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 12 + */ + +#define WCL_CORE_1_FROM_WORLD_12 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_12_M (WCL_CORE_1_FROM_WORLD_12_V << WCL_CORE_1_FROM_WORLD_12_S) +#define WCL_CORE_1_FROM_WORLD_12_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_12_S 0 + +/* WCL_CORE_1_STATUSTABLE13_REG register + * Status register of world switch of entry 13 + */ + +#define WCL_CORE_1_STATUSTABLE13_REG (DR_REG_WORLD_CNTL_BASE + 0x4b0) + +/* WCL_CORE_1_CURRENT_13 : R/W; bitpos: [5]; default: 0; + * This bit is used to confirm whether the current state is in entry 13 + */ + +#define WCL_CORE_1_CURRENT_13 (BIT(5)) +#define WCL_CORE_1_CURRENT_13_M (WCL_CORE_1_CURRENT_13_V << WCL_CORE_1_CURRENT_13_S) +#define WCL_CORE_1_CURRENT_13_V 0x00000001 +#define WCL_CORE_1_CURRENT_13_S 5 + +/* WCL_CORE_1_FROM_ENTRY_13 : R/W; bitpos: [4:1]; default: 0; + * This filed is used to confirm in which entry before enter entry 13 + */ + +#define WCL_CORE_1_FROM_ENTRY_13 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_13_M (WCL_CORE_1_FROM_ENTRY_13_V << WCL_CORE_1_FROM_ENTRY_13_S) +#define WCL_CORE_1_FROM_ENTRY_13_V 0x0000000f +#define WCL_CORE_1_FROM_ENTRY_13_S 1 + +/* WCL_CORE_1_FROM_WORLD_13 : R/W; bitpos: [0]; default: 0; + * This bit is used to confirm world before enter entry 13 + */ + +#define WCL_CORE_1_FROM_WORLD_13 (BIT(0)) +#define WCL_CORE_1_FROM_WORLD_13_M (WCL_CORE_1_FROM_WORLD_13_V << WCL_CORE_1_FROM_WORLD_13_S) +#define WCL_CORE_1_FROM_WORLD_13_V 0x00000001 +#define WCL_CORE_1_FROM_WORLD_13_S 0 + +/* WCL_CORE_1_STATUSTABLE_CURRENT_REG register + * Status register of statustable current + */ + +#define WCL_CORE_1_STATUSTABLE_CURRENT_REG (DR_REG_WORLD_CNTL_BASE + 0x4fc) + +/* WCL_CORE_1_STATUSTABLE_CURRENT : R/W; bitpos: [13:1]; default: 0; + * This field is used to quickly read and rewrite the current field of all + * STATUSTABLE registers,for example,bit 1 represents the current field of + * STATUSTABLE1 + */ + +#define WCL_CORE_1_STATUSTABLE_CURRENT 0x00001fff +#define WCL_CORE_1_STATUSTABLE_CURRENT_M (WCL_CORE_1_STATUSTABLE_CURRENT_V << WCL_CORE_1_STATUSTABLE_CURRENT_S) +#define WCL_CORE_1_STATUSTABLE_CURRENT_V 0x00001fff +#define WCL_CORE_1_STATUSTABLE_CURRENT_S 1 + +/* WCL_CORE_1_MESSAGE_ADDR_REG register + * Clear writer_buffer write address configuration register + */ + +#define WCL_CORE_1_MESSAGE_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x500) + +/* WCL_CORE_1_MESSAGE_ADDR : R/W; bitpos: [31:0]; default: 0; + * This field is used to set address that need to write when enter WORLD0 + */ + +#define WCL_CORE_1_MESSAGE_ADDR 0xffffffff +#define WCL_CORE_1_MESSAGE_ADDR_M (WCL_CORE_1_MESSAGE_ADDR_V << WCL_CORE_1_MESSAGE_ADDR_S) +#define WCL_CORE_1_MESSAGE_ADDR_V 0xffffffff +#define WCL_CORE_1_MESSAGE_ADDR_S 0 + +/* WCL_CORE_1_MESSAGE_MAX_REG register + * Clear writer_buffer write number configuration register + */ + +#define WCL_CORE_1_MESSAGE_MAX_REG (DR_REG_WORLD_CNTL_BASE + 0x504) + +/* WCL_CORE_1_MESSAGE_MAX : R/W; bitpos: [3:0]; default: 0; + * This filed is used to set the max value of clear write_buffer + */ + +#define WCL_CORE_1_MESSAGE_MAX 0x0000000f +#define WCL_CORE_1_MESSAGE_MAX_M (WCL_CORE_1_MESSAGE_MAX_V << WCL_CORE_1_MESSAGE_MAX_S) +#define WCL_CORE_1_MESSAGE_MAX_V 0x0000000f +#define WCL_CORE_1_MESSAGE_MAX_S 0 + +/* WCL_CORE_1_MESSAGE_PHASE_REG register + * Clear writer_buffer status register + */ + +#define WCL_CORE_1_MESSAGE_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x508) + +/* WCL_CORE_1_MESSAGE_ADDRESSPHASE : RO; bitpos: [6]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, + * and is checking address. + */ + +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE (BIT(6)) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_M (WCL_CORE_1_MESSAGE_ADDRESSPHASE_V << WCL_CORE_1_MESSAGE_ADDRESSPHASE_S) +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_V 0x00000001 +#define WCL_CORE_1_MESSAGE_ADDRESSPHASE_S 6 + +/* WCL_CORE_1_MESSAGE_DATAPHASE : RO; bitpos: [5]; default: 0; + * If this bit is 1, it means that is checking clear write_buffer operation, + * and is checking data + */ + +#define WCL_CORE_1_MESSAGE_DATAPHASE (BIT(5)) +#define WCL_CORE_1_MESSAGE_DATAPHASE_M (WCL_CORE_1_MESSAGE_DATAPHASE_V << WCL_CORE_1_MESSAGE_DATAPHASE_S) +#define WCL_CORE_1_MESSAGE_DATAPHASE_V 0x00000001 +#define WCL_CORE_1_MESSAGE_DATAPHASE_S 5 + +/* WCL_CORE_1_MESSAGE_EXPECT : RO; bitpos: [4:1]; default: 0; + * This field indicates the data to be written next time + */ + +#define WCL_CORE_1_MESSAGE_EXPECT 0x0000000f +#define WCL_CORE_1_MESSAGE_EXPECT_M (WCL_CORE_1_MESSAGE_EXPECT_V << WCL_CORE_1_MESSAGE_EXPECT_S) +#define WCL_CORE_1_MESSAGE_EXPECT_V 0x0000000f +#define WCL_CORE_1_MESSAGE_EXPECT_S 1 + +/* WCL_CORE_1_MESSAGE_MATCH : RO; bitpos: [0]; default: 0; + * This bit indicates whether the check is successful + */ + +#define WCL_CORE_1_MESSAGE_MATCH (BIT(0)) +#define WCL_CORE_1_MESSAGE_MATCH_M (WCL_CORE_1_MESSAGE_MATCH_V << WCL_CORE_1_MESSAGE_MATCH_S) +#define WCL_CORE_1_MESSAGE_MATCH_V 0x00000001 +#define WCL_CORE_1_MESSAGE_MATCH_S 0 + +/* WCL_CORE_1_World_TRIGGER_ADDR_REG register + * Core_1 trigger address configuration Register + */ + +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x540) + +/* WCL_CORE_1_WORLD_TRIGGER_ADDR : RW; bitpos: [31:0]; default: 0; + * This field is used to configure the entry address from WORLD0 to + * WORLD1,when the CPU executes to this address,switch to WORLD1 + */ + +#define WCL_CORE_1_WORLD_TRIGGER_ADDR 0xffffffff +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_M (WCL_CORE_1_WORLD_TRIGGER_ADDR_V << WCL_CORE_1_WORLD_TRIGGER_ADDR_S) +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_V 0xffffffff +#define WCL_CORE_1_WORLD_TRIGGER_ADDR_S 0 + +/* WCL_CORE_1_World_PREPARE_REG register + * Core_1 prepare world configuration Register + */ + +#define WCL_CORE_1_WORLD_PREPARE_REG (DR_REG_WORLD_CNTL_BASE + 0x544) + +/* WCL_CORE_1_WORLD_PREPARE : R/W; bitpos: [1:0]; default: 0; + * This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means + * WORLD1 + */ + +#define WCL_CORE_1_WORLD_PREPARE 0x00000003 +#define WCL_CORE_1_WORLD_PREPARE_M (WCL_CORE_1_WORLD_PREPARE_V << WCL_CORE_1_WORLD_PREPARE_S) +#define WCL_CORE_1_WORLD_PREPARE_V 0x00000003 +#define WCL_CORE_1_WORLD_PREPARE_S 0 + +/* WCL_CORE_1_World_UPDATE_REG register + * Core_1 configuration update register + */ + +#define WCL_CORE_1_WORLD_UPDATE_REG (DR_REG_WORLD_CNTL_BASE + 0x548) + +/* WCL_CORE_1_UPDATE : WO; bitpos: [31:0]; default: 0; + * This field is used to update configuration completed, can write any + * value,the hardware only checks the write operation of this register and + * does not case about its value + */ + +#define WCL_CORE_1_UPDATE 0xffffffff +#define WCL_CORE_1_UPDATE_M (WCL_CORE_1_UPDATE_V << WCL_CORE_1_UPDATE_S) +#define WCL_CORE_1_UPDATE_V 0xffffffff +#define WCL_CORE_1_UPDATE_S 0 + +/* WCL_CORE_1_World_Cancel_REG register + * Core_1 configuration cancel register + */ + +#define WCL_CORE_1_WORLD_CANCEL_REG (DR_REG_WORLD_CNTL_BASE + 0x54c) + +/* WCL_CORE_1_WORLD_CANCEL : WO; bitpos: [31:0]; default: 0; + * This field is used to cancel switch world configuration,if the trigger + * address and update configuration complete,can use this register to cancel + * world switch. can write any value, the hardware only checks the write + * operation of this register and does not case about its value + */ + +#define WCL_CORE_1_WORLD_CANCEL 0xffffffff +#define WCL_CORE_1_WORLD_CANCEL_M (WCL_CORE_1_WORLD_CANCEL_V << WCL_CORE_1_WORLD_CANCEL_S) +#define WCL_CORE_1_WORLD_CANCEL_V 0xffffffff +#define WCL_CORE_1_WORLD_CANCEL_S 0 + +/* WCL_CORE_1_World_IRam0_REG register + * Core_1 Iram0 world register + */ + +#define WCL_CORE_1_WORLD_IRAM0_REG (DR_REG_WORLD_CNTL_BASE + 0x550) + +/* WCL_CORE_1_WORLD_IRAM0 : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Iram0 bus + */ + +#define WCL_CORE_1_WORLD_IRAM0 0x00000003 +#define WCL_CORE_1_WORLD_IRAM0_M (WCL_CORE_1_WORLD_IRAM0_V << WCL_CORE_1_WORLD_IRAM0_S) +#define WCL_CORE_1_WORLD_IRAM0_V 0x00000003 +#define WCL_CORE_1_WORLD_IRAM0_S 0 + +/* WCL_CORE_1_World_DRam0_PIF_REG register + * Core_1 dram0 and PIF world register + */ + +#define WCL_CORE_1_WORLD_DRAM0_PIF_REG (DR_REG_WORLD_CNTL_BASE + 0x554) + +/* WCL_CORE_1_WORLD_DRAM0_PIF : R/W; bitpos: [1:0]; default: 0; + * this field is used to read current world of Dram0 bus and PIF bus + */ + +#define WCL_CORE_1_WORLD_DRAM0_PIF 0x00000003 +#define WCL_CORE_1_WORLD_DRAM0_PIF_M (WCL_CORE_1_WORLD_DRAM0_PIF_V << WCL_CORE_1_WORLD_DRAM0_PIF_S) +#define WCL_CORE_1_WORLD_DRAM0_PIF_V 0x00000003 +#define WCL_CORE_1_WORLD_DRAM0_PIF_S 0 + +/* WCL_CORE_1_World_Phase_REG register + * Core_0 world status register + */ + +#define WCL_CORE_1_WORLD_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x558) + +/* WCL_CORE_1_WORLD_PHASE : RO; bitpos: [0]; default: 0; + * This bit indicates whether is preparing to switch to WORLD1,1 means value. + */ + +#define WCL_CORE_1_WORLD_PHASE (BIT(0)) +#define WCL_CORE_1_WORLD_PHASE_M (WCL_CORE_1_WORLD_PHASE_V << WCL_CORE_1_WORLD_PHASE_S) +#define WCL_CORE_1_WORLD_PHASE_V 0x00000001 +#define WCL_CORE_1_WORLD_PHASE_S 0 + +/* WCL_CORE_1_NMI_MASK_ENABLE_REG register + * Core_1 NMI mask enable register + */ + +#define WCL_CORE_1_NMI_MASK_ENABLE_REG (DR_REG_WORLD_CNTL_BASE + 0x580) + +/* WCL_CORE_1_NMI_MASK_ENABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to set NMI mask, it can write any value, when write + * this register,the hardware start masking NMI interrupt + */ + +#define WCL_CORE_1_NMI_MASK_ENABLE 0xffffffff +#define WCL_CORE_1_NMI_MASK_ENABLE_M (WCL_CORE_1_NMI_MASK_ENABLE_V << WCL_CORE_1_NMI_MASK_ENABLE_S) +#define WCL_CORE_1_NMI_MASK_ENABLE_V 0xffffffff +#define WCL_CORE_1_NMI_MASK_ENABLE_S 0 + +/* WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG register + * Core_1 NMI mask trigger addr register + */ + +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_REG (DR_REG_WORLD_CNTL_BASE + 0x584) + +/* WCL_CORE_1_NMI_MASK_TRIGGER_ADDR : R/W; bitpos: [31:0]; default: 0; + * this field to used to set trigger address + */ + +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR 0xffffffff +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_M (WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V << WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S) +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_V 0xffffffff +#define WCL_CORE_1_NMI_MASK_TRIGGER_ADDR_S 0 + +/* WCL_CORE_1_NMI_MASK_DISABLE_REG register + * Core_1 NMI mask disable register + */ + +#define WCL_CORE_1_NMI_MASK_DISABLE_REG (DR_REG_WORLD_CNTL_BASE + 0x588) + +/* WCL_CORE_1_NMI_MASK_DISABLE : WO; bitpos: [31:0]; default: 0; + * this field is used to disable NMI mask, it will not take effect + * immediately,only when the CPU executes to the trigger address will it + * start to cancel NMI mask + */ + +#define WCL_CORE_1_NMI_MASK_DISABLE 0xffffffff +#define WCL_CORE_1_NMI_MASK_DISABLE_M (WCL_CORE_1_NMI_MASK_DISABLE_V << WCL_CORE_1_NMI_MASK_DISABLE_S) +#define WCL_CORE_1_NMI_MASK_DISABLE_V 0xffffffff +#define WCL_CORE_1_NMI_MASK_DISABLE_S 0 + +/* WCL_CORE_1_NMI_MASK_CANCLE_REG register + * Core_1 NMI mask disable register + */ + +#define WCL_CORE_1_NMI_MASK_CANCLE_REG (DR_REG_WORLD_CNTL_BASE + 0x58c) + +/* WCL_CORE_1_NMI_MASK_CANCEL : WO; bitpos: [31:0]; default: 0; + * this field is used to cancel NMI mask disable function. + */ + +#define WCL_CORE_1_NMI_MASK_CANCEL 0xffffffff +#define WCL_CORE_1_NMI_MASK_CANCEL_M (WCL_CORE_1_NMI_MASK_CANCEL_V << WCL_CORE_1_NMI_MASK_CANCEL_S) +#define WCL_CORE_1_NMI_MASK_CANCEL_V 0xffffffff +#define WCL_CORE_1_NMI_MASK_CANCEL_S 0 + +/* WCL_CORE_1_NMI_MASK_REG register + * Core_1 NMI mask register + */ + +#define WCL_CORE_1_NMI_MASK_REG (DR_REG_WORLD_CNTL_BASE + 0x590) + +/* WCL_CORE_1_NMI_MASK : R/W; bitpos: [0]; default: 0; + * this bit is used to mask NMI interrupt,it can directly mask NMI interrupt + */ + +#define WCL_CORE_1_NMI_MASK (BIT(0)) +#define WCL_CORE_1_NMI_MASK_M (WCL_CORE_1_NMI_MASK_V << WCL_CORE_1_NMI_MASK_S) +#define WCL_CORE_1_NMI_MASK_V 0x00000001 +#define WCL_CORE_1_NMI_MASK_S 0 + +/* WCL_CORE_1_NMI_MASK_PHASE_REG register + * Core_1 NMI mask phase register + */ + +#define WCL_CORE_1_NMI_MASK_PHASE_REG (DR_REG_WORLD_CNTL_BASE + 0x594) + +/* WCL_CORE_1_NMI_MASK_PHASE : RO; bitpos: [0]; default: 0; + * this bit is used to indicates whether the NMI interrupt is being masked, + * 1 means NMI interrupt is being masked + */ + +#define WCL_CORE_1_NMI_MASK_PHASE (BIT(0)) +#define WCL_CORE_1_NMI_MASK_PHASE_M (WCL_CORE_1_NMI_MASK_PHASE_V << WCL_CORE_1_NMI_MASK_PHASE_S) +#define WCL_CORE_1_NMI_MASK_PHASE_V 0x00000001 +#define WCL_CORE_1_NMI_MASK_PHASE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_WCL_CORE_H */ diff --git a/boards/xtensa/esp32s3/common/kernel/Makefile b/boards/xtensa/esp32s3/common/kernel/Makefile index 5a08434340..05a0355e19 100644 --- a/boards/xtensa/esp32s3/common/kernel/Makefile +++ b/boards/xtensa/esp32s3/common/kernel/Makefile @@ -31,7 +31,6 @@ ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) USER_LDSCRIPT = $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)protected_memory.ld) USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld) USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) @@ -46,9 +45,12 @@ USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" # Source files +ASRCS = esp32s3_user_vectors.S CSRCS = esp32s3_userspace.c + +AOBJS = $(ASRCS:.S=$(OBJEXT)) COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) +OBJS = $(AOBJS) $(COBJS) ifeq ($(LD),$(CC)) LDSTARTGROUP ?= -Wl,--start-group @@ -65,6 +67,9 @@ endif all: $(TOPDIR)$(DELIM)nuttx_user.elf .PHONY: nuttx_user.elf depend clean distclean +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE,$<,$@) + $(COBJS): %$(OBJEXT): %.c $(call COMPILE,$<,$@) diff --git a/boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S b/boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S new file mode 100644 index 0000000000..fe3d3150b8 --- /dev/null +++ b/boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + + .file "esp32s3_user_vectors.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Medium-/High-priority interrupt vectors + ****************************************************************************/ + +/**************************************************************************** + * Name: _xtensa_level2_vector + ****************************************************************************/ + + .begin literal_prefix .xtensa_level2_vector + .section .xtensa_level2_vector.text, "ax" + .global _xtensa_level2_vector + .type _xtensa_level2_vector, @function + .align 4 + +_xtensa_level2_vector: + j __kernel_vector_table + 0x180 + + .size _xtensa_level2_vector, . - _xtensa_level2_vector + .end literal_prefix + +/**************************************************************************** + * Name: _xtensa_level3_vector + ****************************************************************************/ + + .begin literal_prefix .xtensa_level3_vector + .section .xtensa_level3_vector.text, "ax" + .global _xtensa_level3_vector + .type _xtensa_level3_vector, @function + .align 4 + +_xtensa_level3_vector: + j __kernel_vector_table + 0x1c0 + + .size _xtensa_level3_vector, . - _xtensa_level3_vector + .end literal_prefix + +/**************************************************************************** + * Name: _xtensa_level4_vector + ****************************************************************************/ + + .begin literal_prefix .xtensa_level4_vector + .section .xtensa_level4_vector.text, "ax" + .global _xtensa_level4_vector + .type _xtensa_level4_vector, @function + .align 4 + +_xtensa_level4_vector: + j __kernel_vector_table + 0x200 + + .size _xtensa_level4_vector, . - _xtensa_level4_vector + .end literal_prefix + +/**************************************************************************** + * Name: _xtensa_level5_vector + ****************************************************************************/ + + .begin literal_prefix .xtensa_level5_vector + .section .xtensa_level5_vector.text, "ax" + .global _xtensa_level5_vector + .type _xtensa_level5_vector, @function + .align 4 + +_xtensa_level5_vector: + j __kernel_vector_table + 0x240 + + .size _xtensa_level5_vector, . - _xtensa_level5_vector + .end literal_prefix + +/**************************************************************************** + * Name: _debug_exception_vector + ****************************************************************************/ + + .begin literal_prefix .debug_exception_vector + .section .debug_exception_vector.text, "ax" + .global _debug_exception_vector + .type _debug_exception_vector, @function + .align 4 + +_debug_exception_vector: + j __kernel_vector_table + 0x280 + + .size _debug_exception_vector, . - _debug_exception_vector + .end literal_prefix + +/**************************************************************************** + * Name: _nmi_exception_vector + ****************************************************************************/ + + .begin literal_prefix .nmi_exception_vector + .section .nmi_exception_vector.text, "ax" + .global _nmi_exception_vector + .type _nmi_exception_vector, @function + .align 4 + +_nmi_exception_vector: + j __kernel_vector_table + 0x2c0 + + .size _nmi_exception_vector, . - _nmi_exception_vector + .end literal_prefix + +/**************************************************************************** + * General exception vectors + ****************************************************************************/ + +/**************************************************************************** + * Name: _kernel_exception_vector + ****************************************************************************/ + + .begin literal_prefix .kernel_exception_vector + .section .kernel_exception_vector.text, "ax" + .global _kernel_exception_vector + .type _kernel_exception_vector, @function + .align 4 + +_kernel_exception_vector: + j __kernel_vector_table + 0x300 + + .size _kernel_exception_vector, . - _kernel_exception_vector + .end literal_prefix + +/**************************************************************************** + * Name: _user_exception_vector + ****************************************************************************/ + + .begin literal_prefix .user_exception_vector + .section .user_exception_vector.text, "ax" + .global _user_exception_vector + .type _user_exception_vector, @function + .align 4 + +_user_exception_vector: + j __kernel_vector_table + 0x340 + + .size _user_exception_vector, . - _user_exception_vector + .end literal_prefix + +/**************************************************************************** + * Name: _double_exception_vector + ****************************************************************************/ + + .begin literal_prefix .double_exception_vector + .section .double_exception_vector.text, "ax" + .global _double_exception_vector + .type _double_exception_vector, @function + .align 4 + +_double_exception_vector: + j __kernel_vector_table + 0x3c0 + + .size _double_exception_vector, . - _double_exception_vector + .end literal_prefix + +/**************************************************************************** + * Window exception vectors + ****************************************************************************/ + + .section .window_vectors.text, "ax" + +/**************************************************************************** + * Name: _window_overflow4 + ****************************************************************************/ + + .org 0x0 + .global _window_overflow4 +_window_overflow4: + s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/**************************************************************************** + * Name: _window_underflow4 + ****************************************************************************/ + + .org 0x40 + .global _window_underflow4 +_window_underflow4: + l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + rfwu + +/**************************************************************************** + * Name: _window_overflow8 + ****************************************************************************/ + + .org 0x80 + .global _window_overflow8 +_window_overflow8: + s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/**************************************************************************** + * Name: _window_underflow8 + ****************************************************************************/ + + .org 0xc0 + .global _window_underflow8 +_window_underflow8: + l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a7, a1, -12 /* a7 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + rfwu + +/**************************************************************************** + * Name: _window_overflow12 + ****************************************************************************/ + + .org 0x100 + .global _window_overflow12 +_window_overflow12: + s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + (used to find end of call[j]'s frame) */ + s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/**************************************************************************** + * Name: _window_underflow12 + ****************************************************************************/ + + .org 0x140 + .global _window_underflow12 +_window_underflow12: + l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a11, a1, -12 /* a11 <- call[i-1]'s sp + (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + rfwu diff --git a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld index 48fffb7551..a14a51b83c 100644 --- a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld +++ b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld @@ -48,8 +48,6 @@ __kdram_end = ORIGIN(KDRAM) + LENGTH(KDRAM); ENTRY(_stext) -_diram_i_start = 0x40378000; - SECTIONS { /* Send .iram0 code to iram */ @@ -104,6 +102,7 @@ SECTIONS _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) + esp32s3_userspace.*(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) *libkarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) *libkarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*) @@ -127,15 +126,6 @@ SECTIONS _iram_end = ABSOLUTE(.); } >KIRAM - .dram0.dummy (NOLOAD) : - { - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - . = ORIGIN(KDRAM) + MAX(_iram_end, _diram_i_start) - _diram_i_start; - } >KDRAM - /* Shared RAM */ .dram0.bss (NOLOAD) : @@ -203,6 +193,7 @@ SECTIONS KEEP (*(.jcr)) *(.dram1 .dram1.*) *libphy.a:(.rodata .rodata.*) + esp32s3_userspace.*(.rodata .rodata.*) *libkarch.a:esp32s3_spiflash.*(.rodata .rodata.*) *libkarch.a:xtensa_cpupause.*(.rodata .rodata.*) *libkarch.a:xtensa_copystate.*(.rodata .rodata.*) diff --git a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld index 7dc58edc18..f7022f8e10 100644 --- a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld +++ b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld @@ -51,17 +51,13 @@ MEMORY { - metadata (RX) : org = 0x0, len = 0x18 - ROM (RX) : org = 0x18, len = 0x100000 + metadata (RX) : org = 0x0, len = 0x30 + ROM (RX) : org = 0x30, len = 0x100000 - /* Below values assume the flash cache is on, and have the blocks this - * uses subtracted from the length of the various regions. The 'data access - * port' dram/drom regions map to the same iram/irom regions but are - * connected to the data port of the CPU and e.g. allow bytewise access. - */ + /* Instruction RAM */ - KIRAM (RWX) : org = SRAM_IRAM_ORG, len = 48K - UIRAM (RWX) : org = ORIGIN(KIRAM) + LENGTH(KIRAM), len = 64K + UIRAM (RWX) : org = SRAM_IRAM_ORG, len = 16K + KIRAM (RWX) : org = ORIGIN(UIRAM) + LENGTH(UIRAM), len = 32K /* Flash mapped instruction data. */ @@ -78,21 +74,21 @@ MEMORY /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ - KDRAM (RW) : org = SRAM_DRAM_ORG + 0x18000, len = 64K - UDRAM (RW) : org = ORIGIN(KDRAM) + LENGTH(KDRAM), len = 192K + KDRAM (RW) : org = ORIGIN(KIRAM) + LENGTH(KIRAM) - I_D_SRAM_OFFSET, len = 64K + UDRAM (RW) : org = ORIGIN(KDRAM) + LENGTH(KDRAM), len = 256K /* Flash mapped constant data */ /* See KIROM region documentation above for the meaning of the 0x20 offset. * - * The 0x18 offset for the UDROM region is a convenience for the User + * The 0x30 offset for the UDROM region is a convenience for the User * binary image generation following a custom image format, which defines * a "metadata" output section containing some information that the Kernel - * needs for properly configuring the External Flash MMU when loading the - * User application image. + * needs for properly configuring the External Flash MMU and initializing + * SRAM contents when loading the User application image. */ KDROM (R) : org = 0x3c000020, len = 0x80000 - 0x20 - UDROM (R) : org = 0x3c080018, len = 0x180000 - 0x18 + UDROM (R) : org = 0x3c080030, len = 0x180000 - 0x30 } diff --git a/boards/xtensa/esp32s3/common/scripts/user-space.ld b/boards/xtensa/esp32s3/common/scripts/user-space.ld index c39d191e11..1c7b60baf6 100644 --- a/boards/xtensa/esp32s3/common/scripts/user-space.ld +++ b/boards/xtensa/esp32s3/common/scripts/user-space.ld @@ -30,7 +30,17 @@ SECTIONS LONG(ADDR(.userspace)) LONG(LOADADDR(.userspace)) - LONG(SIZEOF(.userspace) + SIZEOF(.rodata)) + LONG(LOADADDR(.rodata) + SIZEOF(.rodata) - LOADADDR(.userspace)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) /* IROM metadata: * - Destination address (VMA) for IROM region @@ -45,6 +55,8 @@ SECTIONS /* section info */ + __kernel_vector_table = ORIGIN(KIRAM); + __ld_uirom_start = ORIGIN(UIROM); __ld_uirom_size = LENGTH(UIROM); __ld_uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); @@ -128,25 +140,61 @@ SECTIONS . = ALIGN(4); } >UDROM AT>ROM - .iram0.text : + .iram0.vectors : { _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + __vectors_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_exception_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN (16); + + __vectors_end = ABSOLUTE(.); + + *(.entry.text) + *(.init.literal) + *(.init) + + _init_end = ABSOLUTE(.); + } >UIRAM AT>ROM + + .iram0.text : + { + *(.iram1) *(.iram1.*) _iram_end = ABSOLUTE(.); } >UIRAM AT>ROM - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - .dram0.dummy (NOLOAD): - { - . = ORIGIN(UDRAM) + _iram_end - _iram_start; - } >UDRAM - /* Shared RAM */ .bss (NOLOAD) : @@ -170,6 +218,7 @@ SECTIONS *(.share.mem) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(8); _ebss = ABSOLUTE(.); diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig index 2fc6f11c44..b444f176ac 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig @@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1=y CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILD_PROTECTED=y @@ -25,18 +24,20 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_ESP32S3_UART0=y +CONFIG_ESP32S3_WCL=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NUTTX_USERSPACE=0x3c080018 +CONFIG_NUTTX_USERSPACE=0x3c080030 CONFIG_PASS1_BUILDIR="boards/xtensa/esp32s3/common/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688