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xtensa/esp32s3: Configure the PMS peripheral for Protected Mode

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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2022-11-17 17:10:59 -03:00 committed by Xiang Xiao
parent bfc40c74d0
commit 1ecaa4e672
24 changed files with 13779 additions and 114 deletions
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30
arch/xtensa/Kconfig
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@ -87,18 +87,18 @@ config ARCH_CHIP_ESP32S3
select ARCH_HAVE_BOOTLOADER select ARCH_HAVE_BOOTLOADER
select ARCH_HAVE_TESTSET select ARCH_HAVE_TESTSET
select ARCH_VECNOTIRQ select ARCH_VECNOTIRQ
select LIBC_ARCH_MEMCPY select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR select LIBC_ARCH_MEMCHR if BUILD_FLAT
select LIBC_ARCH_MEMCMP select LIBC_ARCH_MEMCMP if BUILD_FLAT
select LIBC_ARCH_MEMMOVE select LIBC_ARCH_MEMMOVE if BUILD_FLAT
select LIBC_ARCH_MEMSET select LIBC_ARCH_MEMSET if BUILD_FLAT
select LIBC_ARCH_STRCHR select LIBC_ARCH_STRCHR if BUILD_FLAT
select LIBC_ARCH_STRCMP select LIBC_ARCH_STRCMP if BUILD_FLAT
select LIBC_ARCH_STRCPY select LIBC_ARCH_STRCPY if BUILD_FLAT
select LIBC_ARCH_STRLCPY select LIBC_ARCH_STRLCPY if BUILD_FLAT
select LIBC_ARCH_STRNCPY select LIBC_ARCH_STRNCPY if BUILD_FLAT
select LIBC_ARCH_STRLEN select LIBC_ARCH_STRLEN if BUILD_FLAT
select LIBC_ARCH_STRNLEN select LIBC_ARCH_STRNLEN if BUILD_FLAT
---help--- ---help---
ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz. ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz.
Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz, Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz,
@ -129,7 +129,11 @@ config XTENSA_HAVE_DCACHE_LOCK
bool bool
default n default n
config XTENSA_HAVE_EXCEPTION_HOOKS config XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
bool
default n
config XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
bool bool
default n default n

4
arch/xtensa/src/common/xtensa_macros.S
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@ -179,7 +179,7 @@
rsr a0, EPC_1 + \level - 1 /* Save interruptee's PC */ rsr a0, EPC_1 + \level - 1 /* Save interruptee's PC */
s32i a0, sp, (4 * REG_PC) s32i a0, sp, (4 * REG_PC)
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
/* Perform chip-specific exception entry operations */ /* Perform chip-specific exception entry operations */
exception_entry_hook \level sp a0 exception_entry_hook \level sp a0
@ -207,7 +207,7 @@
l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_1 + \level - 1 wsr a0, EPC_1 + \level - 1
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
/* Perform chip-specific exception exit operations */ /* Perform chip-specific exception exit operations */
exception_exit_hook \level a2 a0 a1 exception_exit_hook \level a2 a0 a1

3
arch/xtensa/src/common/xtensa_swint.c
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@ -54,6 +54,9 @@ static void xtensa_registerdump(const uintptr_t *regs)
regs[REG_A8], regs[REG_A9], regs[REG_A10], regs[REG_A11], regs[REG_A8], regs[REG_A9], regs[REG_A10], regs[REG_A11],
regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]); regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]);
svcinfo(" PC: %08x PS: %08x\n", regs[REG_PC], regs[REG_PS]); svcinfo(" PC: %08x PS: %08x\n", regs[REG_PC], regs[REG_PS]);
#ifdef CONFIG_BUILD_PROTECTED
svcinfo(" INT_CTX: %08x\n", regs[REG_INT_CTX]);
#endif
} }
#endif #endif

8
arch/xtensa/src/common/xtensa_window_vector.S
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@ -98,7 +98,7 @@ _window_overflow4:
s32e a1, a5, -12 /* Save a1 to call[j+1]'s stack frame */ s32e a1, a5, -12 /* Save a1 to call[j+1]'s stack frame */
s32e a2, a5, -8 /* Save a2 to call[j+1]'s stack frame */ s32e a2, a5, -8 /* Save a2 to call[j+1]'s stack frame */
s32e a3, a5, -4 /* Save a3 to call[j+1]'s stack frame */ s32e a3, a5, -4 /* Save a3 to call[j+1]'s stack frame */
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
j _overflow4_exit_hook j _overflow4_exit_hook
#else #else
rfwo /* Rotates back to call[i] position */ rfwo /* Rotates back to call[i] position */
@ -125,7 +125,7 @@ _window_underflow4:
l32e a1, a5, -12 /* Restore a1 from call[i+1]'s stack frame */ l32e a1, a5, -12 /* Restore a1 from call[i+1]'s stack frame */
l32e a2, a5, -8 /* Restore a2 from call[i+1]'s stack frame */ l32e a2, a5, -8 /* Restore a2 from call[i+1]'s stack frame */
l32e a3, a5, -4 /* Restore a3 from call[i+1]'s stack frame */ l32e a3, a5, -4 /* Restore a3 from call[i+1]'s stack frame */
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
j _underflow4_exit_hook j _underflow4_exit_hook
#else #else
rfwu rfwu
@ -188,7 +188,7 @@ _window_overflow8:
s32e a5, a0, -28 /* Save a5 to call[j]'s stack frame */ s32e a5, a0, -28 /* Save a5 to call[j]'s stack frame */
s32e a6, a0, -24 /* Save a6 to call[j]'s stack frame */ s32e a6, a0, -24 /* Save a6 to call[j]'s stack frame */
s32e a7, a0, -20 /* Save a7 to call[j]'s stack frame */ s32e a7, a0, -20 /* Save a7 to call[j]'s stack frame */
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
j _overflow8_exit_hook j _overflow8_exit_hook
#else #else
rfwo /* Rotates back to call[i] position */ rfwo /* Rotates back to call[i] position */
@ -221,7 +221,7 @@ _window_underflow8:
l32e a5, a7, -28 /* Restore a5 from call[i]'s stack frame */ l32e a5, a7, -28 /* Restore a5 from call[i]'s stack frame */
l32e a6, a7, -24 /* Restore a6 from call[i]'s stack frame */ l32e a6, a7, -24 /* Restore a6 from call[i]'s stack frame */
l32e a7, a7, -20 /* Restore a7 from call[i]'s stack frame */ l32e a7, a7, -20 /* Restore a7 from call[i]'s stack frame */
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
j _underflow8_exit_hook j _underflow8_exit_hook
#else #else
rfwu rfwu

3
arch/xtensa/src/esp32/Kconfig
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@ -738,7 +738,8 @@ config ESP32_PID
bool "PID Controller" bool "PID Controller"
default n default n
select ARCH_USE_MPU select ARCH_USE_MPU
select XTENSA_HAVE_EXCEPTION_HOOKS if BUILD_PROTECTED select XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS if BUILD_PROTECTED
select XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS if BUILD_PROTECTED
depends on EXPERIMENTAL depends on EXPERIMENTAL
endmenu # ESP32 Peripheral Selection endmenu # ESP32 Peripheral Selection

2
arch/xtensa/src/esp32/Make.defs
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@ -25,7 +25,7 @@ include common/Make.defs
HEAD_CSRC = esp32_start.c esp32_wdt.c HEAD_CSRC = esp32_start.c esp32_wdt.c
ifeq ($(CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS),y) ifeq ($(CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS),y)
HEAD_ASRC += esp32_window_hooks.S HEAD_ASRC += esp32_window_hooks.S
endif endif

4
arch/xtensa/src/esp32/chip_macros.h
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@ -193,7 +193,7 @@
* *
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
.macro exception_entry_hook level reg_sp tmp .macro exception_entry_hook level reg_sp tmp
/* Save PID information from interruptee when handling User (Level 1) and /* Save PID information from interruptee when handling User (Level 1) and
@ -221,7 +221,7 @@
* *
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
.macro exception_exit_hook level reg_sp tmp1 tmp2 .macro exception_exit_hook level reg_sp tmp1 tmp2
/* Configure the PID Controller for the new execution context before /* Configure the PID Controller for the new execution context before

4
arch/xtensa/src/esp32/esp32_window_hooks.S
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@ -32,7 +32,7 @@
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS #ifdef CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
/* PID Controller is configured to switch to PID 0 when the CPU fetches /* PID Controller is configured to switch to PID 0 when the CPU fetches
* instruction from the following window exception vectors: * instruction from the following window exception vectors:
* - Window Overflow 4: mapped as Level 2 vector entry address * - Window Overflow 4: mapped as Level 2 vector entry address
@ -131,4 +131,4 @@ _underflow8_exit_hook:
rsr a1, misc1 rsr a1, misc1
rfwu rfwu
#endif /* CONFIG_XTENSA_HAVE_EXCEPTION_HOOKS */ #endif /* CONFIG_XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS */

6
arch/xtensa/src/esp32s3/Kconfig
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@ -400,6 +400,12 @@ config ESP32S3_RT_TIMER
---help--- ---help---
Real-Time Timer is relying upon the Systimer 1. Real-Time Timer is relying upon the Systimer 1.
config ESP32S3_WCL
bool "World Controller"
default n
select ARCH_USE_MPU
select XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS if BUILD_PROTECTED
endmenu # ESP32-S3 Peripheral Selection endmenu # ESP32-S3 Peripheral Selection
menu "SPI RAM Configuration" menu "SPI RAM Configuration"

185
arch/xtensa/src/esp32s3/chip_macros.h
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@ -33,6 +33,10 @@
#endif #endif
#endif #endif
#if defined(CONFIG_ESP32S3_WCL) && defined(CONFIG_BUILD_PROTECTED)
#include "hardware/esp32s3_wcl_core.h"
#endif
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
@ -43,13 +47,20 @@
#define HANDLER_SECTION .iram1 #define HANDLER_SECTION .iram1
#if defined(CONFIG_BUILD_PROTECTED) #if defined(CONFIG_ESP32S3_WCL) && defined(CONFIG_BUILD_PROTECTED)
#define xtensa_saveprivilege(regs,var) /* Definitions for the Worlds reserved for Kernel and Userspace */
#define xtensa_restoreprivilege(regs,var)
#define xtensa_lowerprivilege(regs) #define WCL_WORLD_KERNEL 0 /* Privileged */
#define xtensa_raiseprivilege(regs) #define WCL_WORLD_USER 1 /* Non-privileged */
/* Macros for privilege handling with the World Controller peripheral */
#define xtensa_saveprivilege(regs,var) ((var) = (regs)[REG_INT_CTX])
#define xtensa_restoreprivilege(regs,var) ((regs)[REG_INT_CTX] = (var))
#define xtensa_lowerprivilege(regs) ((regs)[REG_INT_CTX] = WCL_WORLD_USER)
#define xtensa_raiseprivilege(regs) ((regs)[REG_INT_CTX] = WCL_WORLD_KERNEL)
#endif #endif
@ -99,7 +110,169 @@
l32i a1, \tmp2, 0 /* a1 = *tmp2 */ l32i a1, \tmp2, 0 /* a1 = *tmp2 */
.endm .endm
#endif #endif
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Name: clear_wcl_write_buffer
*
* Description:
* Clear World Controller write buffer upon World 0 entry.
*
* Entry Conditions:
* tmp - Temporary register
*
****************************************************************************/
.macro clear_wcl_write_buffer tmp
/* Refer to ESP32-S3 Technical Reference Manual, section 16.4.3, for a
* detailed description of the write buffer clearing process.
*/
wsr a2, DEPC
movi \tmp, SOC_RTC_DATA_LOW
movi a2, 0
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
addi a2, a2, 1
s32i a2, \tmp, 0
l32i \tmp, \tmp, 0
memw
rsr a2, DEPC
.endm
/****************************************************************************
* Name: get_prev_world
*
* Description:
* Retrieve World information from interruptee.
*
* Entry Conditions:
* level - Interrupt level
* out - Temporary and output register
*
* Exit Conditions:
* World number to be returned will be written to "out" register.
*
****************************************************************************/
.macro get_prev_world level out
.ifeq (\level - 1) * (\level - 3)
.ifeq (\level - 1)
movi \out, WCL_CORE_0_STATUSTABLE1_REG
.endif
.ifeq (\level - 3)
movi \out, WCL_CORE_0_STATUSTABLE2_REG
.endif
l32i \out, \out, 0
extui \out, \out, 0, 1
.endif
.endm
/****************************************************************************
* Name: set_next_world
*
* Description:
* Configure the World Controller for the new execution context.
*
* Entry Conditions:
* reg_sp - Stack pointer
* tmp1 - Temporary register 1
* tmp2 - Temporary register 2
*
****************************************************************************/
.macro set_next_world reg_sp tmp1 tmp2
movi \tmp1, BIT(1)
movi \tmp2, WCL_CORE_0_WORLD_PREPARE_REG
s32i \tmp1, \tmp2, 0 /* Prepare execution on World 1 */
l32i \tmp1, \reg_sp, (4 * REG_PC)
movi \tmp2, WCL_CORE_0_WORLD_TRIGGER_ADDR_REG
s32i \tmp1, \tmp2, 0
movi \tmp1, BIT(0)
movi \tmp2, WCL_CORE_0_WORLD_UPDATE_REG
s32i \tmp1, \tmp2, 0
.endm
/****************************************************************************
* Name: exception_entry_hook
*
* Description:
* Perform chip-specific exception entry operations.
*
* Entry Conditions:
* level - Interrupt level
* reg_sp - Stack pointer
* tmp - Temporary register
*
****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
.macro exception_entry_hook level reg_sp tmp
.ifeq (\level - 1) * (\level - 3)
clear_wcl_write_buffer \tmp
/* Save World information from interruptee when handling User Exceptions
* (Level 1) and Software-triggered interrupts (Level 3).
*/
get_prev_world \level \tmp
s32i \tmp, \reg_sp, (4 * REG_INT_CTX) /* Save World into context */
.endif
.endm
#endif
/****************************************************************************
* Name: exception_exit_hook
*
* Description:
* Perform chip-specific exception exit operations.
*
* Entry Conditions:
* level - Interrupt level
* reg_sp - Stack pointer
* tmp1 - Temporary register 1
* tmp2 - Temporary register 2
*
****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
.macro exception_exit_hook level reg_sp tmp1 tmp2
/* Configure the World Controller for the new execution context before
* returning from User Exceptions (Level 1) and Software-triggered
* interrupts (Level 3).
*/
.ifeq (\level - 1) * (\level - 3)
movi \tmp1, 0x0
.ifeq (\level - 1)
movi \tmp2, WCL_CORE_0_STATUSTABLE1_REG
.endif
.ifeq (\level - 3)
movi \tmp2, WCL_CORE_0_STATUSTABLE2_REG
.endif
s32i \tmp1, \tmp2, 0 /* Clear the table entry */
l32i \tmp1, \reg_sp, (4 * REG_INT_CTX)
beqz \tmp1, 1f
set_next_world \reg_sp \tmp1 \tmp2
1:
memw
.endif
.endm
#endif
#endif /* __ASSEMBLY */
/**************************************************************************** /****************************************************************************
* Public Data * Public Data

12
arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
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@ -43,6 +43,10 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
#ifndef ALIGN_DOWN
# define ALIGN_DOWN(num, align) ((num) & ~((align) - 1))
#endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@ -66,7 +70,13 @@ void up_allocate_heap(void **heap_start, size_t *heap_size)
{ {
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
uintptr_t ubase = USERSPACE->us_dataend; uintptr_t ubase = USERSPACE->us_dataend;
uintptr_t utop = ets_rom_layout_p->dram0_rtos_reserved_start;
/* Align the heap top address to 256 bytes to match the PMS split address
* requirement.
*/
uintptr_t utop = ALIGN_DOWN(ets_rom_layout_p->dram0_rtos_reserved_start,
256);
size_t usize = utop - ubase; size_t usize = utop - ubase;
minfo("Heap: start=%" PRIxPTR " end=%" PRIxPTR " size=%zu\n", minfo("Heap: start=%" PRIxPTR " end=%" PRIxPTR " size=%zu\n",

7
arch/xtensa/src/esp32s3/esp32s3_irq.c
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@ -43,6 +43,7 @@
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
#include "esp32s3_smp.h" #include "esp32s3_smp.h"
#endif #endif
#include "esp32s3_userspace.h"
#include "hardware/esp32s3_interrupt_core0.h" #include "hardware/esp32s3_interrupt_core0.h"
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
#include "hardware/esp32s3_interrupt_core1.h" #include "hardware/esp32s3_interrupt_core1.h"
@ -420,9 +421,7 @@ void up_irqinitialize(void)
/* Hard code special cases. */ /* Hard code special cases. */
g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0); g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32S3_CPUINT_SOFTWARE1); g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32S3_CPUINT_SOFTWARE1);
g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32S3_CPUINT_SOFTWARE1); g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32S3_CPUINT_SOFTWARE1);
/* Initialize CPU interrupts */ /* Initialize CPU interrupts */
@ -439,6 +438,10 @@ void up_irqinitialize(void)
esp32s3_gpioirqinitialize(); esp32s3_gpioirqinitialize();
/* Initialize interrupt handler for the PMS violation ISR */
esp32s3_pmsirqinitialize();
#ifndef CONFIG_SUPPRESS_INTERRUPTS #ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts. Also clears PS.EXCM */ /* And finally, enable interrupts. Also clears PS.EXCM */

1629
arch/xtensa/src/esp32s3/esp32s3_userspace.c
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File diff suppressed because it is too large Load Diff

20
arch/xtensa/src/esp32s3/esp32s3_userspace.h
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@ -46,4 +46,24 @@
void esp32s3_userspace(void); void esp32s3_userspace(void);
#endif #endif
/****************************************************************************
* Name: esp32s3_pmsirqinitialize
*
* Description:
* Initialize interrupt handler for the PMS violation ISR.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void esp32s3_pmsirqinitialize(void);
#else
# define esp32s3_pmsirqinitialize()
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USERSPACE_H */ #endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USERSPACE_H */

1135
arch/xtensa/src/esp32s3/hardware/esp32s3_apb_ctrl.h Normal file
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File diff suppressed because it is too large Load Diff

8495
arch/xtensa/src/esp32s3/hardware/esp32s3_sensitive.h Normal file
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File diff suppressed because it is too large Load Diff

10
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
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@ -25,8 +25,10 @@
* Included Files * Included Files
****************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#endif
#include "xtensa_attr.h" #include "xtensa_attr.h"
@ -148,6 +150,8 @@
#define BIT(nr) (1UL << (nr)) #define BIT(nr) (1UL << (nr))
#ifndef __ASSEMBLY__
/* Write value to register */ /* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) #define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
@ -260,6 +264,8 @@
#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M)) #define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
#endif /* __ASSEMBLY__ */
/* Peripheral Clock */ /* Peripheral Clock */
#define APB_CLK_FREQ_ROM (40*1000000) #define APB_CLK_FREQ_ROM (40*1000000)
@ -435,6 +441,8 @@
#define RTC_PLL_FREQ_320M 320 #define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480 #define RTC_PLL_FREQ_480M 480
#ifndef __ASSEMBLY__
/**************************************************************************** /****************************************************************************
* Inline Functions * Inline Functions
****************************************************************************/ ****************************************************************************/
@ -486,4 +494,6 @@ static inline bool IRAM_ATTR esp32s3_ptr_exec(const void *p)
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
} }
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H */ #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SOC_H */

1908
arch/xtensa/src/esp32s3/hardware/esp32s3_wcl_core.h Normal file
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File diff suppressed because it is too large Load Diff

9
boards/xtensa/esp32s3/common/kernel/Makefile
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@ -31,7 +31,6 @@ ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT))
USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS)))))
USER_LDSCRIPT = $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)protected_memory.ld) USER_LDSCRIPT = $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)protected_memory.ld)
USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)user-space.ld) USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)user-space.ld)
USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32s3_rom.ld)
USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex)
USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin)
@ -46,9 +45,12 @@ USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
# Source files # Source files
ASRCS = esp32s3_user_vectors.S
CSRCS = esp32s3_userspace.c CSRCS = esp32s3_userspace.c
AOBJS = $(ASRCS:.S=$(OBJEXT))
COBJS = $(CSRCS:.c=$(OBJEXT)) COBJS = $(CSRCS:.c=$(OBJEXT))
OBJS = $(COBJS) OBJS = $(AOBJS) $(COBJS)
ifeq ($(LD),$(CC)) ifeq ($(LD),$(CC))
LDSTARTGROUP ?= -Wl,--start-group LDSTARTGROUP ?= -Wl,--start-group
@ -65,6 +67,9 @@ endif
all: $(TOPDIR)$(DELIM)nuttx_user.elf all: $(TOPDIR)$(DELIM)nuttx_user.elf
.PHONY: nuttx_user.elf depend clean distclean .PHONY: nuttx_user.elf depend clean distclean
$(AOBJS): %$(OBJEXT): %.S
$(call ASSEMBLE,$<,$@)
$(COBJS): %$(OBJEXT): %.c $(COBJS): %$(OBJEXT): %.c
$(call COMPILE,$<,$@) $(call COMPILE,$<,$@)

304
boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S Normal file
View File

@ -0,0 +1,304 @@
/****************************************************************************
* boards/xtensa/esp32s3/common/kernel/esp32s3_user_vectors.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
.file "esp32s3_user_vectors.S"
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include <arch/chip/core-isa.h>
#include <arch/xtensa/xtensa_abi.h>
#include <arch/xtensa/xtensa_specregs.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Medium-/High-priority interrupt vectors
****************************************************************************/
/****************************************************************************
* Name: _xtensa_level2_vector
****************************************************************************/
.begin literal_prefix .xtensa_level2_vector
.section .xtensa_level2_vector.text, "ax"
.global _xtensa_level2_vector
.type _xtensa_level2_vector, @function
.align 4
_xtensa_level2_vector:
j __kernel_vector_table + 0x180
.size _xtensa_level2_vector, . - _xtensa_level2_vector
.end literal_prefix
/****************************************************************************
* Name: _xtensa_level3_vector
****************************************************************************/
.begin literal_prefix .xtensa_level3_vector
.section .xtensa_level3_vector.text, "ax"
.global _xtensa_level3_vector
.type _xtensa_level3_vector, @function
.align 4
_xtensa_level3_vector:
j __kernel_vector_table + 0x1c0
.size _xtensa_level3_vector, . - _xtensa_level3_vector
.end literal_prefix
/****************************************************************************
* Name: _xtensa_level4_vector
****************************************************************************/
.begin literal_prefix .xtensa_level4_vector
.section .xtensa_level4_vector.text, "ax"
.global _xtensa_level4_vector
.type _xtensa_level4_vector, @function
.align 4
_xtensa_level4_vector:
j __kernel_vector_table + 0x200
.size _xtensa_level4_vector, . - _xtensa_level4_vector
.end literal_prefix
/****************************************************************************
* Name: _xtensa_level5_vector
****************************************************************************/
.begin literal_prefix .xtensa_level5_vector
.section .xtensa_level5_vector.text, "ax"
.global _xtensa_level5_vector
.type _xtensa_level5_vector, @function
.align 4
_xtensa_level5_vector:
j __kernel_vector_table + 0x240
.size _xtensa_level5_vector, . - _xtensa_level5_vector
.end literal_prefix
/****************************************************************************
* Name: _debug_exception_vector
****************************************************************************/
.begin literal_prefix .debug_exception_vector
.section .debug_exception_vector.text, "ax"
.global _debug_exception_vector
.type _debug_exception_vector, @function
.align 4
_debug_exception_vector:
j __kernel_vector_table + 0x280
.size _debug_exception_vector, . - _debug_exception_vector
.end literal_prefix
/****************************************************************************
* Name: _nmi_exception_vector
****************************************************************************/
.begin literal_prefix .nmi_exception_vector
.section .nmi_exception_vector.text, "ax"
.global _nmi_exception_vector
.type _nmi_exception_vector, @function
.align 4
_nmi_exception_vector:
j __kernel_vector_table + 0x2c0
.size _nmi_exception_vector, . - _nmi_exception_vector
.end literal_prefix
/****************************************************************************
* General exception vectors
****************************************************************************/
/****************************************************************************
* Name: _kernel_exception_vector
****************************************************************************/
.begin literal_prefix .kernel_exception_vector
.section .kernel_exception_vector.text, "ax"
.global _kernel_exception_vector
.type _kernel_exception_vector, @function
.align 4
_kernel_exception_vector:
j __kernel_vector_table + 0x300
.size _kernel_exception_vector, . - _kernel_exception_vector
.end literal_prefix
/****************************************************************************
* Name: _user_exception_vector
****************************************************************************/
.begin literal_prefix .user_exception_vector
.section .user_exception_vector.text, "ax"
.global _user_exception_vector
.type _user_exception_vector, @function
.align 4
_user_exception_vector:
j __kernel_vector_table + 0x340
.size _user_exception_vector, . - _user_exception_vector
.end literal_prefix
/****************************************************************************
* Name: _double_exception_vector
****************************************************************************/
.begin literal_prefix .double_exception_vector
.section .double_exception_vector.text, "ax"
.global _double_exception_vector
.type _double_exception_vector, @function
.align 4
_double_exception_vector:
j __kernel_vector_table + 0x3c0
.size _double_exception_vector, . - _double_exception_vector
.end literal_prefix
/****************************************************************************
* Window exception vectors
****************************************************************************/
.section .window_vectors.text, "ax"
/****************************************************************************
* Name: _window_overflow4
****************************************************************************/
.org 0x0
.global _window_overflow4
_window_overflow4:
s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
rfwo /* rotates back to call[i] position */
/****************************************************************************
* Name: _window_underflow4
****************************************************************************/
.org 0x40
.global _window_underflow4
_window_underflow4:
l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
rfwu
/****************************************************************************
* Name: _window_overflow8
****************************************************************************/
.org 0x80
.global _window_overflow8
_window_overflow8:
s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */
s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/****************************************************************************
* Name: _window_underflow8
****************************************************************************/
.org 0xc0
.global _window_underflow8
_window_underflow8:
l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */
rfwu
/****************************************************************************
* Name: _window_overflow12
****************************************************************************/
.org 0x100
.global _window_overflow12
_window_overflow12:
s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */
s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */
s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */
s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */
s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */
s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */
s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/****************************************************************************
* Name: _window_underflow12
****************************************************************************/
.org 0x140
.global _window_underflow12
_window_underflow12:
l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a11, a1, -12 /* a11 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */
l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */
l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */
l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */
l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */
l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */
l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */
rfwu

13
boards/xtensa/esp32s3/common/scripts/kernel-space.ld
View File

@ -48,8 +48,6 @@ __kdram_end = ORIGIN(KDRAM) + LENGTH(KDRAM);
ENTRY(_stext) ENTRY(_stext)
_diram_i_start = 0x40378000;
SECTIONS SECTIONS
{ {
/* Send .iram0 code to iram */ /* Send .iram0 code to iram */
@ -104,6 +102,7 @@ SECTIONS
_iram_text_start = ABSOLUTE(.); _iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*) *(.iram1 .iram1.*)
esp32s3_userspace.*(.literal .text .literal.* .text.*)
*librtc.a:(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*)
*libkarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) *libkarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
*libkarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*) *libkarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
@ -127,15 +126,6 @@ SECTIONS
_iram_end = ABSOLUTE(.); _iram_end = ABSOLUTE(.);
} >KIRAM } >KIRAM
.dram0.dummy (NOLOAD) :
{
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
. = ORIGIN(KDRAM) + MAX(_iram_end, _diram_i_start) - _diram_i_start;
} >KDRAM
/* Shared RAM */ /* Shared RAM */
.dram0.bss (NOLOAD) : .dram0.bss (NOLOAD) :
@ -203,6 +193,7 @@ SECTIONS
KEEP (*(.jcr)) KEEP (*(.jcr))
*(.dram1 .dram1.*) *(.dram1 .dram1.*)
*libphy.a:(.rodata .rodata.*) *libphy.a:(.rodata .rodata.*)
esp32s3_userspace.*(.rodata .rodata.*)
*libkarch.a:esp32s3_spiflash.*(.rodata .rodata.*) *libkarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libkarch.a:xtensa_cpupause.*(.rodata .rodata.*) *libkarch.a:xtensa_cpupause.*(.rodata .rodata.*)
*libkarch.a:xtensa_copystate.*(.rodata .rodata.*) *libkarch.a:xtensa_copystate.*(.rodata .rodata.*)

26
boards/xtensa/esp32s3/common/scripts/protected_memory.ld
View File

@ -51,17 +51,13 @@
MEMORY MEMORY
{ {
metadata (RX) : org = 0x0, len = 0x18 metadata (RX) : org = 0x0, len = 0x30
ROM (RX) : org = 0x18, len = 0x100000 ROM (RX) : org = 0x30, len = 0x100000
/* Below values assume the flash cache is on, and have the blocks this /* Instruction RAM */
* uses subtracted from the length of the various regions. The 'data access
* port' dram/drom regions map to the same iram/irom regions but are
* connected to the data port of the CPU and e.g. allow bytewise access.
*/
KIRAM (RWX) : org = SRAM_IRAM_ORG, len = 48K UIRAM (RWX) : org = SRAM_IRAM_ORG, len = 16K
UIRAM (RWX) : org = ORIGIN(KIRAM) + LENGTH(KIRAM), len = 64K KIRAM (RWX) : org = ORIGIN(UIRAM) + LENGTH(UIRAM), len = 32K
/* Flash mapped instruction data. */ /* Flash mapped instruction data. */
@ -78,21 +74,21 @@ MEMORY
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */
KDRAM (RW) : org = SRAM_DRAM_ORG + 0x18000, len = 64K KDRAM (RW) : org = ORIGIN(KIRAM) + LENGTH(KIRAM) - I_D_SRAM_OFFSET, len = 64K
UDRAM (RW) : org = ORIGIN(KDRAM) + LENGTH(KDRAM), len = 192K UDRAM (RW) : org = ORIGIN(KDRAM) + LENGTH(KDRAM), len = 256K
/* Flash mapped constant data */ /* Flash mapped constant data */
/* See KIROM region documentation above for the meaning of the 0x20 offset. /* See KIROM region documentation above for the meaning of the 0x20 offset.
* *
* The 0x18 offset for the UDROM region is a convenience for the User * The 0x30 offset for the UDROM region is a convenience for the User
* binary image generation following a custom image format, which defines * binary image generation following a custom image format, which defines
* a "metadata" output section containing some information that the Kernel * a "metadata" output section containing some information that the Kernel
* needs for properly configuring the External Flash MMU when loading the * needs for properly configuring the External Flash MMU and initializing
* User application image. * SRAM contents when loading the User application image.
*/ */
KDROM (R) : org = 0x3c000020, len = 0x80000 - 0x20 KDROM (R) : org = 0x3c000020, len = 0x80000 - 0x20
UDROM (R) : org = 0x3c080018, len = 0x180000 - 0x18 UDROM (R) : org = 0x3c080030, len = 0x180000 - 0x30
} }

71
boards/xtensa/esp32s3/common/scripts/user-space.ld
View File

@ -30,7 +30,17 @@ SECTIONS
LONG(ADDR(.userspace)) LONG(ADDR(.userspace))
LONG(LOADADDR(.userspace)) LONG(LOADADDR(.userspace))
LONG(SIZEOF(.userspace) + SIZEOF(.rodata)) LONG(LOADADDR(.rodata) + SIZEOF(.rodata) - LOADADDR(.userspace))
/* IRAM metadata:
* - Destination address (VMA) for IRAM region
* - Flash offset (LMA) for start of IRAM region
* - Size of IRAM region
*/
LONG(ADDR(.iram0.vectors))
LONG(LOADADDR(.iram0.vectors))
LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors))
/* IROM metadata: /* IROM metadata:
* - Destination address (VMA) for IROM region * - Destination address (VMA) for IROM region
@ -45,6 +55,8 @@ SECTIONS
/* section info */ /* section info */
__kernel_vector_table = ORIGIN(KIRAM);
__ld_uirom_start = ORIGIN(UIROM); __ld_uirom_start = ORIGIN(UIROM);
__ld_uirom_size = LENGTH(UIROM); __ld_uirom_size = LENGTH(UIROM);
__ld_uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); __ld_uirom_end = ORIGIN(UIROM) + LENGTH(UIROM);
@ -128,25 +140,61 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
} >UDROM AT>ROM } >UDROM AT>ROM
.iram0.text : .iram0.vectors :
{ {
_iram_start = ABSOLUTE(.); _iram_start = ABSOLUTE(.);
/* Vectors go to IRAM */
_init_start = ABSOLUTE(.);
__vectors_start = ABSOLUTE(.);
/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
. = 0x0;
KEEP (*(.window_vectors.text));
. = 0x180;
KEEP (*(.xtensa_level2_vector.text));
. = 0x1c0;
KEEP (*(.xtensa_level3_vector.text));
. = 0x200;
KEEP (*(.xtensa_level4_vector.text));
. = 0x240;
KEEP (*(.xtensa_level5_vector.text));
. = 0x280;
KEEP (*(.debug_exception_vector.text));
. = 0x2c0;
KEEP (*(.nmi_exception_vector.text));
. = 0x300;
KEEP (*(.kernel_exception_vector.text));
. = 0x340;
KEEP (*(.user_exception_vector.text));
. = 0x3c0;
KEEP (*(.double_exception_vector.text));
. = 0x400;
*(.*_vector.literal)
. = ALIGN (16);
__vectors_end = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
*(.init)
_init_end = ABSOLUTE(.);
} >UIRAM AT>ROM
.iram0.text :
{
*(.iram1) *(.iram1)
*(.iram1.*) *(.iram1.*)
_iram_end = ABSOLUTE(.); _iram_end = ABSOLUTE(.);
} >UIRAM AT>ROM } >UIRAM AT>ROM
/* This section is required to skip .iram0.text area because iram0_0_seg
* and dram0_0_seg reflect the same address space on different buses.
*/
.dram0.dummy (NOLOAD):
{
. = ORIGIN(UDRAM) + _iram_end - _iram_start;
} >UDRAM
/* Shared RAM */ /* Shared RAM */
.bss (NOLOAD) : .bss (NOLOAD) :
@ -170,6 +218,7 @@ SECTIONS
*(.share.mem) *(.share.mem)
*(.gnu.linkonce.b.*) *(.gnu.linkonce.b.*)
*(COMMON) *(COMMON)
. = ALIGN(8); . = ALIGN(8);
_ebss = ABSOLUTE(.); _ebss = ABSOLUTE(.);

5
boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig
View File

@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP="esp32s3"
CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3=y
CONFIG_ARCH_CHIP_ESP32S3WROOM1=y CONFIG_ARCH_CHIP_ESP32S3WROOM1=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_USE_MPU=y
CONFIG_ARCH_XTENSA=y CONFIG_ARCH_XTENSA=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILD_PROTECTED=y CONFIG_BUILD_PROTECTED=y
@ -25,18 +24,20 @@ CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_SYMBOLS=y
CONFIG_ESP32S3_UART0=y CONFIG_ESP32S3_UART0=y
CONFIG_ESP32S3_WCL=y
CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_IDLETHREAD_STACKSIZE=3072
CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64 CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NUTTX_USERSPACE=0x3c080018 CONFIG_NUTTX_USERSPACE=0x3c080030
CONFIG_PASS1_BUILDIR="boards/xtensa/esp32s3/common/kernel" CONFIG_PASS1_BUILDIR="boards/xtensa/esp32s3/common/kernel"
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688 CONFIG_RAM_SIZE=114688