SAM D20: More clock configuration logic (still incomplete)
This commit is contained in:
Gregory Nutt
parent
293484ffed
commit
1ed6677f57
@ -367,7 +367,19 @@ static inline void sam_osc8m_config(void)
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* Configure the DFLL based on settings in the board.h header file.
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* Depends on:
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*
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*
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* BOARD_DFLL_OPENLOOP - Boolean (defined / not defined)
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* BOARD_DFLL_TRACKAFTERFINELOCK - Boolean (defined / not defined)
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* BOARD_DFLL_KEEPLOCKONWAKEUP - Boolean (defined / not defined)
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* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
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* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
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* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
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* BOARD_DFLL_COARSEVALUE - Value
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* BOARD_DFLL_FINEVALUE - Value
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*
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* Closed Loop mode only:
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* BOARD_DFLL_MAXCOARSESTEP - Value
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* BOARD_DFLL_MAXFINESTEP - Value
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* BOARD_DFLL_MULTIPLIER - Value
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*
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* Input Parameters:
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* None
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@ -380,7 +392,64 @@ static inline void sam_osc8m_config(void)
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#if defined(CONFIG_SAMD_DFLL) || defined(BOARD_DFLL_ENABLE)
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static inline void sam_dfll_config(void)
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{
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#warning Missing logic
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uint16_t control;
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uint32_t regval;
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/* Set up the DFLL control register */
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control = SYSCTRL_DFLLCTRL_ENABLE; /* Enable the DFLL */
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#ifndef BOARD_DFLL_OPENLOOP
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control |= SYSCTRL_DFLLCTRL_MODE; /* Closed loop mode */
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#endif
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#ifndef BOARD_DFLL_TRACKAFTERFINELOCK
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control |= SYSCTRL_DFLLCTRL_STABLE; /* FINE calibration fixed after a fine lock */
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#endif
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#ifndef BOARD_DFLL_KEEPLOCKONWAKEUP
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control |= SYSCTRL_DFLLCTRL_LLAW; /* Lose lock after wake */
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#endif
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#ifndef BOARD_DFLL_ENABLECHILLCYCLE
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control |= SYSCTRL_DFLLCTRL_CCDIS; /* Chill cycle disable */
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#endif
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#ifndef BOARD_DFLL_QUICKLOCK
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control |= SYSCTRL_DFLLCTRL_QLDIS; /* Quick lock disable */
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#endif
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/* Then enable the DFLL (with ONDEMAND set to zero). */
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putreg16(control, SAM_SYSCTRL_DFLLCTRL);
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/* Wait for the DFLL to synchronize */
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while ((getreg32(SAM_SYSCTRL_PCLKSR) & SYSCTRL_INT_DFLLRDY) == 0);
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/* Set up the open loop mode multiplier register */
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#ifndef BOARD_DFLL_OPENLOOP
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regval = SYSCTRL_DFLLMUL_CSTEP(BOARD_DFLL_MAXCOARSESTEP) |
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SYSCTRL_DFLLMUL_FSTEP(BOARD_DFLL_MAXFINESTEP) |
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SYSCTRL_DFLLMUL_MUL(BOARD_DFLL_MULTIPLIER);
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putreg32(regval, SAM_SYSCTRL_DFLLMUL);
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#else
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putreg32(0, SAM_SYSCTRL_DFLLMUL);
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#endif
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/* Set up the DFLL value register */
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regval = SYSCTRL_DFLLVAL_COARSE(BOARD_DFLL_COARSEVALUE) |
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SYSCTRL_DFLLVAL_FINE(BOARD_DFLL_FINEVALUE);
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putreg32(regval, SAM_SYSCTRL_DFLLMUL);
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/* Finally, set the state of the ONDEMAND bit if necessary */
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#ifdef BOARD_DFLL_ONDEMAND
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control |= SYSCTRL_DFLLCTRL_ONDEMAND; /* On demand control */
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putreg16(control, SAM_SYSCTRL_DFLLCTRL);
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#endif
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}
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#else
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# define sam_dfll_config()
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@ -60,9 +60,7 @@
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* may vary with temperature changes.
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*/
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#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
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#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
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#define BOARD_DFLL48M_FREQUENCY 48000000 /* 48MHz Digital Frequency Locked Loop */
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#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
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/* The SAMD20 Xplained Pro has one on-board crystal:
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*
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@ -81,11 +79,11 @@
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*/
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#undef BOARD_XOSC_ENABLE
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#define BOARD_XOSC_FREQUENCY 12000000UL
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#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
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#define BOARD_XOSC_ISCRYSTAL 1
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#define BOARD_XOSC_AMPGC 1
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#define BOARD_XOSC_ONDEMAND 1
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#define BOARD_XOSC_FREQUENCY 12000000UL
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#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
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#define BOARD_XOSC_ISCRYSTAL 1
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#define BOARD_XOSC_AMPGC 1
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#define BOARD_XOSC_ONDEMAND 1
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#undef BOARD_XOSC_RUNINSTANDBY
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/* XOSC32 Configuration -- Not used
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@ -102,13 +100,13 @@
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*/
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#undef BOARD_XOSC32K_ENABLE
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#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
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#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S
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#define BOARD_XOSC32K_ISCRYSTAL 1
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#define BOARD_XOSC32K_AAMPEN 1
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#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
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#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S
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#define BOARD_XOSC32K_ISCRYSTAL 1
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#define BOARD_XOSC32K_AAMPEN 1
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#undef BOARD_XOSC32K_EN1KHZ
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#define BOARD_XOSC32K_EN32KHZ 1
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#define BOARD_XOSC32K_ONDEMAND 1
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#define BOARD_XOSC32K_EN32KHZ 1
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#define BOARD_XOSC32K_ONDEMAND 1
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#undef BOARD_XOSC32K_RUNINSTANDBY
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/* OSC32 Configuration -- not used
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@ -123,11 +121,11 @@
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*/
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#undef BOARD_OSC32K_ENABLE
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#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
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#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
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#define BOARD_OSC32K_EN1KHZ 1
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#define BOARD_OSC32K_EN32KHZ 1
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#define BOARD_OSC32K_ONDEMAND 1
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#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
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#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
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#define BOARD_OSC32K_EN1KHZ 1
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#define BOARD_OSC32K_EN32KHZ 1
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#define BOARD_OSC32K_ONDEMAND 1
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#undef BOARD_OSC32K_RUNINSTANDBY
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/* OSC8M Configuration -- always enabled
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@ -137,10 +135,63 @@
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* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
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#define BOARD_OSC8M_ONDEMAND 1
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#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
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#define BOARD_OSC8M_ONDEMAND 1
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#undef BOARD_OSC8M_RUNINSTANDBY
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#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
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/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
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* DFLL output frequency (Fdfll) is given by:
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*
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* Fdfll = DFLLmul * Frefclk
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* = (48000000/32768) * 32768 = 48MHz
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*
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* Where the reference clock is always the Generic Clock Channel 0 output.
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*
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* When operating in open-loop mode, the output frequency of the DFLL will
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* be determined by the values written to the DFLL Coarse Value bit group
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* and the DFLL Fine Value bit group in the DFLL Value register.
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*
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* BOARD_DFLL_OPENLOOP - Boolean (defined / not defined)
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* BOARD_DFLL_TRACKAFTERFINELOCK - Boolean (defined / not defined)
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* BOARD_DFLL_KEEPLOCKONWAKEUP - Boolean (defined / not defined)
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* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
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* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
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* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
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* BOARD_DFLL_COARSEVALUE - Value
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* BOARD_DFLL_FINEVALUE - Value
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*
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* Open Loop mode only:
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* BOARD_DFLL_MAXCOARSESTEP - Value
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* BOARD_DFLL_MAXFINESTEP - Value
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* BOARD_DFLL_MULTIPLIER - Value
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*
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* BOARD_DFLL_FREQUENCY - The resulting frequency
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*/
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#define BOARD_DFLL_OPENLOOP 1
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#undef BOARD_DFLL_ONDEMAND
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#undef BOARD_DFLL_RUNINSTANDBY
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/* DFLL open loop mode configuration */
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#define BOARD_DFLL_COARSEVALUE (0x1f / 4)
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#define BOARD_DFLL_FINEVALUE (0xff / 4)
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/* DFLL closed loop mode configuration */
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#define BOARD_DFLL_SRCGCLKGEN 1 /* GCLK generator channel 1 */
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#define BOARD_DFLL_MULTIPLIER 6
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#define BOARD_DFLL_QUICKLOCK 1
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#define BOARD_DFLL_TRACKAFTERFINELOCK 1
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#define BOARD_DFLL_KEEPLOCKONWAKEUP 1
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#define BOARD_DFLL_ENABLECHILLCYCLE 1
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#define BOARD_DFLL_MAXCOARSESTEP (0x1f / 4)
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#define BOARD_DFLL_MAXFINESTEP (0xff / 4)
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#define BOARD_DFLL_FREQUENCY (48000000)
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/* The source of the main clock is always GLCK_MAIN. Also called GCLKGEN[0], this is
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* the clock feeding the Power Manager. The Power Manager, in turn, generates main
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* clock which is divided down to produce the CPU, AHB, and APB clocks.
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@ -162,24 +213,9 @@
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* Fglckmain = Frefclk / Divider
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*/
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#define BOARD_GLCK_MAIN_SRC_OSC8M 1
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#define BOARD_GLCK_MAIN_DIVIDER 1
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#define BOARD_GLCK_MAIN_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GLCK_MAIN_DIVIDER)
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/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
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* DFLL output frequency (Fdfll) is given by:
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*
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* Fdfll = DFLLmul * Frefclk
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* = (48000000/32768) * 32768 = 48MHz
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*
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* Where the reference clock is always the Generic Clock Channel 0 output.
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*
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* NOTE: Nothing must be defined if the DFPLL is not used
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*/
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#define BOARD_DFLL48M_TARGET 48000000
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#define BOARD_DFLL48M_MUL (BOARD_DFLL0_TARGET / BOARD_GCK_MAIN_FREQUENCY)
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#define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MUL * BOARD_GCK_MAIN_FREQUENCY)
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#define BOARD_GLCK_MAIN_SRC_OSC8M 1
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#define BOARD_GLCK_MAIN_DIVIDER 1
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#define BOARD_GLCK_MAIN_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GLCK_MAIN_DIVIDER)
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/* Main clock dividers
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*
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@ -194,24 +230,24 @@
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* BOARD_APBC_FRQUENCY - In Hz
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*/
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#define BOARD_CPU_FAILDECT 1
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#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1
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#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1
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#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1
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#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1
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#define BOARD_CPU_FAILDECT 1
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#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1
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#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1
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#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1
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#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1
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/* Resulting frequencies */
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#define BOARD_MCK_FREQUENCY (BOARD_GLCK_MAIN_FREQUENCY)
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#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_MCK_FREQUENCY (BOARD_GLCK_MAIN_FREQUENCY)
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#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY)
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/* FLASH wait states */
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#define BOARD_FLASH_WAITSTATES 0
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#define BOARD_FLASH_WAITSTATES 0
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/* LED definitions ******************************************************************/
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/* There are three LEDs on board the SAMD20 Xplained Pro board: The EDBG
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@ -225,12 +261,12 @@
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/* LED index values for use with sam_setled() */
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#define BOARD_STATUS_LED 0
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#define BOARD_NLEDS 1
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#define BOARD_STATUS_LED 0
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#define BOARD_NLEDS 1
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/* LED bits for use with sam_setleds() */
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#define BOARD_STATUS LED_BIT (1 << BOARD_STATUS_LED)
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#define BOARD_STATUS LED_BIT (1 << BOARD_STATUS_LED)
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/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
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* control the LED as defined below. Thus if the LED is statically on, NuttX has
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@ -239,14 +275,14 @@
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* system has halted.
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*/
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#define LED_STARTED 0 /* STATUS LED=OFF */
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#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */
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#define LED_IRQSENABLED 0 /* STATUS LED=OFF */
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#define LED_STACKCREATED 1 /* STATUS LED=ON */
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#define LED_INIRQ 2 /* STATUS LED=no change */
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#define LED_SIGNAL 2 /* STATUS LED=no change */
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#define LED_ASSERTION 2 /* STATUS LED=no change */
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#define LED_PANIC 3 /* STATUS LED=flashing */
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#define LED_STARTED 0 /* STATUS LED=OFF */
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#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */
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#define LED_IRQSENABLED 0 /* STATUS LED=OFF */
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#define LED_STACKCREATED 1 /* STATUS LED=ON */
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#define LED_INIRQ 2 /* STATUS LED=no change */
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#define LED_SIGNAL 2 /* STATUS LED=no change */
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#define LED_ASSERTION 2 /* STATUS LED=no change */
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#define LED_PANIC 3 /* STATUS LED=flashing */
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/* Button definitions ***************************************************************/
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/* Mechanical buttons:
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@ -260,10 +296,10 @@
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/* The SAMD20 Xplained Pro supports one button: */
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#define BUTTON_SW0 0
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#define NUM_BUTTONS 1
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#define BUTTON_SW0 0
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#define NUM_BUTTONS 1
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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/************************************************************************************
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* Public Data
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