diff --git a/arch/arm/include/tms570/chip.h b/arch/arm/include/tms570/chip.h index dcff36c234..e153f95f87 100644 --- a/arch/arm/include/tms570/chip.h +++ b/arch/arm/include/tms570/chip.h @@ -355,6 +355,43 @@ # undef TMS570_RTP /* No RAM trace port (RTP) */ # undef TMS570_DMM /* No DMM */ +#elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +# undef TMS570_CORTEX_R4 /* Not Cortex-R4 family */ +# define TMS570_CORTEX_R4F 1 /* Cortex-R4F family */ +# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */ +# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */ +# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */ +# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */ +# define TMS570_PFLASH (3000*1024) /* 3072 KB Program FLASH */ +# define TMS570_SRAM (256*1024) /* 256 KB SRAM */ +# define TMS570_DFLASH (64*1024) /* 64 KB Data FLASH (EEPROM) */ +# define TMS570_NEMAC 1 /* One 10/100 Mbit EMAC */ +# define TMS570_FLEXRAY_NCH 2 /* Two Flexray channels */ +# define TMS570_NCAN 3 /* Three CAN */ +# define TMS570_NMIBADC 2 /* Two MiBADC */ +# define TMS570_MIBADC_NCH 24 /* 24 MibADC channels */ +# define TMS570_NN2HET 2 /* Two N2HET */ +# define TMS570_N2HET_NCH 44 /* 44 N2HET channels */ +# undef TMS570_EPWM_NCH /* 14 ePWM channels */ +# undef TMS570_ECAP_NCH /* 6 eCAP channels */ +# undef TMS570_EQEP_NCH /* 2 eQEP channels */ +# define TMS570_NMIBSPI 3 /* 3 MibSPI */ +# define TMS570_MIBSPI1_NCS 6 /* MibSPI1: 6 chip selects */ +# define TMS570_MIBSPI2_NCS 6 /* MibSPI2: 6 chip selects */ +# define TMS570_MIBSPI3_NCS 4 /* MibSPI3: 4 chip selects */ +# define TMS570_NSPI 2 /* Two SPI */ +# define TMS570_SPI1_NCS 2 /* SPI1: Two chip selects */ +# define TMS570_SPI2_NCS 1 /* SPI2: One chip selects */ +# define TMS570_NSCI 2 /* Two SCI */ +# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */ +# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */ +# define TMS570_NI2C 1 /* One I2C */ +# define TMS570_NGPIOINT 16 /* 16 GPIO interrupts */ +# define TMS570_NEMIF16 1 /* One EMIF 16-bit data */ +# define TMS570_ETM 1 /* 32-bit ETM (trace) */ +# define TMS570_RTP 1 /* 16-bit trace port (RTP) */ +# define TMS570_DMM 1 /* 16-bit DMM */ + #else # error Unrecognized TMS570 chip #endif diff --git a/arch/arm/include/tms570/irq.h b/arch/arm/include/tms570/irq.h index f83fad69de..1c4071d43a 100644 --- a/arch/arm/include/tms570/irq.h +++ b/arch/arm/include/tms570/irq.h @@ -72,6 +72,8 @@ # error No IRQ definitions for the TMS570LS0714ZWT #elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT) # error No IRQ definitions for the TMS570LS1227ZWT +#elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +# include #else # error "Unrecognized Hercules chip" #endif @@ -111,4 +113,3 @@ extern "C" #endif #endif /* __ARCH_ARM_INCLUDE_TMS570_IRQ_H */ - diff --git a/arch/arm/src/armv7-r/arm_fpuconfig.S b/arch/arm/src/armv7-r/arm_fpuconfig.S index 7f81415ad4..a7837fd94b 100644 --- a/arch/arm/src/armv7-r/arm_fpuconfig.S +++ b/arch/arm/src/armv7-r/arm_fpuconfig.S @@ -47,9 +47,9 @@ .globl arm_fpuconfig #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified .file "arm_fpuconfig.S" diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S index 9de8e405b7..1fbac09984 100644 --- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S +++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S @@ -55,9 +55,9 @@ .globl up_fullcontextrestore #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index a081d230b6..9042d25a43 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -139,9 +139,9 @@ .global g_idle_topstack /* Top of the initial/IDLE stack */ #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified .file "arm_head.S" diff --git a/arch/arm/src/armv7-r/arm_initialstate.c b/arch/arm/src/armv7-r/arm_initialstate.c index 2150020510..d5986f7c17 100644 --- a/arch/arm/src/armv7-r/arm_initialstate.c +++ b/arch/arm/src/armv7-r/arm_initialstate.c @@ -132,6 +132,8 @@ void up_initial_state(struct tcb_s *tcb) #ifndef CONFIG_ARMV7R_DECODEFIQ cpsr |= PSR_F_BIT; + cpsr |= PSR_A_BIT; + cpsr |= PSR_E_BIT; #endif /* !CONFIG_ARMV7R_DECODEFIQ */ #endif /* CONFIG_SUPPRESS_INTERRUPTS */ diff --git a/arch/arm/src/armv7-r/arm_restorefpu.S b/arch/arm/src/armv7-r/arm_restorefpu.S index 1557986e55..f189691b4c 100644 --- a/arch/arm/src/armv7-r/arm_restorefpu.S +++ b/arch/arm/src/armv7-r/arm_restorefpu.S @@ -50,9 +50,9 @@ .globl up_restorefpu #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified .file "arm_restorefpu.S" @@ -107,4 +107,3 @@ up_restorefpu: .size up_restorefpu, .-up_restorefpu #endif /* CONFIG_ARCH_FPU */ .end - diff --git a/arch/arm/src/armv7-r/arm_saveusercontext.S b/arch/arm/src/armv7-r/arm_saveusercontext.S index 19b198077c..babeb5337c 100644 --- a/arch/arm/src/armv7-r/arm_saveusercontext.S +++ b/arch/arm/src/armv7-r/arm_saveusercontext.S @@ -47,9 +47,9 @@ .globl up_saveusercontext #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified .file "arm_saveusercontext.S" diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c index a51d660cb4..6491961647 100644 --- a/arch/arm/src/armv7-r/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c @@ -151,7 +151,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) */ CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver; - CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT); + CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_E_BIT); /* And make sure that the saved context in the TCB is the same * as the interrupt return context. @@ -182,7 +182,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) */ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; - tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT); + tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT | PSR_A_BIT | PSR_E_BIT); } } diff --git a/arch/arm/src/armv7-r/arm_signal_handler.S b/arch/arm/src/armv7-r/arm_signal_handler.S index f2812a934f..fb715241b9 100644 --- a/arch/arm/src/armv7-r/arm_signal_handler.S +++ b/arch/arm/src/armv7-r/arm_signal_handler.S @@ -48,9 +48,9 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_FPU - .cpu cortex-r4 -#else .cpu cortex-r4f +#else + .cpu cortex-r4 #endif .syntax unified .file "arm_signal_handler.S" diff --git a/arch/arm/src/tms570/Kconfig b/arch/arm/src/tms570/Kconfig index 7c2f6a8bf8..662c840333 100644 --- a/arch/arm/src/tms570/Kconfig +++ b/arch/arm/src/tms570/Kconfig @@ -13,6 +13,26 @@ config TMS570_HAVE_SCI2 bool default n +config TMS570_HAVE_SPI1 + bool + default n + +config TMS570_HAVE_SPI2 + bool + default n + +config TMS570_HAVE_SPI3 + bool + default n + +config TMS570_HAVE_SPI4 + bool + default n + +config TMS570_HAVE_SPI5 + bool + default n + # Summary Configurations # Chip Selection @@ -53,6 +73,16 @@ config ARCH_CHIP_TMS570LS1227ZWT select ARCH_CORTEXR4F select TMS570_HAVE_SCI2 +config ARCH_CHIP_TMS570LS3137ZWT + bool "TI TMS570LS3137ZWT" + select ARCH_CORTEXR4F + select TMS570_HAVE_SCI2 + select TMS570_HAVE_SPI1 + select TMS570_HAVE_SPI2 + select TMS570_HAVE_SPI3 + select TMS570_HAVE_SPI4 + select TMS570_HAVE_SPI5 + endchoice # TI TMS570 Chip Selection menu "TMS570 Peripheral Support" @@ -81,9 +111,40 @@ config TMS570_DCAN1 bool "Controller Area Network 1 (D" default n -config TMS570_MIBASPI1 - bool "Multi-Buffered Serial Peripheral Interface Module (MibSPI1)" +config TMS570_SPI1 + bool "SPI1" default n + depends on TMS570_HAVE_SPI4 + select SPI + select TMS570_SPI + +config TMS570_SPI2 + bool "SPI2" + default n + depends on TMS570_HAVE_SPI2 + select SPI + select TMS570_SPI + +config TMS570_SPI3 + bool "SPI3" + default n + depends on TMS570_HAVE_SPI3 + select SPI + select TMS570_SPI + +config TMS570_SPI4 + bool "SPI4" + default n + depends on TMS570_HAVE_SPI4 + select SPI + select TMS570_SPI + +config TMS570_SPI5 + bool "SPI5" + default n + depends on TMS570_HAVE_SPI5 + select SPI + select TMS570_SPI config TMS570_SCI1 bool "Serial Communication Interface 1 (SCI1)" diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs index c1103a2f01..9960c69146 100644 --- a/arch/arm/src/tms570/Make.defs +++ b/arch/arm/src/tms570/Make.defs @@ -40,7 +40,7 @@ HEAD_ASRC = arm_vectortab.S # Common assembly language files -CMN_ASRCS += arm_vectors.S arm_head.S arm_fullcontextrestore.S +CMN_ASRCS += arm_vectortab.S arm_vectors.S arm_head.S arm_fullcontextrestore.S CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S arm_vfork.S CMN_ASRCS += arm_testset.S arm_fetchadd.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S @@ -102,7 +102,7 @@ CHIP_ASRCS = # SAMA5-specific C source files CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_esm.c tms570_gio.c -CHIP_CSRCS += tms570_irq.c tms570_lowputc.c tms570_serial.c +CHIP_CSRCS += tms570_irq.c tms570_lowputc.c tms570_serial.c tms570_spi.c # Configuration dependent C and assembly language files diff --git a/arch/arm/src/tms570/chip/tms570_memorymap.h b/arch/arm/src/tms570/chip/tms570_memorymap.h index dc452cdaee..fafb946b79 100644 --- a/arch/arm/src/tms570/chip/tms570_memorymap.h +++ b/arch/arm/src/tms570/chip/tms570_memorymap.h @@ -56,6 +56,8 @@ # error No memory map for the TMS570LS0714ZWT #elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT) # error No memory map for the TMS570LS1227ZWT +#elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +# include "chip/tms570ls31xx_memorymap.h" #else # error "Unrecognized Hercules chip" #endif diff --git a/arch/arm/src/tms570/chip/tms570_pinmux.h b/arch/arm/src/tms570/chip/tms570_pinmux.h index 281fc09b9f..af97106b7c 100644 --- a/arch/arm/src/tms570/chip/tms570_pinmux.h +++ b/arch/arm/src/tms570/chip/tms570_pinmux.h @@ -56,6 +56,8 @@ # error No pin multiplexing for the TMS570LS0714ZWT #elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT) # error No pin multiplexing for the TMS570LS1227ZWT +#elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +# include "chip/tms570ls04x03x_pinmux.h" #else # error "Unrecognized Hercules chip" #endif diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h index 8ed50d1b4a..8357d8923e 100644 --- a/arch/arm/src/tms570/chip/tms570_sys.h +++ b/arch/arm/src/tms570/chip/tms570_sys.h @@ -176,6 +176,9 @@ /* Register Bit-Field Definitions *******************************************************************/ +#define SYS_GLBSTAT_OSC_ERR_MASK (0x01) +#define SYS_GLBSTAT_OSC_ERR_CLR (0x0301) + /* SYS Pin Control Register 1 */ #define SYS_PC1_ECPCLKFUN (1 << 0) /* Bit 0: ECLK function */ @@ -221,13 +224,17 @@ #define SYS_CSDIS_CLKSR3OFF (1 << 3) /* Bit 3: Clock source 3 */ #define SYS_CSDIS_CLKSR4OFF (1 << 4) /* Bit 4: Clock source 4 */ #define SYS_CSDIS_CLKSR5OFF (1 << 5) /* Bit 5: Clock source 5 */ -#define SYS_CSDIS_CLKSROFFALL (0x3b) +#define SYS_CSDIS_CLKSR6OFF (1 << 6) /* Bit 4: Clock source 4 */ +#define SYS_CSDIS_CLKSR7OFF (1 << 7) /* Bit 5: Clock source 5 */ +#define SYS_CSDIS_CLKSROFFALL (0xff) #define SYS_CSDIS_CLKSRC_OSC SYS_CSDIS_CLKSR0OFF /* Oscillator */ -#define SYS_CSDIS_CLKSRC_PLL SYS_CSDIS_CLKSR1OFF /* PLL */ -#define SYS_CSDIS_CLKSRC_EXTCLKIN SYS_CSDIS_CLKSR3OFF /* EXTCLKIN */ +#define SYS_CSDIS_CLKSRC_PLL1 SYS_CSDIS_CLKSR1OFF /* PLL1 */ +#define SYS_CSDIS_CLKSRC_EXTCLKIN1 SYS_CSDIS_CLKSR3OFF /* EXTCLKIN */ #define SYS_CSDIS_CLKSRC_LFLPO SYS_CSDIS_CLKSR4OFF /* Low Frequency LPO (Low Power Oscillator) clock */ #define SYS_CSDIS_CLKSRC_HFLPO SYS_CSDIS_CLKSR5OFF /* High Frequency LPO (Low Power Oscillator) clock */ +#define SYS_CSDIS_CLKSRC_PLL2 SYS_CSDIS_CLKSR6OFF /* PLL2 */ +#define SYS_CSDIS_CLKSRC_EXTCLKIN2 SYS_CSDIS_CLKSR7OFF /* EXTCLKIN2 */ /* Clock Domain Disable Register, Clock Domain Disable Set Register, and Clock Domain * Disable Clear Register. @@ -339,6 +346,29 @@ # define SYS_VCLKASRC_VCLKA1S_EXTERNAL2 SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_EXTERNAL2) # define SYS_VCLKASRC_VCLKA1S_VCLK SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_VCLK) +#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +#define SYS_VCLKASRC_VCLKA2S_SHIFT (8) /* Bits 0-3: Peripheral asynchronous clock2 source */ +#define SYS_VCLKASRC_VCLKA2S_MASK (15 << SYS_VCLKASRC_VCLKA2S_SHIFT) +# define SYS_VCLKASRC_VCLKA2S_SRC0 (0 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source0 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC1 (1 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source1 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC2 (2 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source2 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC3 (3 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source3 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC4 (4 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source4 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC5 (5 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source5 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC6 (6 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source6 for VCLKA2S */ +# define SYS_VCLKASRC_VCLKA2S_SRC7 (7 << SYS_VCLKASRC_VCLKA2S_SHIFT) /* Clock source7 for VCLKA2S */ + +# define SYS_VCLKASRC_VCLKA2S(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA2S_SHIFT) +# define SYS_VCLKASRC_VCLKA2S_OSC SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_OSC) +# define SYS_VCLKASRC_VCLKA2S_PLL1 SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_PLL1) +# define SYS_VCLKASRC_VCLKA2S_EXTERNAL1 SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_EXTERNAL1) +# define SYS_VCLKASRC_VCLKA2S_LPOLOW SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_LPOLOW) +# define SYS_VCLKASRC_VCLKA2S_LPOHIGH SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_LPOHIGH) +# define SYS_VCLKASRC_VCLKA2S_PLL2 SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_PLL2) +# define SYS_VCLKASRC_VCLKA2S_EXTERNAL2 SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_EXTERNAL2) +# define SYS_VCLKASRC_VCLKA2S_VCLK SYS_VCLKASRC_VCLKA2S(SYS_CLKSRC_VCLK) +#endif + /* RTI Clock Source Register */ #define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */ @@ -401,7 +431,16 @@ #if defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ) || defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ) /* From TMS570LS0x32 Data Sheet */ +# define SYS_MSIENA_RAM (1 << 0) +# define SYS_MSIENA_VIM_RAM (1 << 2) +# define SYS_MSIENA_N2HET_RAM (1 << 3) +# define SYS_MSIENA_HTU_RAM (1 << 4) +# define SYS_MSIENA_DCAN1_RAM (1 << 5) +# define SYS_MSIENA_DCAN2_RAM (1 << 6) +# define SYS_MSIENA_MIBSPI1_RAM (1 << 7) +# define SYS_MSIENA_MIBADC_RAM (1 << 8) +#elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) # define SYS_MSIENA_RAM (1 << 0) # define SYS_MSIENA_VIM_RAM (1 << 2) # define SYS_MSIENA_N2HET_RAM (1 << 3) @@ -439,7 +478,7 @@ #define SYS_PLLCTL1_MASKSLIP_SHIFT (29) /* Bits 29-30: Mask detection of PLL slip */ #define SYS_PLLCTL1_MASKSLIP_MASK (3 << SYS_PLLCTL1_MASKSLIP_SHIFT) # define SYS_PLLCTL1_MASKSLIP_DISABLE (0 << SYS_PLLCTL1_MASKSLIP_SHIFT) /* All values but 2 disable */ -# define SYS_PLLCTL1_MASKSLIP_ENABLE (2 << SYS_PLLCTL1_MASKSLIP_SHIFT) +# define SYS_PLLCTL1_MASKSLIP_ENABLE (1 << SYS_PLLCTL1_MASKSLIP_SHIFT) #define SYS_PLLCTL1_ROS (1 << 31) /* Bit 31: Reset on PLL Slip */ /* PLL Control Register 2 */ diff --git a/arch/arm/src/tms570/chip/tms570_sys2.h b/arch/arm/src/tms570/chip/tms570_sys2.h index 9edb33cd39..9772b8dd23 100644 --- a/arch/arm/src/tms570/chip/tms570_sys2.h +++ b/arch/arm/src/tms570/chip/tms570_sys2.h @@ -62,6 +62,8 @@ #define TMS570_SYS2_DIEDH_REG1_OFFSET 0x00f4 /* Die Identification Register Upper Word */ #define TMS570_SYS2_DIEDL_REG2_OFFSET 0x00f8 /* Die Identification Register Lower Word */ #define TMS570_SYS2_DIEDH_REG3_OFFSET 0x00fc /* Die Identification Register Upper Word */ +#define TMS570_SYS2_CLK2CNTRL_OFFSET 0x003c +#define TMS570_SYS2_VCLKACON1_OFFSET 0x0040 /* Register Addresses *******************************************************************************/ @@ -72,6 +74,8 @@ #define TMS570_SYS2_DIEDH_REG1 (TMS570_SYS2_BASE+TMS570_SYS2_DIEDH_REG1_OFFSET) #define TMS570_SYS2_DIEDL_REG2 (TMS570_SYS2_BASE+TMS570_SYS2_DIEDL_REG2_OFFSET) #define TMS570_SYS2_DIEDH_REG3 (TMS570_SYS2_BASE+TMS570_SYS2_DIEDH_REG3_OFFSET) +#define TMS570_SYS2_CLK2CNTRL (TMS570_SYS2_BASE+TMS570_SYS2_CLK2CNTRL_OFFSET) +#define TMS570_SYS2_VCLKACON1 (TMS570_SYS2_BASE+TMS570_SYS2_VCLKACON1_OFFSET) /* Register Bit-Field Definitions *******************************************************************/ @@ -90,4 +94,66 @@ /* Die Identification Register Upper Word */ #define SYS2_DIEDH_REG3_ +#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) +#define SYS_VCLKASRC_VCLKA3R_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock2 source */ +#define SYS_VCLKASRC_VCLKA3R_MASK (15 << SYS_VCLKASRC_VCLKA3R_SHIFT) +# define SYS_VCLKASRC_VCLKA3R(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA3R_SHIFT) +# define SYS_VCLKASRC_VCLKA3R_OSC SYS_VCLKASRC_VCLKA3R(0) +# define SYS_VCLKASRC_VCLKA3R_PLL1 SYS_VCLKASRC_VCLKA3R(1) +# define SYS_VCLKASRC_VCLKA3R_EXTERNAL1 SYS_VCLKASRC_VCLKA3R(3) +# define SYS_VCLKASRC_VCLKA3R_LPOLOW SYS_VCLKASRC_VCLKA3R(4) +# define SYS_VCLKASRC_VCLKA3R_LPOHIGH SYS_VCLKASRC_VCLKA3R(5) +# define SYS_VCLKASRC_VCLKA3R_PLL2 SYS_VCLKASRC_VCLKA3R(6) +# define SYS_VCLKASRC_VCLKA3R_EXTERNAL2 SYS_VCLKASRC_VCLKA3R(7) +# define SYS_VCLKASRC_VCLKA3R_VCLK SYS_VCLKASRC_VCLKA3R(9) + +#define SYS_VCLKASRC_VCLKA3R_DIV_ENABLE (1 << 4) +#define SYS_VCLKASRC_VCLKA3R_DIV_DISABLE (0 << 4) + +#define SYS_VCLKASRC_VCLKA3R_DIV_SHIFT (8) +#define SYS_VCLKASRC_VCLKA3R_DIV_MASK (7 << SYS_VCLKASRC_VCLKA3R_SHIFT) +# define SYS_VCLKASRC_VCLKA3R_DIV(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA3R_SHIFT) +# define SYS_VCLKASRC_VCLKA3R_DIV1 SYS_VCLKASRC_VCLKA3R_DIV_MASK(0) +# define SYS_VCLKASRC_VCLKA3R_DIV2 SYS_VCLKASRC_VCLKA3R_DIV_MASK(1) +# define SYS_VCLKASRC_VCLKA3R_DIV3 SYS_VCLKASRC_VCLKA3R_DIV_MASK(2) +# define SYS_VCLKASRC_VCLKA3R_DIV4 SYS_VCLKASRC_VCLKA3R_DIV_MASK(3) +# define SYS_VCLKASRC_VCLKA3R_DIV5 SYS_VCLKASRC_VCLKA3R_DIV_MASK(4) +# define SYS_VCLKASRC_VCLKA3R_DIV6 SYS_VCLKASRC_VCLKA3R_DIV_MASK(5) +# define SYS_VCLKASRC_VCLKA3R_DIV7 SYS_VCLKASRC_VCLKA3R_DIV_MASK(6) +# define SYS_VCLKASRC_VCLKA3R_DIV8 SYS_VCLKASRC_VCLKA3R_DIV_MASK(7) + +#define SYS_VCLKASRC_VCLKA4S_SHIFT (16) +#define SYS_VCLKASRC_VCLKA4S_MASK (15 << SYS_VCLKASRC_VCLKA4S_SHIFT) +# define SYS_VCLKASRC_VCLKA4S(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA4S_SHIFT) +# define SYS_VCLKASRC_VCLKA4S_OSC SYS_VCLKASRC_VCLKA4S(0) +# define SYS_VCLKASRC_VCLKA4S_PLL1 SYS_VCLKASRC_VCLKA4S(1) +# define SYS_VCLKASRC_VCLKA4S_EXTERNAL1 SYS_VCLKASRC_VCLKA4S(3) +# define SYS_VCLKASRC_VCLKA4S_LPOLOW SYS_VCLKASRC_VCLKA4S(4) +# define SYS_VCLKASRC_VCLKA4S_LPOHIGH SYS_VCLKASRC_VCLKA4S(5) +# define SYS_VCLKASRC_VCLKA4S_PLL2 SYS_VCLKASRC_VCLKA4S(6) +# define SYS_VCLKASRC_VCLKA4S_EXTERNAL2 SYS_VCLKASRC_VCLKA4S(7) +# define SYS_VCLKASRC_VCLKA4S_VCLK SYS_VCLKASRC_VCLKA4S(9) + +#define SYS_VCLKASRC_VCLKA4S_DIV_ENABLE (1 << 20) +#define SYS_VCLKASRC_VCLKA4S_DIV_DISABLE (0 << 20) + +#define SYS_VCLKASRC_VCLKA4S_DIV_SHIFT (24) /* Bits 0-3: Peripheral asynchronous clock2 source */ +#define SYS_VCLKASRC_VCLKA4S_DIV_MASK (7 << SYS_VCLKASRC_VCLKA4S_DIV_SHIFT) +# define SYS_VCLKASRC_VCLKA4S_DIV(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA4S_DIV_SHIFT) +# define SYS_VCLKASRC_VCLKA4S_DIV1 SYS_VCLKASRC_VCLKA4S_DIV(0) +# define SYS_VCLKASRC_VCLKA4S_DIV2 SYS_VCLKASRC_VCLKA4S_DIV(1) +# define SYS_VCLKASRC_VCLKA4S_DIV3 SYS_VCLKASRC_VCLKA4S_DIV(2) +# define SYS_VCLKASRC_VCLKA4S_DIV4 SYS_VCLKASRC_VCLKA4S_DIV(3) +# define SYS_VCLKASRC_VCLKA4S_DIV5 SYS_VCLKASRC_VCLKA4S_DIV(4) +# define SYS_VCLKASRC_VCLKA4S_DIV6 SYS_VCLKASRC_VCLKA4S_DIV(5) +# define SYS_VCLKASRC_VCLKA4S_DIV7 SYS_VCLKASRC_VCLKA4S_DIV(6) +# define SYS_VCLKASRC_VCLKA4S_DIV8 SYS_VCLKASRC_VCLKA4S_DIV(7) + +#define SYS_CLK2CNTL_VCLK3R_SHIFT (0) /* Bits 16-19: VBUS clock ratio */ +#define SYS_CLKC2NTL_VCLK3R_MASK (15 << SYS_CLK2CNTL_VCLK3R_SHIFT) +# define SYS_CLK2CNTL_VCLK3R_DIV1 (0 << SYS_CLK2CNTL_VCLK3R_SHIFT) +# define SYS_CLK2CNTL_VCLK3R_DIV2 (1 << SYS_CLK2CNTL_VCLK3R_SHIFT) + +#endif + #endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS2_H */ diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index 40938bbc7a..3caeba643d 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tms570/tms570_clockconfig.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Some logic in this file was inspired/leveraged from TI's Project0 which @@ -50,7 +50,9 @@ #include "up_arch.h" +#include "chip/tms570_esm.h" #include "chip/tms570_sys.h" +#include "chip/tms570_sys2.h" #include "chip/tms570_pcr.h" #include "chip/tms570_flash.h" #include "chip/tms570_iomm.h" @@ -84,7 +86,7 @@ #if BOARD_VCLK2_DIVIDER == 1 # define SYS_CLKCNTL_VCLKR2 SYS_CLKCNTL_VCLKR2_DIV1 #elif BOARD_VCLK2_DIVIDER == 2 -# define SYS_CLKCNTL_VCLKR2 SYS_CLKCNTL_VCLKR_DIV2 +# define SYS_CLKCNTL_VCLKR2 SYS_CLKCNTL_VCLKR2_DIV2 #else # error Invalid value for SYS_CLKCNTL_VCLKR2_DIV2 #endif @@ -99,10 +101,10 @@ # define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV2 #elif BOARD_RTICLK_DIVIDER == 4 # define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV4 -#elif BOARD_RTICLK_DIVIDER == 78 +#elif BOARD_RTICLK_DIVIDER == 8 # define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV8 #else -# error Invalid value for SYS_CLKCNTL_VCLKR2_DIV2 +# error Invalid value for BOARD_RTICLK_DIVIDER #endif /**************************************************************************** @@ -120,6 +122,205 @@ static const struct tms570_pinmux_s g_pinmux_table[] = * Private Functions ****************************************************************************/ +#define ESM_SR1_PLL1SLIP 0x400 +#define ESM_SR4_PLL2SLIP 0x400 +#define dcc1CNT1_CLKSRC_PLL1 0x0000a000u +#define dcc1CNT1_CLKSRC_PLL2 0x0000a001u + +/**************************************************************************** + * Name: check_frequency + * + * Description: + * This function is used to verify is the Main Clock frequency correct + ****************************************************************************/ + +static uint32_t check_frequency(uint32_t cnt1_clksrc) +{ + uint32_t regval = 0; + + /* Setup DCC1 */ + /* DCC1 Global Control register configuration */ + + regval = (uint32_t)0x5u | /* Disable DCC1 */ + (uint32_t)((uint32_t)0x5u << 4u) | /* No Error Interrupt */ + (uint32_t)((uint32_t)0xau << 8u) | /* Single Shot mode */ + (uint32_t)((uint32_t)0x5u << 12u); /* No Done Interrupt */ + putreg32(regval,TMS570_DCC_BASE); + + /* Clear ERR and DONE bits */ + + regval = 3u; + putreg32(regval,TMS570_DCC_BASE + 0x14); + + /* DCC1 Clock0 Counter Seed value configuration */ + + regval = 68u; + putreg32(regval,TMS570_DCC_BASE + 0x08); + + /* DCC1 Clock0 Valid Counter Seed value configuration */ + + regval = 4u; + putreg32(regval,TMS570_DCC_BASE + 0x0c); + + /* DCC1 Clock1 Counter Seed value configuration */ + + regval = 972u; + putreg32(regval,TMS570_DCC_BASE + 0x10); + + /* DCC1 Clock1 Source 1 Select */ + + regval = (uint32_t)((uint32_t)10u << 12u) | /* DCC Enable / Disable Key */ + (uint32_t) cnt1_clksrc; /* DCC1 Clock Source 1 */ + putreg32(regval,TMS570_DCC_BASE + 0x24); + + regval = (uint32_t)15; /* DCC1 Clock Source 0 */ + putreg32(regval,TMS570_DCC_BASE + 0x28); + + /* DCC1 Global Control register configuration */ + + regval = (uint32_t)0xau | /* Enable DCC1 */ + (uint32_t)((uint32_t)0x5u << 4u) | /* No Error Interrupt */ + (uint32_t)((uint32_t)0xau << 8u) | /* Single Shot mode */ + (uint32_t)((uint32_t)0x5u << 12u); /* No Done Interrupt */ + + putreg32(regval,TMS570_DCC_BASE); + while(getreg32(TMS570_DCC_BASE + 0x14) == 0u) + { + /* Wait */ + } + + return (getreg32(TMS570_DCC_BASE + 0x14) & 0x01u); +} + +/**************************************************************************** + * Name: _errata_SSWF021_45_both_plls + * + * Description: + * This function is used to verify that PLL1 and PLL2 lock after + * system start-up. If PLL does not lock after system start-up + * and PLL slip occur then this function should be called at the + * beginning of tms570_clockconfig. (Errata sheet TMS570) + * + ****************************************************************************/ + +uint32_t _errata_SSWF021_45_both_plls( uint32_t count) +{ + uint32_t failcode; + uint32_t retries; + uint32_t clkcntrlsave; + uint32_t regval; + + /* Save CLKCNTL, */ + + clkcntrlsave = getreg32(TMS570_SYS_CLKCNTL); + + /* First set VCLK2 = HCLK */ + + regval = clkcntrlsave & 0x000f0100u; + putreg32(regval, TMS570_SYS_CLKCNTL); + + /* Now set VCLK = HCLK and enable peripherals */ + + regval = SYS_CLKCNTL_PENA; + putreg32(regval, TMS570_SYS_CLKCNTL); + + for(retries = 0u; (retries < count) || (count == 0u); retries++) + { + failcode = 0u; + + /* Disable PLL1 and PLL2 */ + + regval = 0x00000002u | 0x00000040u; + putreg32(regval, TMS570_SYS_CSDISSET); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != regval) + { + } + + /* Clear Global Status Register */ + + regval = 0x00000301u; + putreg32(regval,TMS570_SYS_GLBSTAT); + + /* Clear the ESM PLL slip flags */ + + putreg32(ESM_SR1_PLL1SLIP,TMS570_ESM_SR1); + putreg32(ESM_SR4_PLL2SLIP,TMS570_ESM_SR4); + + /* Set both PLLs to OSCIN/1*27/(2*1) */ + + regval = 0x20001a00u; + putreg32(regval,TMS570_SYS_PLLCTL1); + + regval = 0x3fc0723du; + putreg32(regval,TMS570_SYS_PLLCTL2); + + regval = 0x20001a00u; + putreg32(regval, 0xffffe100); + + regval = 0x00000002u | 0x00000040u; + putreg32(regval, TMS570_SYS_CSDISCLR); + + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + + while ((((getreg32(TMS570_SYS_CSVSTAT) & SYS_CLKSRC_PLL1) == 0u) && + ((getreg32(TMS570_ESM_SR1) & ESM_SR1_PLL1SLIP) == 0u)) || + (((getreg32(TMS570_SYS_CSVSTAT) & SYS_CLKSRC_PLL2) == 0u) && + ((getreg32(TMS570_ESM_SR4) & ESM_SR4_PLL2SLIP) == 0u))) + { + /* Wait */ + } + + /* If PLL1 valid, check the frequency */ + + if((getreg32(TMS570_ESM_SR1) & ESM_SR1_PLL1SLIP) != 0u) + { + failcode |= 1u; + } + else + { + failcode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + + /* If PLL2 valid, check the frequency */ + + if((getreg32(TMS570_ESM_SR4) & ESM_SR4_PLL2SLIP) != 0u) + { + failcode |= 2u; + } + else + { + failcode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + + if (failcode == 0u) + { + break; + } + } + + /* Disable plls */ + + regval = 0x00000002U | 0x00000040U; + putreg32(regval, TMS570_SYS_CSDISSET); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != regval) + { + } + + /* restore CLKCNTL, VCLKR and PENA first */ + + clkcntrlsave = getreg32(TMS570_SYS_CLKCNTL); + + /* First set VCLK2 = HCLK */ + + regval = clkcntrlsave & 0x000F0100U; + putreg32(regval, TMS570_SYS_CLKCNTL); + + putreg32(clkcntrlsave, TMS570_SYS_CLKCNTL); + return failcode; +} + /**************************************************************************** * Name: tms570_pll_setup * @@ -185,10 +386,48 @@ static void tms570_pll_setup(void) * NOTE: That R is temporary set to the maximum (32) here. */ + /* Turn off PLL1 and PLL2 */ + + regval = SYS_CSDIS_CLKSRC_PLL1 | SYS_CSDIS_CLKSRC_PLL2; + putreg32(regval, TMS570_SYS_CSDISSET); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != regval) + { + } + + /* Check for OSC failure */ + + regval = getreg32(TMS570_SYS_GLBSTAT); + if ((regval & SYS_GLBSTAT_OSC_ERR_MASK) == SYS_GLBSTAT_OSC_ERR_MASK) + { + regval = SYS_GHVSRC_GHVSRC_LPOHIGH | SYS_GHVSRC_HVLPM_LPOHIGH | + SYS_GHVSRC_GHVWAKE_LPOHIGH; + putreg32(regval, TMS570_SYS_GHVSRC); + + regval = SYS_CSDIS_CLKSRC_PLL1 | SYS_CSDIS_CLKSRC_PLL2 | + SYS_CSDIS_CLKSRC_OSC; + putreg32(regval, TMS570_SYS_CSDISSET); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != regval) + { + } + + putreg32(SYS_GLBSTAT_OSC_ERR_CLR,TMS570_SYS_GLBSTAT); + + regval = SYS_CSDIS_CLKSRC_OSC; + putreg32(regval, TMS570_SYS_CSDISCLR); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != regval) + { + } + } + + /* Setup pll control register 1 */ + regval = SYS_PLLCTL1_PLLMUL((BOARD_PLL_NF - 1) << 8) | SYS_PLLCTL1_REFCLKDIV(BOARD_PLL_NR - 1) | SYS_PLLCTL1_PLLDIV_MAX | - SYS_PLLCTL1_MASKSLIP_DISABLE; + (SYS_PLLCTL1_MASKSLIP_ENABLE); putreg32(regval, TMS570_SYS_PLLCTL1); /* Setup pll control register 2 */ @@ -206,8 +445,12 @@ static void tms570_pll_setup(void) * external clock remains disabled. */ - regval = SYS_CSDIS_CLKSRC_EXTCLKIN; - putreg32(regval, TMS570_SYS_CSDIS); + regval = SYS_CSDIS_CLKSRC_PLL1 | SYS_CSDIS_CLKSRC_PLL2; + putreg32(regval, TMS570_SYS_CSDISCLR); + + while((getreg32(TMS570_SYS_CSDIS) & regval) != 0) + { + } } /**************************************************************************** @@ -333,7 +576,7 @@ static void tms570_lpo_trim(void) /* The LPO trim value may be available in TI OTP */ - lotrim = (getreg32(TMS570_TITCM_LPOTRIM) & TMS570_TITCM_LPOTRIM_MASK) << + lotrim = (getreg32(TMS570_TITCM_LPOTRIM) & TMS570_TITCM_LPOTRIM_MASK) >> TMS570_TITCM_LPOTRIM_SHIFT; /* Use if the LPO trim value TI OTP if programmed. Otherwise, use a @@ -348,7 +591,7 @@ static void tms570_lpo_trim(void) { regval = SYS_LPOMONCTL_BIASENABLE | SYS_LPOMONCTL_HFTRIM_100p00 | - SYS_LPOMONCTL_60p86; + SYS_LPOMONCTL_100p00; } putreg32(regval, TMS570_SYS_LPOMONCTL); @@ -391,12 +634,13 @@ static void tms570_flash_setup(void) putreg32(FLASH_FSMWRENA_ENABLE, TMS570_FLASH_FSMWRENA); regval = FLASH_EEPROMCFG_GRACE(2) | FLASH_EEPROMCFG_EWAIT(BOARD_EWAIT); putreg32(regval, TMS570_FLASH_EEPROMCFG); - putreg32(FLASH_FSMWRENA_DISABLE, TMS570_FLASH_FSMWRENA); + //putreg32(FLASH_FSMWRENA_DISABLE, TMS570_FLASH_FSMWRENA); + putreg32(0x0a, TMS570_FLASH_FSMWRENA); /* Setup flash bank power modes */ regval = FLASH_FBFALLBACK_BANKPWR0_ACTIV | - FLASH_FBFALLBACK_BANKPWR1_SLEEP | + FLASH_FBFALLBACK_BANKPWR1_ACTIV | FLASH_FBFALLBACK_BANKPWR7_ACTIV; putreg32(regval, TMS570_FLASH_FBFALLBACK); } @@ -427,7 +671,7 @@ static void tms570_clocksrc_configure(void) * TCLK_EQEP Bit 9 On */ - putreg32(0, TMS570_SYS_CDDIS); + putreg32(0, TMS570_SYS_CDDISSET); /* Work Around for Errata SYS#46: Errata Description: Clock Source * Switching Not Qualified with Clock Source Enable And Clock Source Valid @@ -440,23 +684,17 @@ static void tms570_clocksrc_configure(void) { /* Get the set of valid clocks */ - csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_CSVSTAT_CLKSRVALL; + csvstat = getreg32(TMS570_SYS_CSVSTAT); /* Get the (inverted) state of each clock. Inverted so that '1' means * ON not OFF. */ csdis = (getreg32(TMS570_SYS_CSDIS) ^ SYS_CSDIS_CLKSROFFALL) & - SYS_CSDIS_CLKSROFFALL; + SYS_CSDIS_CLKSROFFALL; } while ((csvstat & csdis) != csdis); - - /* Now the PLLs are locked and the PLL outputs can be sped up. The R- - * divider was programmed to be 0xF. Now this divider is changed to - * programmed value - */ - regval = getreg32(TMS570_SYS_PLLCTL1); regval &= ~SYS_PLLCTL1_PLLDIV_MASK; regval |= SYS_PLLCTL1_PLLDIV(BOARD_PLL_R - 1); @@ -474,21 +712,48 @@ static void tms570_clocksrc_configure(void) SYS_GHVSRC_GHVWAKE_PLL1; putreg32(regval, TMS570_SYS_GHVSRC); + /* Setup RTICLK1 and RTICLK2 clocks */ + + regval = SYS_RCLKSRC_RTI1SRC_VCLK; + putreg32(regval, TMS570_SYS_RCLKSRC); + + /* Now the PLLs are locked and the PLL outputs can be sped up. The R- + * divider was programmed to be 0xF. Now this divider is changed to + * programmed value + */ + + /* Setup asynchronous peripheral clock sources for AVCLK1 */ + +#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) + regval = SYS_VCLKASRC_VCLKA2S_VCLK | SYS_VCLKASRC_VCLKA1S_VCLK; +#else + regval = SYS_VCLKASRC_VCLKA1S_VCLK; +#endif + putreg32(regval, TMS570_SYS_VCLKASRC); + +#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) + regval = SYS_VCLKASRC_VCLKA4S_VCLK |SYS_VCLKASRC_VCLKA3R_VCLK; + putreg32(regval, TMS570_SYS2_VCLKACON1); +#endif + /* Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ regval = getreg32(TMS570_SYS_CLKCNTL); - regval &= ~(SYS_CLKCNTL_VCLKR2_MASK | SYS_CLKCNTL_VCLKR_MASK); - regval |= SYS_CLKCNTL_VCLKR2 | SYS_CLKCNTL_VCLKR; + regval &= ~(SYS_CLKCNTL_VCLKR2_MASK); + regval |= SYS_CLKCNTL_VCLKR2; putreg32(regval, TMS570_SYS_CLKCNTL); - /* Setup RTICLK1 and RTICLK2 clocks */ + regval = getreg32(TMS570_SYS_CLKCNTL); + regval &= ~( SYS_CLKCNTL_VCLKR_MASK); + regval |= SYS_CLKCNTL_VCLKR; + putreg32(regval, TMS570_SYS_CLKCNTL); - regval = SYS_RCLKSRC_RTI1SRC_VCLK | SYS_RCLKSRC_RTI1DIV; - putreg32(regval, TMS570_SYS_RCLKSRC); - - /* Setup asynchronous peripheral clock sources for AVCLK1 */ - - putreg32(SYS_VCLKASRC_VCLKA1S_VCLK, TMS570_SYS_VCLKASRC); +#if defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT) + regval = getreg32(TMS570_SYS2_CLK2CNTRL); + regval &= ~(SYS_CLKC2NTL_VCLK3R_MASK); + regval |= SYS_CLK2CNTL_VCLK3R_DIV2; + putreg32(regval, TMS570_SYS2_CLK2CNTRL); +#endif } /**************************************************************************** @@ -555,7 +820,8 @@ void tms570_clockconfig(void) #ifdef CONFIG_TMS570_SELFTEST /* Run eFuse controller start-up checks and start eFuse controller ECC - * self-test.*/ + * self-test. + */ tms570_efc_selftest_start(); #endif /* CONFIG_TMS570_SELFTEST */ diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c index 33f2890b74..44d423b470 100644 --- a/arch/arm/src/tms570/tms570_irq.c +++ b/arch/arm/src/tms570/tms570_irq.c @@ -110,6 +110,10 @@ static void tms570_error_handler(void) * ****************************************************************************/ +#define TMS570_VIM_FIRQPR3 (TMS570_VIM_BASE+0x001c) +#define TMS570_VIM_REQENASET3 (TMS570_VIM_BASE+0x003c) +#define TMS570_VIM_REQENACLR3 (TMS570_VIM_BASE+0x004c) + void up_irqinitialize(void) { FAR uintptr_t *vimram; @@ -293,7 +297,6 @@ void up_disable_irq(int channel) /* Offset to account for the "phantom" vector */ - channel++; regndx = VIM_REGNDX(channel); channel = VIM_REGBIT(channel); bitmask = (1 << channel); @@ -302,7 +305,7 @@ void up_disable_irq(int channel) regaddr = TMS570_VIM_REQENACLR(regndx); regval = getreg32(regaddr); - regaddr |= bitmask; + regval |= bitmask; putreg32(regval, regaddr); } @@ -325,7 +328,6 @@ void up_enable_irq(int channel) /* Offset to account for the "phantom" vector */ - channel++; regndx = VIM_REGNDX(channel); channel = VIM_REGBIT(channel); bitmask = (1 << channel); @@ -335,7 +337,7 @@ void up_enable_irq(int channel) regaddr = TMS570_VIM_FIRQPR(regndx); regval = getreg32(regaddr); - regaddr &= ~bitmask; + regval &= ~bitmask; putreg32(regval, regaddr); #endif @@ -343,7 +345,7 @@ void up_enable_irq(int channel) regaddr = TMS570_VIM_REQENASET(regndx); regval = getreg32(regaddr); - regaddr |= bitmask; + regval |= bitmask; putreg32(regval, regaddr); } @@ -367,7 +369,6 @@ void up_enable_fiq(int channel) /* Offset to account for the "phantom" vector */ - channel++; regndx = VIM_REGNDX(channel); channel = VIM_REGBIT(channel); bitmask = (1 << channel); @@ -376,14 +377,14 @@ void up_enable_fiq(int channel) regaddr = TMS570_VIM_FIRQPR(regndx); regval = getreg32(regaddr); - regaddr &= ~bitmask; + regval &= ~bitmask; putreg32(regval, regaddr); /* Enable the FIQ by setting the corresponding REQENASET bit. */ regaddr = TMS570_VIM_REQENASET(regndx); regval = getreg32(regaddr); - regaddr |= bitmask; + regval |= bitmask; putreg32(regval, regaddr); } #endif diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index c5d21319e6..cba122a546 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tms570/tms570_lowputc.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Includes some logic from TI sample which has a compatibile three-clause @@ -55,6 +55,7 @@ #include "up_arch.h" #include "chip/tms570_sci.h" +#include "chip/tms570_iomm.h" #include "tms570_lowputc.h" /**************************************************************************** @@ -112,8 +113,31 @@ static const struct sci_config_s g_console_config = static void tms570_sci_initialize(uint32_t base) { +#if 0 + uint32_t reg; + + reg = 0x83e70b13u; + putreg32(reg,TMS570_IOMM_KICK0); + + reg = 0x95a4f1e0u; + putreg32(reg,TMS570_IOMM_KICK1); + + reg = (2 << 16); + putreg32(reg,TMS570_IOMM_PINMMR7); + + reg = (2 << 0); + putreg32(reg,TMS570_IOMM_PINMMR8); + + reg = 0; + putreg32(reg,TMS570_IOMM_KICK0); + + reg = 0; + putreg32(reg,TMS570_IOMM_KICK1); +#endif + /* Bring SCI1 out of reset */ + putreg32(0x0, base + TMS570_SCI_GCR0_OFFSET); putreg32(SCI_GCR0_RESET, base + TMS570_SCI_GCR0_OFFSET); /* Configure pins */ @@ -258,9 +282,9 @@ void tms570_lowsetup(void) int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config) { - uint64_t divb7; - uint64_t intpart; - uint64_t frac; + float32 divb7; + uint32_t intpart; + float32 frac; uint32_t p; uint32_t m; uint32_t u; @@ -274,26 +298,11 @@ int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config) * Asynchronous timing is assumed. */ - divb7 = ((uint64_t)BOARD_VCLK_FREQUENCY << 7) / (config->baud >> 4); + divb7 = BOARD_VCLK_FREQUENCY / (config->baud * 16) ; /* Break out the integer and fractional parts */ - intpart = divb7 >> 7; - if (intpart < 1) - { - /* Baud cannot be represented */ - - DEBUGPANIC(); - return -ERANGE; - } - - if (--intpart > 0x00ffffff) - { - /* Baud cannot be represented */ - - DEBUGPANIC(); - return -ERANGE; - } + intpart = (uint32_t)divb7; /* Disable all interrupts and map them all to INT0 */ @@ -338,14 +347,13 @@ int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config) gcr1 |= SCI_GCR1_STOP; } + gcr1 = 0; + gcr1 = (SCI_GCR1_TIMING | SCI_GCR1_CLOCK | SCI_GCR1_RXENA | SCI_GCR1_TXENA); putreg32(gcr1, base + TMS570_SCI_GCR1_OFFSET); - /* Set baud divisor using the pre-calculated values */ - - p = (uint32_t)intpart; - frac = (uint32_t)(divb7 & 0x3f); - m = frac >> 3; - u = frac & 3; + p = (uint32_t)intpart - 1; + m = (divb7 - intpart) * 16; + u = 0; regval = SCI_BRS_P(p) | SCI_BRS_M(m) | SCI_BRS_U(u); putreg32(regval, base + TMS570_SCI_BRS_OFFSET); diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index 8bb84ed91f..469074e494 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -860,7 +860,7 @@ void up_serialinit(void) tms570_disableallints(TTYS1_DEV.priv, NULL); #endif -#ifdef HAVE_SERIAL_CONSOLE +#ifdef CONSOLE_DEV /* Configure whichever one is the console. NOTE: This was already done * in tms570_lowsetup(). */ diff --git a/arch/arm/src/tms570/tms570_timerisr.c b/arch/arm/src/tms570/tms570_timerisr.c index 3dba2a1eae..e4c813c89f 100644 --- a/arch/arm/src/tms570/tms570_timerisr.c +++ b/arch/arm/src/tms570/tms570_timerisr.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tms570/tms570_timerisr.c * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -105,7 +105,7 @@ * - The following calculation performs rounding. */ -#define RTI_CPUC0 (((BOARD_RTICLK_FREQUENCY + RTI_FRC0CLK / 2) / RTI_FRC0CLK) - 1) +#define RTI_CPUC0 (((BOARD_RTICLK_FREQUENCY ) / RTI_FRC0CLK) - 1) /* CMP0 = CONFIG_USEC_PER_TICK * FRC0CLK / 1,000,000 * @@ -115,7 +115,7 @@ * FRCLK being a multiple of 100,000 */ -#define RTI_CMP0 ((CONFIG_USEC_PER_TICK * (RTI_FRC0CLK / 100000) + 50) / 100) +#define RTI_CMP0 ((CONFIG_USEC_PER_TICK * (RTI_FRC0CLK / 100000) + 50) / 10) /**************************************************************************** * Private Functions @@ -132,7 +132,7 @@ static int tms570_timerisr(int irq, uint32_t *regs, void *arg) { - /* Cleear the RTI Compare 0 interrupts */ + /* Clear the RTI Compare 0 interrupts */ putreg32(RTI_INT0, TMS570_RTI_INTFLAG); @@ -160,6 +160,7 @@ void arm_timer_initialize(void) /* Disable all RTI interrupts */ up_disable_irq(TMS570_REQ_RTICMP0); + putreg32(0x0, TMS570_RTI_GCTRL); putreg32(RTI_ALLINTS, TMS570_RTI_CLEARINTENA); /* Configure RTICOMP0 register and the RTIUDCP0 Register to initialize with @@ -173,7 +174,7 @@ void arm_timer_initialize(void) * calculated value. */ - putreg32(RTI_CMP0, TMS570_RTI_CPUC0); + putreg32(RTI_CPUC0, TMS570_RTI_CPUC0); /* Initialize the free-running counter and the RTI up-counter */ @@ -182,7 +183,7 @@ void arm_timer_initialize(void) /* Clear any pending interrupts */ - putreg32(RTI_ALLINTS, TMS570_RTI_COMP0); + putreg32(RTI_ALLINTS, TMS570_RTI_INTFLAG); /* Enable the RTI Compare 0 interrupts (still disabled at the VIM) */ @@ -194,7 +195,7 @@ void arm_timer_initialize(void) /* Attach the interrupt handler to the RTI Compare 0 interrupt */ - DEBUGVERIFY(irq_attach(TMS570_REQ_RTICMP0, (xcpt_t)tms570_timerisr), NULL); + DEBUGVERIFY(irq_attach(TMS570_REQ_RTICMP0, (xcpt_t)tms570_timerisr, NULL)); /* Enable RTI compare 0 interrupts at the VIM */