From 1f021add532d27ae833b746a8c86bfe287b071d6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Aug 2019 08:20:31 -0600 Subject: [PATCH] arm/arm/src/stm32f7 and h7: Fix coding standard problems found by tools/nxstyle in files modified/added in last PR. --- arch/arm/src/stm32f7/stm32_rtc.c | 33 ++-- arch/arm/src/stm32h7/hardware/stm32_rtcc.h | 1 - .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 7 +- arch/arm/src/stm32h7/stm32_rtc.c | 33 ++-- arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c | 7 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 165 +++++++++--------- .../stm32h7/nucleo-h743zi/src/nucleo-h743zi.h | 1 + 7 files changed, 128 insertions(+), 119 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index 12aa23f1c0..c7d8219a78 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -63,7 +63,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* This RTC implementation supports * - date/time RTC hardware * - extended functions Alarm A and B @@ -200,7 +202,7 @@ static void rtc_dumpregs(FAR const char *msg) ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) | ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) | ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0); - rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state); + rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n", rtc_state); } #else # define rtc_dumpregs(msg) @@ -256,7 +258,7 @@ static void rtc_wprunlock(void) /* The following steps are required to unlock the write protection on all * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). * - * 1. Write 0xCA into the RTC_WPR register. + * 1. Write 0xca into the RTC_WPR register. * 2. Write 0x53 into the RTC_WPR register. * * Writing a wrong key re-activates the write protection. @@ -845,7 +847,8 @@ rtchw_set_alrmbr_exit: #ifdef CONFIG_RTC_ALARM static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, FAR struct tm *tp) { - uint32_t data, tmp; + uint32_t data; + uint32_t tmp; DEBUGASSERT(tp != NULL); @@ -908,6 +911,7 @@ int up_rtc_initialize(void) */ /* Select the clock source */ + /* Save the token before losing it when resetting */ regval = getreg32(RTC_MAGIC_REG); @@ -1257,14 +1261,15 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: This interface exposes sub-second accuracy capability of RTC hardware. - * This interface allow maintaining timing accuracy when system time needs constant - * resynchronization with RTC, for example with board level power-save mode utilizing - * deep-sleep modes such as STOP on STM32 MCUs. + * NOTE: This interface exposes sub-second accuracy capability of RTC + * hardware. This interface allow maintaining timing accuracy when + * system time needs constant resynchronization with RTC, for example with + * board level power-save mode utilizing deep-sleep modes such as STOP on + * STM32 MCUs. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -1788,7 +1793,7 @@ int stm32_rtc_setperiodic(FAR const struct timespec *period, #elif defined(CONFIG_STM32F7_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32F7_RTC_LSECLOCK) - const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffU / STM32_LSE_FREQUENCY; + const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1799,12 +1804,12 @@ int stm32_rtc_setperiodic(FAR const struct timespec *period, * We currently go for subseconds accuracy instead of maximum period. */ - if (period->tv_sec > 0xffffU || - (period->tv_sec == 0xffffU && period->tv_nsec > 0)) + if (period->tv_sec > 0xffffu || + (period->tv_sec == 0xffffu && period->tv_nsec > 0)) { /* More than max. */ - secs = 0xffffU; + secs = 0xffffu; millisecs = secs * 1000; } else diff --git a/arch/arm/src/stm32h7/hardware/stm32_rtcc.h b/arch/arm/src/stm32h7/hardware/stm32_rtcc.h index 9e4f0f0d16..6d7a4cf7a5 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rtcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rtcc.h @@ -396,5 +396,4 @@ #define RTC_OR_RTC_ALARM_TYPE (1 << 0) /* Bit 0: RTC_ALARM output type on PC13 */ #define RTC_OR_RTC_OUT_RMP (1 << 1) /* Bit 1: RTC_OUT remap */ - #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 6fea50fce9..4ead8f3b66 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -50,7 +50,7 @@ /* Register Offsets *********************************************************************************/ -// TODO: Complete comments +/* TODO: Complete comments */ #define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ #define STM32_RCC_ICSCR_OFFSET 0x0004 /* */ @@ -494,7 +494,6 @@ #define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) /* 0x0000FFF8 */ #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK - /* Bit definitions for RCC_D1CCIPR reigster */ #define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ @@ -1001,7 +1000,6 @@ #define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ #define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ - /* AHB2 low power mode peripheral clock enable register */ #define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ @@ -1013,7 +1011,7 @@ #define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ #define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ -/* AHB4 low power mode peripheral clock enable register*/ +/* AHB4 low power mode peripheral clock enable register */ #define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ #define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ @@ -1064,7 +1062,6 @@ #define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ #define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ - /* APB1 H low power mode peripheral clock enable register */ #define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index 0c356c4ca4..15f4e79ef3 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -63,7 +63,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* This RTC implementation supports * - date/time RTC hardware * - extended functions Alarm A and B @@ -200,7 +202,7 @@ static void rtc_dumpregs(FAR const char *msg) ((getreg32(STM32_EXTI_FTSR1) & EXTI_RTC_ALARM) ? 0x0100 : 0) | ((getreg32(STM32_EXTI_CPUIMR1) & EXTI_RTC_ALARM) ? 0x0010 : 0) | ((getreg32(STM32_EXTI_CPUEMR1) & EXTI_RTC_ALARM) ? 0x0001 : 0); - rtcinfo("EXTI (RTSR1 FTSR1 ISR EVT): %01x\n",rtc_state); + rtcinfo("EXTI (RTSR1 FTSR1 ISR EVT): %01x\n", rtc_state); } #else # define rtc_dumpregs(msg) @@ -256,7 +258,7 @@ static void rtc_wprunlock(void) /* The following steps are required to unlock the write protection on all * the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). * - * 1. Write 0xCA into the RTC_WPR register. + * 1. Write 0xca into the RTC_WPR register. * 2. Write 0x53 into the RTC_WPR register. * * Writing a wrong key re-activates the write protection. @@ -845,7 +847,8 @@ rtchw_set_alrmbr_exit: #ifdef CONFIG_RTC_ALARM static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, FAR struct tm *tp) { - uint32_t data, tmp; + uint32_t data; + uint32_t tmp; DEBUGASSERT(tp != NULL); @@ -908,6 +911,7 @@ int up_rtc_initialize(void) */ /* Select the clock source */ + /* Save the token before losing it when resetting */ regval = getreg32(RTC_MAGIC_REG); @@ -1257,14 +1261,15 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: This interface exposes sub-second accuracy capability of RTC hardware. - * This interface allow maintaining timing accuracy when system time needs constant - * resynchronization with RTC, for example with board level power-save mode utilizing - * deep-sleep modes such as STOP on STM32 MCUs. + * NOTE: This interface exposes sub-second accuracy capability of RTC + * hardware. This interface allow maintaining timing accuracy when system + * time needs constant resynchronization with RTC, for example with board + * level power-save mode utilizing deep-sleep modes such as STOP on STM32 + * MCUs. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -1788,7 +1793,7 @@ int stm32_rtc_setperiodic(FAR const struct timespec *period, #elif defined(CONFIG_STM32H7_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32H7_RTC_LSECLOCK) - const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffU / STM32_LSE_FREQUENCY; + const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1799,12 +1804,12 @@ int stm32_rtc_setperiodic(FAR const struct timespec *period, * We currently go for subseconds accuracy instead of maximum period. */ - if (period->tv_sec > 0xffffU || - (period->tv_sec == 0xffffU && period->tv_nsec > 0)) + if (period->tv_sec > 0xffffu || + (period->tv_sec == 0xffffu && period->tv_nsec > 0)) { /* More than max. */ - secs = 0xffffU; + secs = 0xffffu; millisecs = secs * 1000; } else diff --git a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c index 90001d8fcf..f41c342fab 100644 --- a/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c @@ -137,6 +137,7 @@ static int stm32_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id); /**************************************************************************** * Private Data ****************************************************************************/ + /* STM32 RTC driver operations */ static const struct rtc_ops_s g_rtc_ops = @@ -248,9 +249,9 @@ static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower, ret = nxsem_wait(&priv->devsem); if (ret < 0) - { - return ret; - } + { + return ret; + } #if defined(CONFIG_RTC_DATETIME) /* This operation depends on the fact that struct rtc_time is cast diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 5857299fd4..528ff6531f 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -733,28 +733,28 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) - { - /* Do not use this in STM32_SDMMC_MASK register */ + { + /* Do not use this in STM32_SDMMC_MASK register */ - waitmask &= !SDIOWAIT_WRCOMPLETE; + waitmask &= !SDIOWAIT_WRCOMPLETE; - pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); + pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); - /* Arm the SDMMC_D Ready and install Isr */ + /* Arm the SDMMC_D Ready and install Isr */ - (void)stm32_gpiosetevent(pinset, true, false, false, - stm32_sdmmc_rdyinterrupt, priv); - } + (void)stm32_gpiosetevent(pinset, true, false, false, + stm32_sdmmc_rdyinterrupt, priv); + } /* Disarm SDMMC_D ready */ if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) - { - (void)stm32_gpiosetevent(priv->d0_gpio, false, false, false, - NULL, NULL); - stm32_configgpio(priv->d0_gpio); - } + { + (void)stm32_gpiosetevent(priv->d0_gpio, false, false, false, + NULL, NULL); + stm32_configgpio(priv->d0_gpio); + } #endif priv->waitevents = waitevents; @@ -943,10 +943,10 @@ static uint8_t stm32_log2(uint16_t value) DEBUGASSERT(value > 0); while (value != 1) - { - value >>= 1; - log2++; - } + { + value >>= 1; + log2++; + } return log2; } @@ -1040,40 +1040,40 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) while (priv->remaining > 0 && (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_TXFIFOF) == 0) - { - /* Is there a full word remaining in the user buffer? */ - - if (priv->remaining >= sizeof(uint32_t)) { - /* Yes, transfer the word to the TX FIFO */ + /* Is there a full word remaining in the user buffer? */ - data.w = *priv->buffer++; - priv->remaining -= sizeof(uint32_t); + if (priv->remaining >= sizeof(uint32_t)) + { + /* Yes, transfer the word to the TX FIFO */ + + data.w = *priv->buffer++; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* No.. transfer just the bytes remaining in the user buffer, + * padding with zero as necessary to extend to a full word. + */ + + uint8_t *ptr = (uint8_t *)priv->remaining; + int i; + + data.w = 0; + for (i = 0; i < (int)priv->remaining; i++) + { + data.b[i] = *ptr++; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + + /* Put the word in the FIFO */ + + sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); } - else - { - /* No.. transfer just the bytes remaining in the user buffer, - * padding with zero as necessary to extend to a full word. - */ - - uint8_t *ptr = (uint8_t *)priv->remaining; - int i; - - data.w = 0; - for (i = 0; i < (int)priv->remaining; i++) - { - data.b[i] = *ptr++; - } - - /* Now the transfer is finished */ - - priv->remaining = 0; - } - - /* Put the word in the FIFO */ - - sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); - } } /**************************************************************************** @@ -1105,34 +1105,34 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) while (priv->remaining > 0 && (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_RXFIFOE) == 0) - { - /* Read the next word from the RX FIFO */ - - data.w = sdmmc_getreg32(priv, STM32_SDMMC_FIFO_OFFSET); - if (priv->remaining >= sizeof(uint32_t)) { - /* Transfer the whole word to the user buffer */ + /* Read the next word from the RX FIFO */ - *priv->buffer++ = data.w; - priv->remaining -= sizeof(uint32_t); + data.w = sdmmc_getreg32(priv, STM32_SDMMC_FIFO_OFFSET); + if (priv->remaining >= sizeof(uint32_t)) + { + /* Transfer the whole word to the user buffer */ + + *priv->buffer++ = data.w; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* Transfer any trailing fractional word */ + + uint8_t *ptr = (uint8_t *)priv->buffer; + int i; + + for (i = 0; i < (int)priv->remaining; i++) + { + *ptr++ = data.b[i]; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } } - else - { - /* Transfer any trailing fractional word */ - - uint8_t *ptr = (uint8_t *)priv->buffer; - int i; - - for (i = 0; i < (int)priv->remaining; i++) - { - *ptr++ = data.b[i]; - } - - /* Now the transfer is finished */ - - priv->remaining = 0; - } - } } #endif @@ -1172,12 +1172,12 @@ static void stm32_eventtimeout(int argc, uint32_t arg) /* Is a data transfer complete event expected? */ if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) - { - /* Yes.. wake up any waiting threads */ + { + /* Yes.. wake up any waiting threads */ - stm32_endwait(priv, SDIOWAIT_TIMEOUT); - mcerr("Timeout: remaining: %d\n", priv->remaining); - } + stm32_endwait(priv, SDIOWAIT_TIMEOUT); + mcerr("Timeout: remaining: %d\n", priv->remaining); + } } /**************************************************************************** @@ -1479,10 +1479,10 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Yes.. Is their a thread waiting for response done? */ if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) - { - /* Yes.. wake the thread up */ + { + /* Yes.. wake the thread up */ - stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); + stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); } } @@ -2875,6 +2875,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) } /* Initialize the SDIO slot structure */ + /* Initialize semaphores */ nxsem_init(&priv->waitsem, 0, 0); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index a250b037ef..493cfd18b6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -62,6 +62,7 @@ #define HAVE_RTC_DRIVER 1 /* Configuration ********************************************************************/ + /* LED * * The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a