Fix Z16F context structure
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@556 42af7a65-404d-4744-a932-0658087f49c3
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@ -69,7 +69,7 @@ typedef unsigned int uint32;
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* irqsave()
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* irqsave()
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*/
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*/
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typedef unsigned int irqstate_t;
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typedef unsigned short irqstate_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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@ -98,19 +98,31 @@
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* in the TCB to many context switches.
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* in the TCB to many context switches.
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*/
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*/
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#define XCPT_I (0) /* Offset 0: Saved I w/interrupt state in carry */
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#define REG_R0 ( 0) /* 32-bits: R0 */
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#define XCPT_BC (1) /* Offset 1: Saved BC register */
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#define REG_R1 ( 2) /* 32-bits: R0 */
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#define XCPT_DE (2) /* Offset 2: Saved DE register */
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#define REG_R2 ( 4) /* 32-bits: R0 */
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#define XCPT_IX (3) /* Offset 3: Saved IX register */
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#define REG_R3 ( 6) /* 32-bits: R0 */
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#define XCPT_IY (4) /* Offset 4: Saved IY register */
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#define REG_R4 ( 8) /* 32-bits: R0 */
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#define XCPT_SP (5) /* Offset 5: Offset to SP at time of interrupt */
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#define REG_R5 (10) /* 32-bits: R0 */
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#define XCPT_HL (6) /* Offset 6: Saved HL register */
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#define REG_R6 (12) /* 32-bits: R0 */
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#define XCPT_AF (7) /* Offset 7: Saved AF register */
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#define REG_R7 (14) /* 32-bits: R0 */
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#define XCPT_PC (8) /* Offset 8: Offset to PC at time of interrupt */
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#define REG_R8 (16) /* 32-bits: R0 */
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#define REG_R9 (18) /* 32-bits: R0 */
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#define REG_R10 (20) /* 32-bits: R0 */
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#define REG_R11 (22) /* 32-bits: R0 */
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#define REG_R12 (24) /* 32-bits: R0 */
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#define REG_R13 (26) /* 32-bits: R0 */
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#define REG_R14 (28) /* 32-bits: R0 */
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#define REG_R15 (30) /* 32-bits: R0 */
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#define REG_PC (32) /* 32-bits: Return PC */
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#define REG_FLAGS (34) /* 16-bits: Flags register (with 0x00 padding)
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#define XCPTCONTEXT_REGS (9)
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#define XCPTCONTEXT_REGS (35)
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#define XCPTCONTEXT_SIZE (2 * XCPTCONTEXT_REGS)
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#define XCPTCONTEXT_SIZE (2 * XCPTCONTEXT_REGS)
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#define REG_FP REG_R14
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#define REG_SP REG_R15
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/****************************************************************************
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/****************************************************************************
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* Public Types
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* Public Types
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****************************************************************************/
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****************************************************************************/
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@ -138,12 +150,24 @@ struct xcptcontext
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/* The following retains that state during signal execution */
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/* The following retains that state during signal execution */
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uint16 saved_pc; /* Saved return address */
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uint32 saved_pc; /* Saved return address */
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uint16 saved_i; /* Saved interrupt state */
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uint16 saved_i; /* Saved interrupt state */
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#endif
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#endif
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};
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};
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#endif
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#endif
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/* The ZDS-II provides built-in operations to test & disable and to restore
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* the interrupt state.
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*
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* irqstate_t irqsave(void);
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* void irqrestore(irqstate_t flags);
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*/
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#ifdef __ZILOG__
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# define irqsave() TDI()
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# define irqrestore(f) RI(f)
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#endif
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/****************************************************************************
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/****************************************************************************
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* Inline functions
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* Inline functions
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****************************************************************************/
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****************************************************************************/
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@ -164,8 +188,10 @@ extern "C" {
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#define EXTERN extern
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#define EXTERN extern
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#endif
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#endif
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#ifndef __ZILOG__
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EXTERN irqstate_t irqsave(void);
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EXTERN irqstate_t irqsave(void);
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EXTERN void irqrestore(irqstate_t flags);
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EXTERN void irqrestore(irqstate_t flags);
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#endif
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#undef EXTERN
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#undef EXTERN
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -81,7 +81,7 @@ $(AOBJS) $(HEAD_AOBJ): %$(OBJEXT): %$(ASMEXT)
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$(call ASSEMBLE, $<, $@)
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$(call ASSEMBLE, $<, $@)
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else
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else
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$(OBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S
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$(OBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S
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$(call ASSEMBLE, $<, $@)endif
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$(call ASSEMBLE, $<, $@)
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endif
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endif
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$(COBJS): %$(OBJEXT): %.c
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$(COBJS): %$(OBJEXT): %.c
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@ -78,14 +78,14 @@
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void up_initial_state(_TCB *tcb)
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void up_initial_state(_TCB *tcb)
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{
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{
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struct xcptcontext *xcp = &tcb->xcp;
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uint32 *reg32 = (uint32*)tcb->xcp.regs;
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/* Initialize the initial exception register context structure */
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/* Initialize the initial exception register context structure */
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memset(xcp, 0, sizeof(struct xcptcontext));
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memset(&tcb->xcp, 0, sizeof(struct xcptcontext));
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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xcp->regs[XCPT_I] = Z80_C_FLAG; /* Carry flag will enable interrupts */
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xcp->regs[REG_FLAGS] = Z16F_CNTRL_FLAGS_IRQE << 8; /* IRQE flag will enable interrupts */
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#endif
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#endif
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xcp->regs[XCPT_SP] = (chipreg_t)tcb->adj_stack_ptr;
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reg32[REG_SP/2] = (uint32)tcb->adj_stack_ptr;
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xcp->regs[XCPT_PC] = (chipreg_t)tcb->start;
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reg32[REG_PC/2] = (uint32)tcb->start;
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}
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}
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@ -76,16 +76,15 @@
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#ifdef CONFIG_ARCH_STACKDUMP
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#ifdef CONFIG_ARCH_STACKDUMP
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static void up_registerdump(void)
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static void up_registerdump(void)
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{
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{
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if (current_regs)
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uint32 *regs32 = (uint32*)current_regs;
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{
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lldbg("R0 :%08x R1 :%08x R2 :%08x R3 :%08x "
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lldbg("AF: %04x I: %04x\n",
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"R4 :%08x R5 :%08x R6 :%08x R7 :%08x\n"
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current_regs[XCPT_AF], current_regs[XCPT_I]);
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regs32[REG_R0/2], regs32[REG_R1/2], regs32[REG_R2/2], regs32[REG_R3/2],
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lldbg("BC: %04x DE: %04x HL: %04x\n",
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regs32[REG_R4/2], regs32[REG_R5/2], regs32[REG_R6/2], regs32[REG_R7/2]);
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current_regs[XCPT_BC], current_regs[XCPT_DE], current_regs[XCPT_HL]);
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lldbg("R8 :%08x R9 :%08x R10:%08x R11:%08x R12:%08x R13:%08x\n"
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lldbg("IX: %04x IY: %04x\n",
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regs32[REG_R8/2], regs32[REG_R9/2], regs32[REG_R10/2], regs3[REG_R11/2],
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current_regs[XCPT_IX], current_regs[XCPT_IY]);
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regs32[REG_R12/2], regs32[REG_R13/2]);
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lldbg("SP: %04x PC: $04x\n"
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lldbg("FP :%08x SP :%08x FLG:%04x\n"
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current_regs[XCPT_SP], current_regs[XCPT_PC]);
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regs32[REG_R14/2], regs32[REG_R15/2], current_regs[REG_FLAGS]);
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}
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}
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}
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#endif
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#endif
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@ -141,21 +141,23 @@ void up_schedule_sigaction(FAR _TCB *tcb, sig_deliver_t sigdeliver)
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else
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else
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{
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{
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uint32 *current_pc = (uint32*)¤t_regs[REG_PC];
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/* Save the return address and interrupt state.
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/* Save the return address and interrupt state.
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* These will be restored by the signal trampoline after
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* These will be restored by the signal trampoline after
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* the signals have been delivered.
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* the signals have been delivered.
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*/
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*/
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.saved_pc = current_regs[XCPT_PC];
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tcb->xcp.saved_pc = *current_pc;
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tcb->xcp.saved_i = current_regs[XCPT_I];
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tcb->xcp.saved_i = current_regs[REG_FLAGS];
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/* Then set up to vector to the trampoline with interrupts
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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* disabled
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*/
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*/
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current_regs[XCPT_PC] = (chipreg_t)up_sigdeliver;
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*current_pc = (uint32)up_sigdeliver;
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current_regs[XCPT_I] = 0;
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current_regs[REG_FLAGS] = 0;
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/* And make sure that the saved context in the TCB
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/* And make sure that the saved context in the TCB
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* is the same as the interrupt return context.
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* is the same as the interrupt return context.
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@ -173,21 +175,23 @@ void up_schedule_sigaction(FAR _TCB *tcb, sig_deliver_t sigdeliver)
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else
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else
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{
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{
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uint32 *saved_pc = (uint32*)&tcb->xcp.regs[REG_PC];
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/* Save the return lr and cpsr and one scratch register
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/* Save the return lr and cpsr and one scratch register
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* These will be restored by the signal trampoline after
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* These will be restored by the signal trampoline after
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* the signals have been delivered.
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* the signals have been delivered.
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*/
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*/
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.sigdeliver = sigdeliver;
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tcb->xcp.saved_pc = tcb->xcp.regs[XCPT_PC];
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tcb->xcp.saved_pc = *saved_pc;
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tcb->xcp.saved_i = tcb->xcp.regs[XCPT_I];
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tcb->xcp.saved_i = tcb->xcp.regs[REG_FLAGS];
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/* Then set up to vector to the trampoline with interrupts
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/* Then set up to vector to the trampoline with interrupts
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* disabled
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* disabled
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*/
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*/
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tcb->xcp.regs[XCPT_PC] = (chipreg_t)up_sigdeliver;
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*saved_pc = (uint32)up_sigdeliver;
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tcb->xcp.regs[XCPT_I] = 0;
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tcb->xcp.regs[REG_FLAGS] = 0;
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}
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}
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irqrestore(flags);
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irqrestore(flags);
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@ -83,6 +83,7 @@ void up_sigdeliver(void)
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#ifndef CONFIG_DISABLE_SIGNALS
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#ifndef CONFIG_DISABLE_SIGNALS
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_TCB *rtcb = (_TCB*)g_readytorun.head;
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_TCB *rtcb = (_TCB*)g_readytorun.head;
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chipreg_t regs[XCPTCONTEXT_REGS];
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chipreg_t regs[XCPTCONTEXT_REGS];
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uint32 *regs32 = (uint32*)regs;
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sig_deliver_t sigdeliver;
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sig_deliver_t sigdeliver;
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/* Save the errno. This must be preserved throughout the signal handling
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/* Save the errno. This must be preserved throughout the signal handling
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@ -101,8 +102,8 @@ void up_sigdeliver(void)
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/* Save the real return state on the stack. */
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/* Save the real return state on the stack. */
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up_copystate(regs, rtcb->xcp.regs);
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up_copystate(regs, rtcb->xcp.regs);
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regs[XCPT_PC] = rtcb->xcp.saved_pc;
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regs32[REG_PC/2] = rtcb->xcp.saved_pc;
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regs[XCPT_I] = rtcb->xcp.saved_i;
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regs[REG_FLAGS] = rtcb->xcp.saved_i;
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/* Get a local copy of the sigdeliver function pointer.
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/* Get a local copy of the sigdeliver function pointer.
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* we do this so that we can nullify the sigdeliver
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* we do this so that we can nullify the sigdeliver
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@ -116,7 +117,10 @@ void up_sigdeliver(void)
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/* Then restore the task interrupt state. */
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/* Then restore the task interrupt state. */
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irqrestore(regs[XCPT_I]);
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if ((reg[REG_FLAGS] & (Z16F_CNTRL_FLAGS_IRQE << 8)) != 0)
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{
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EI();
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}
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/* Deliver the signals */
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/* Deliver the signals */
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@ -125,12 +125,12 @@ EXEEXT = .hex
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# object files into an archive
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# object files into an archive
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define COMPILE
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define COMPILE
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@echo "CC: $1"
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@#echo "CC: $1"
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@$(CC) $(CFLAGS) $1 1>/dev/null
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@$(CC) $(CFLAGS) $1
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endef
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endef
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define ASSEMBLE
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define ASSEMBLE
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@echo "AS: $1"
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@#echo "AS: $1"
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@$(AS) -c $(AFLAGS) $1
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@$(AS) -c $(AFLAGS) $1
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endef
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endef
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@ -52,11 +52,16 @@ OBJS = $(AOBJS) $(COBJS)
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all: libboard$(LIBEXT)
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all: libboard$(LIBEXT)
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$(AOBJS): %$(OBJEXT): %.S
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$(ASRCS) $(HEAD_ASRC): %$(ASMEXT): %.S
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@$(CPP) $(CPPFLAGS) $< -o $@.tmp
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@cat $@.tmp | sed -e "s/^#/;/g" > $@
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@rm $@.tmp
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$(AOBJS): %$(OBJEXT): %$(ASMEXT)
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$(call ASSEMBLE, $<, $@)
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$(call ASSEMBLE, $<, $@)
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$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
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$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
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$(call COMPILE, $<, $@)
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$(call COMPILE, `cygpath -w $<`, $@)
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libboard$(LIBEXT): $(OBJS)
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libboard$(LIBEXT): $(OBJS)
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@( for obj in $(OBJS) ; do \
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@( for obj in $(OBJS) ; do \
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