Update some README files
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@ -2564,11 +2564,6 @@ Tickless OS
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piece has a large error in the calculation. The cumulative error is the
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cause of the problem.
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Solution: 30.518 microseconds is not representable and the value of
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CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
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long delays (short delays are probably still okay). We should driver
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the interval timer with PCK6 with a period that is exactly representable.
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SAMA5 Timer Usage
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-----------------
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This current implementation uses two timers: A one-shot timer to
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@ -2884,11 +2884,6 @@ Tickless OS
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piece has a large error in the calculation. The cumulative error is the
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cause of the problem.
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Solution: 30.518 microseconds is not representable and the value of
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CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
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long delays (short delays are probably still okay). We should driver
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the interval timer with PCK6 with a period that is exactly representable.
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SAMA5 Timer Usage
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-----------------
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This current implementation uses two timers: A one-shot timer to
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@ -3392,11 +3392,6 @@ Tickless OS
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piece has a large error in the calculation. The cumulative error is the
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cause of the problem.
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Solution: 30.518 microseconds is not representable and the value of
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CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
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long delays (short delays are probably still okay). We should driver
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the interval timer with PCK6 with a period that is exactly representable.
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SAMA5 Timer Usage
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-----------------
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This current implementation uses two timers: A one-shot timer to
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@ -141,7 +141,7 @@
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#define BOARD_PLLA_FREQUENCY (300000000) /* PLLACK: 25 * 12Mhz / 1 */
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#define BOARD_CPU_FREQUENCY (300000000) /* CPU: PLLACK / 1 */
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#define BOARD_MCK_FREQUENCY (150000000) /* MCK: PLLACK / 1 / 2 */
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#define BOARD_UPLL_FREQUENCY /* To be provided */
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#undef BOARD_UPLL_FREQUENCY /* To be provided */
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/* HSMCI clocking
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*
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