Update some README files

This commit is contained in:
Gregory Nutt 2015-12-03 15:36:23 -06:00
parent 734144ad66
commit 1f17ba860a
4 changed files with 1 additions and 16 deletions

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@ -2564,11 +2564,6 @@ Tickless OS
piece has a large error in the calculation. The cumulative error is the
cause of the problem.
Solution: 30.518 microseconds is not representable and the value of
CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
long delays (short delays are probably still okay). We should driver
the interval timer with PCK6 with a period that is exactly representable.
SAMA5 Timer Usage
-----------------
This current implementation uses two timers: A one-shot timer to

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@ -2884,11 +2884,6 @@ Tickless OS
piece has a large error in the calculation. The cumulative error is the
cause of the problem.
Solution: 30.518 microseconds is not representable and the value of
CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
long delays (short delays are probably still okay). We should driver
the interval timer with PCK6 with a period that is exactly representable.
SAMA5 Timer Usage
-----------------
This current implementation uses two timers: A one-shot timer to

View File

@ -3392,11 +3392,6 @@ Tickless OS
piece has a large error in the calculation. The cumulative error is the
cause of the problem.
Solution: 30.518 microseconds is not representable and the value of
CONFIG_USEC_PER_SEC is too inaccurate; error build-up is throwing off
long delays (short delays are probably still okay). We should driver
the interval timer with PCK6 with a period that is exactly representable.
SAMA5 Timer Usage
-----------------
This current implementation uses two timers: A one-shot timer to

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@ -141,7 +141,7 @@
#define BOARD_PLLA_FREQUENCY (300000000) /* PLLACK: 25 * 12Mhz / 1 */
#define BOARD_CPU_FREQUENCY (300000000) /* CPU: PLLACK / 1 */
#define BOARD_MCK_FREQUENCY (150000000) /* MCK: PLLACK / 1 / 2 */
#define BOARD_UPLL_FREQUENCY /* To be provided */
#undef BOARD_UPLL_FREQUENCY /* To be provided */
/* HSMCI clocking
*