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TMS570: Does not have prioritized interrupts in the sense of other CPUs. Fix some compile errors when DEBUG is enabled

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This commit is contained in:
Gregory Nutt 2015-12-26 12:26:57 -06:00
parent d592b2824e
commit 1f2d9c9174
4 changed files with 7 additions and 32 deletions
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10
arch/arm/Kconfig
View File

@ -16,6 +16,7 @@ config ARCH_CHIP_A1X
select ARCH_HAVE_FPU
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_SDRAM
select BOOT_RUNFROMSDRAM
@ -157,6 +158,7 @@ config ARCH_CHIP_SAMA5
bool "Atmel SAMA5"
select ARCH_CORTEXA5
select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
@ -302,7 +304,6 @@ config ARCH_CORTEXM7
config ARCH_CORTEXA5
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
@ -310,7 +311,6 @@ config ARCH_CORTEXA5
config ARCH_CORTEXA8
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
@ -318,14 +318,12 @@ config ARCH_CORTEXA8
config ARCH_CORTEXR4
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR4F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
@ -333,14 +331,12 @@ config ARCH_CORTEXR4F
config ARCH_CORTEXR5
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEX5F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
@ -348,14 +344,12 @@ config ARCH_CORTEX5F
config ARCH_CORTEXR7
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR7F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE

2
arch/arm/src/tms570/tms570_boot.c
View File

@ -202,7 +202,7 @@ void arm_boot(void)
* to do that.
*/
DEBUGASSERT((getreg(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0);
DEBUGASSERT((getreg32(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0);
/* Clear all reset status flags on successful power on reset */

25
arch/arm/src/tms570/tms570_irq.c
View File

@ -289,7 +289,7 @@ void up_disable_irq(int channel)
uint32_t bitmask;
unsigned int regndx;
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS);
/* Offset to account for the "phantom" vector */
@ -321,7 +321,7 @@ void up_enable_irq(int channel)
uint32_t bitmask;
unsigned int regndx;
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS);
/* Offset to account for the "phantom" vector */
@ -363,7 +363,7 @@ void up_enable_fiq(int channel)
uint32_t bitmask;
unsigned int regndx;
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS);
/* Offset to account for the "phantom" vector */
@ -398,23 +398,4 @@ void up_enable_fiq(int channel)
void up_ack_irq(int irq)
{
#warning Missing logic
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int channel, int priority)
{
#warning Missing logic
}
#endif

2
arch/arm/src/tms570/tms570_lowputc.c
View File

@ -323,7 +323,7 @@ int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config)
gcr1 = (SCI_GCR1_TIMING | SCI_GCR1_CLOCK | SCI_GCR1_RXENA | SCI_GCR1_TXENA);
DEBUGASSERT(config->parity >= && config->parity <= 2);
DEBUGASSERT(config->parity >= 0 && config->parity <= 2);
if (config->parity == 1)
{
gcr1 |= SCI_GCR1_PARENA;